CN118072779A - Memory cell structure, control method thereof, array circuit and device, and electronic equipment - Google Patents

Memory cell structure, control method thereof, array circuit and device, and electronic equipment Download PDF

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CN118072779A
CN118072779A CN202410465665.3A CN202410465665A CN118072779A CN 118072779 A CN118072779 A CN 118072779A CN 202410465665 A CN202410465665 A CN 202410465665A CN 118072779 A CN118072779 A CN 118072779A
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transistor
magnetic memory
source line
memory
layer
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CN118072779B (en
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陈浩然
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Abstract

The invention relates to the technical field of memories, and discloses a memory calculation unit structure, a control method thereof, an array circuit, an array device and electronic equipment, wherein the memory calculation unit structure comprises: the first transistor and the second transistor are respectively connected with the first magnetic memory, and the third transistor and the fourth transistor are respectively connected with the second magnetic memory; the first magnetic memory and the second magnetic memory share a common electrode layer; the common electrode layer is connected with the reading source line. Therefore, the layout area of the two magnetic memory devices can be reduced, the process integration level is improved, the effective miniature integration of the array units can be realized, the complexity of the process structure is reduced, the two magnetic memories can write related data under the control of the transistor, the integrated memory and calculation function can be realized, the common electrode layer can output read current through the read source line, and the influence of voltage drop on the accuracy of an array circuit is reduced in the operation process.

Description

Memory cell structure, control method thereof, array circuit and device, and electronic equipment
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a memory unit structure, a control method thereof, an array circuit, an array device, and an electronic device.
Background
With the rapid development of artificial intelligence, the demand for computing power for various intelligent applications is also rapidly increasing. Conventional artificial intelligence chips typically use a von neumann architecture whose storage is separate from the computing unit, resulting in "power consumption wall", "storage wall" problems. To solve this problem, artificial intelligence chip architecture (i.e., architecture for in-memory computing) is applied, which is to put data into memory for computing in-situ to reduce the power consumption of the chip and to improve the computing performance.
In recent years, a circuit design scheme for performing in-memory calculation based on a nonvolatile memory has been attracting attention. The magnetic random access memory (Magnetic Random Access Memory, MRAM) has the characteristics of separation of a writing circuit and a reading circuit and nonvolatile storage data, so that the MRAM integrated memory chip has the characteristics of high speed, high energy efficiency and good reliability, thereby promoting the development of the magnetic integrated memory chip. However, the memory cell design based on a plurality of MRAM has a complex process structure, a large cell area, and cannot be effectively integrated in a miniature manner, and the output current is affected by voltage drop (IR drop) during operation, which is very easy to affect the accuracy of the output result.
Disclosure of Invention
In view of the above, the present invention aims to provide a memory cell structure, a control method thereof, an array circuit, a device and an electronic apparatus, which can reduce the layout area of a device, improve the process integration level, realize the effective micro integration of the array cell, and reduce the influence of voltage drop on the accuracy of the array circuit in the operation process.
In order to solve the above technical problems, the present invention provides a memory unit structure, including: a first transistor, a second transistor, a third transistor, a fourth transistor, and a mirror-symmetrical stacked structure composed of a first magnetic memory and a second magnetic memory;
the first transistor and the second transistor are respectively connected with the first magnetic memory; the third transistor and the fourth transistor are respectively connected with the second magnetic memory;
The first magnetic memory and the second magnetic memory share a common electrode layer; the common electrode layer is connected with the reading source line.
In a first aspect, in the above memory cell structure provided by the present invention, the mirror symmetry stacked structure includes a first heavy metal layer, a first free layer, a first tunneling insulating layer, a first reference layer, the common electrode layer, a second reference layer, a second tunneling insulating layer, a second free layer, and a second heavy metal layer that are stacked;
The first free layer, the first tunneling insulating layer and the first reference layer form a first magnetic tunnel junction; the second free layer, the second tunneling insulating layer and the second reference layer forming a second magnetic tunnel junction;
the first heavy metal layer, the first free layer, the first tunneling insulating layer, the first reference layer and the common electrode layer form the first magnetic memory;
the second heavy metal layer, the second free layer, the second tunneling insulating layer, the second reference layer and the common electrode layer constitute the second magnetic memory.
In the above memory cell structure provided by the present invention, on the other hand, the first transistor and the second transistor are respectively connected to the first heavy metal layer;
the third transistor and the fourth transistor are respectively connected with the second heavy metal layer.
On the other hand, in the above-mentioned memory cell structure provided by the present invention, the two ends of the first heavy metal layer far away from the first free layer side are distributed with a first electrode and a second electrode;
And a third electrode and a fourth electrode are distributed at two ends of one side of the second heavy metal layer, which is far away from the second free layer.
In the above memory cell structure, the drain of the first transistor and the drain of the second transistor are connected to the first electrode, respectively;
The drain electrode of the third transistor is connected with the third electrode respectively;
The second electrode is connected with the fourth electrode.
In the above memory cell structure, the source of the first transistor, the source of the second transistor, and the source of the third transistor and the source of the fourth transistor are connected to a bit line, respectively.
In the above memory cell structure according to the present invention, the second electrode and the fourth electrode are connected to a write source line, respectively.
On the other hand, in the above-mentioned memory cell structure provided by the present invention, one end of the read source line is connected with a switch transistor at the read source line; one end of the writing source line is connected with a switching transistor at the writing source line.
In the above memory cell structure, the first transistor and the switching transistor at the write source line are turned on, the second transistor, the third transistor, the fourth transistor and the switching transistor at the read source line are turned off, and when the bit line is excited by the applied voltage, the injection current flows out of the switching transistor at the write source line through passing through the first heavy metal layer in parallel, so as to complete the data writing of the first magnetic memory.
In the above memory cell structure, the third transistor and the switching transistor at the write source line are turned on, the first transistor, the second transistor, the fourth transistor and the switching transistor at the read source line are turned off, and when the bit line is excited by the applied voltage, the injection current flows out of the switching transistor at the write source line through parallel passing through the second bimetal layer, so as to complete the data writing of the second magnetic memory.
In the above memory cell structure, the second transistor, the fourth transistor, and the switching transistor at the read source line are turned on, the first transistor, the third transistor, and the switching transistor at the write source line are turned off, and when the bit line is excited by the applied voltage, the current is converged at the common electrode layer and is output through the switching transistor at the read source line.
In the above memory cell structure, the gate of the first transistor, the gate of the second transistor, and the gates of the third transistor and the fourth transistor are connected to a word line, respectively.
In another aspect, in the above memory cell structure provided by the present invention, the word lines include a write word line and a read word line;
the switching states of the first transistor and the third transistor are controlled by the write word line;
the switching states of the second transistor and the fourth transistor are controlled by the read word line.
In the above-mentioned memory cell structure, when the weight parameter stored in the first magnetic memory is a positive weight and the weight parameter stored in the second magnetic memory is a negative weight, the calculation formula corresponding to the current value output by the read source line is:
；
wherein, For the current value output by the reading source line,/>A positive weight stored for the first magnetic memory,Negative weights stored for the second magnetic memory,/>For positive voltage excitation input from the bit line when the second transistor is on,/>For negative voltage excitation input from the bit line when the fourth transistor is on,/>For the influence of the resistance of the wires in the circuit on the current when the second transistor is turned on,/>The effect of the resistance of the wire in the line on the current when the fourth transistor is turned on.
In the above-mentioned memory cell structure, when the weight parameters stored in the first magnetic memory and the second magnetic memory are in a state of no positive and negative weights, the calculation formula corresponding to the current value output by the read source line is:
；
wherein, For the current value output by the reading source line,/>The weights stored for the first magnetic memory,Weights stored for the second magnetic memory,/>Exciting a voltage input from the bit line when the second transistor is on,/>Exciting a voltage input from the bit line when the fourth transistor is on,/>For the influence of the resistance of the wires in the circuit on the current when the second transistor is turned on,/>The effect of the resistance of the wire in the line on the current when the fourth transistor is turned on.
In order to solve the above technical problem, the present invention further provides a control method of a storage unit structure, including:
When a data writing operation is carried out on the first magnetic memory, a first transistor and a switching transistor at a writing source line are turned on, a second transistor, a third transistor, a fourth transistor and a switching transistor at a reading source line are turned off, voltage excitation is provided through a bit line, injection current flows out of the switching transistor at the writing source line through a first heavy metal layer which passes through the first magnetic memory in parallel, and data writing of the first magnetic memory is completed;
When the data writing operation is carried out on the second magnetic memory, the third transistor and the switching transistor at the writing source line are turned on, the first transistor is turned off, the second transistor, the fourth transistor and the switching transistor at the reading source line are provided with voltage excitation through the bit line, and the injection current flows out of the switching transistor at the writing source line through the second heavy metal layer which passes through the second magnetic memory in parallel, so that the data writing of the second magnetic memory is completed.
On the other hand, the control method of the storage unit structure provided by the invention further comprises the following steps:
When data reading operation is carried out, the second transistor is started, the fourth transistor and the switching transistor at the reading source line are closed, the first transistor is closed, the third transistor and the switching transistor at the writing source line are provided with voltage excitation through the bit line, current respectively passes through the first magnetic tunnel junction of the first magnetic memory and the second magnetic tunnel junction of the second magnetic memory, and current is converged at the common electrode layer and is output through the switching transistor at the reading source line.
In order to solve the above technical problems, the present invention further provides an array circuit, which includes a plurality of the memory cell structures provided by the present invention in an array arrangement.
In order to solve the technical problem, the invention also provides an array device which comprises the array circuit and a peripheral circuit connected with the array circuit.
In order to solve the technical problems, the invention also provides electronic equipment, which comprises the array device provided by the invention.
As can be seen from the above technical solution, the memory unit structure provided by the present invention includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a mirror-symmetrical stacked structure composed of a first magnetic memory and a second magnetic memory; the first transistor and the second transistor are respectively connected with the first magnetic memory; the third transistor and the fourth transistor are respectively connected with the second magnetic memory; the first magnetic memory and the second magnetic memory share a common electrode layer; the common electrode layer is connected with the reading source line.
The memory unit structure provided by the invention has the beneficial effects that the two magnetic memories are subjected to mirror symmetry lamination design, and the two magnetic memories share the common electrode layer, so that the layout area of two magnetic memory devices can be reduced, the process integration level is improved, the effective miniature integration can be realized when a plurality of memory unit structure design array units are used, the complexity of the process structure is reduced, each magnetic memory is respectively connected with two transistors, under the control of the transistors, the two magnetic memories can write related data, the memory integrated function can be realized, and the common electrode layer can output read current through the read source line, so that the influence of voltage drop on the array circuit precision is reduced in the operation process, the purposes of higher complexity of the process structure based on a plurality of traditional memory unit structures, higher influence of the unit area on the memory circuit computing circuit, the development capability of the memory circuit is easy to generate, the application of the circuit design is further improved, and the application of the intelligent chip is facilitated, and the development capability of the intelligent memory device is further improved.
In addition, the invention also provides a corresponding control method, an array circuit, an array device and electronic equipment for the memory calculation unit structure, which have the same or corresponding technical characteristics as the memory calculation unit structure, so that the memory calculation unit structure has higher practicability.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a memory unit structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a stacked structure of mirror symmetry in a memory cell structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a memory cell structure with mirror symmetry, a transistor, and external connections according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an array circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array device according to an embodiment of the present invention.
Wherein T1 is a first transistor, T2 is a second transistor, T3 is a third transistor, T4 is a fourth transistor, T5 is a switching transistor at a read source line, T6 is a switching transistor at a write source line, M1 is a first magnetic memory, M2 is a second magnetic memory, 10 is a mirror-symmetrical stacked structure, 20 is a common electrode layer, 21 is a first heavy metal layer, 22 is a first free layer, 23 is a first tunneling insulating layer, 24 is a first reference layer, 25 is a second reference layer, 26 is a second tunneling insulating layer, 27 is a second free layer, 28 is a second heavy metal layer, 201 is a first electrode, 202 is a second electrode, 203 is a third electrode, 204 is a fourth electrode, 30 is a read source line, 40 is a bit line, 50 is a write source line, 61 is a read word line corresponding to a positive weight parameter, 62 is a read word line corresponding to a negative weight parameter, 63 is a write word line corresponding to a negative weight parameter, 64 is a write word corresponding to a negative weight parameter.
Detailed Description
Conventional artificial intelligence chips use a von neumann architecture whose storage is separate from the computing unit, i.e., data needs to be transferred back and forth frequently between the processing unit and the storage unit, resulting in problems of power consumption walls and storage walls. While in-memory computing (Computing In Memory, CIM or Process In Memory, PIM) architecture can solve this problem, it can place data in-situ in memory for computing, reducing power consumption of the chip while improving computing performance. Circuit designs for in-Memory computation based on Non-Volatile Memory (NVM), such as magnetic random access Memory (Magnetic Random Access Memory, MRAM), resistive random access Memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM), phase change random access Memory (PHASE CHANGE MATERIA, PCM), and the like, have received much attention. Among them, spin-Orbit Torque magnetic random access memory (Spin-Orbit Torque MRAM, SOT-MRAM) is a third generation magnetic memory, and has a great advantage in performance over previous generation Spin-transfer Torque magnetoresistive magnetic random access memory (SPIN TRANSFER Torque MRAM, STT-MRAM). However, the array unit has a complex process structure and a large unit area, and the circuit precision for in-memory calculation still faces the problems of voltage drop influence and the like, and is still a technical difficulty which is paid attention to in the field.
Based on the above, the invention provides a memory calculation unit structure, which can solve the problems that the process structure based on a plurality of memory calculation unit structures is complex, the unit area is large, and the voltage drop of a memory calculation circuit is easy to generate to influence the circuit precision.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. Fig. 1 is a schematic diagram of a memory unit structure according to an embodiment of the present invention. As shown in fig. 1, includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a mirror-symmetrical stacked structure 10 consisting of a first magnetic memory M1 and a second magnetic memory M2;
The first transistor T1 and the second transistor T2 are connected to the first magnetic memory M1, respectively; the third transistor T3 and the fourth transistor T4 are respectively connected to the second magnetic memory M2;
the first magnetic memory M1 and the second magnetic memory M2 share one common electrode layer 20; the common electrode layer 20 is connected to a Read Source Line (RSL) 30.
In the above-mentioned memory cell structure provided in the embodiment of the present invention, two magnetic memories M1 and M2 are designed in a mirror symmetry lamination manner, and the two magnetic memories M1 and M2 share a common electrode layer 20, so that the layout area of the two magnetic memories M1 and M2 can be reduced, the process integration level is improved, and when a plurality of memory cell structures are used to design an array cell, effective miniaturization integration can be realized, the complexity of the process structure is reduced, and the first transistor T1 and the second transistor T2 are respectively connected with the first magnetic memory M1; the third transistor T3 and the fourth transistor T4 are respectively connected with the second magnetic memory M2, under the control of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can enable the two magnetic memories M1 and M2 to write related data, so that a calculation integrated function can be realized, and the common electrode layer 20 is connected with the read source line 30, and can output a read current through the read source line 30, so that in the operation process, the output current in an array circuit formed by the calculation unit structure is reduced, the influence of voltage drop on the accuracy of the array circuit is reduced, the purpose of improving the calculation accuracy of the circuit is achieved, the problem that the process structure based on a plurality of traditional calculation unit structures is complex, the unit area is large, and the calculation circuit is easy to generate voltage drop to influence the accuracy of the circuit is solved, further the design of optimizing the device structure of the chip bottom layer is facilitated, the calculation capability and the storage capability are further improved, and the development and the application of the artificial intelligence technology are promoted.
It should be noted that the above-mentioned memory cell structure provided by the present invention may include a 4T2M (Four Transistor Two Magnetoresistive Memory Cell) structure, where the 4T2M is composed of four transistors and two magnetic memories, i.e., a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first magnetic memory M1 and a second magnetic memory M2; the first magnetic memory M1 and the second magnetic memory M2 are in a mirror symmetry lamination design, and the layout area of the two magnetic memory devices can be reduced to one size by the structure.
It should be added that the above-mentioned 4T 2M-based memory cell structure is characterized in that the first magnetic memory M1 and the second magnetic memory M2 are designed in a mirror image lamination manner, so that the characteristics of the magnetic memories prepared in the subsequent process of the complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, COMS) process are fully utilized from the device process structure, and the layout area of the two magnetic memory devices is reduced.
That is, the above-mentioned 4T 2M-based memory cell structure is composed of two 2T1M (Two Transistor One Magnetoresistive Memory Cell) units sharing a common electrode layer 20, and the two magnetic memories are mirror-image stacked, so that the two magnetic memories are fabricated in the same CMOS subsequent process step, and the electrodes of the two magnetic memories can be connected with the through holes and the metal layer in the subsequent process. The two magnetic memories output current through the common electrode layer 20.
On the basis of the 4T 2M-based memory unit structural design, the first magnetic memory M1 and the second magnetic memory M2 can respectively store weight parameters in a neural network algorithm; the two weight parameters are respectively a positive weight state and a negative weight state, or are both in a state without positive and negative weights.
That is, positive and negative weights (the weight values of the finger map have positive and negative signs, and the conductance values thereof are still positive) are respectively stored in the upper and lower magnetic memories in the 4T 2M-based memory cell structure, or no positive and negative weights are stored. For example: the first magnetic memory M1 may store parameters of a positive weight state in the neural network algorithm, and the second magnetic memory M2 may store parameters of a negative weight state in the neural network algorithm; or, the first magnetic memory M1 may store parameters of a negative weight state in the neural network algorithm, and the second magnetic memory M2 may store parameters of a positive weight state in the neural network algorithm; alternatively, the first magnetic memory M1 and the second magnetic memory M2 may each store parameters of the neural network algorithm without the positive and negative weight states. The above storage increases the weight state range.
The above-described memory cell structure may be used to perform a convolution operation (or a matrix vector operation, or a multiply-accumulate operation) according to the mirror stack design of the first magnetic memory M1 and the second magnetic memory M2 and the weight parameters stored in the first magnetic memory M1 and the second magnetic memory M2. In the operation of the above-described memory cell structure, the operation result is obtained by reading the current output from the source line 30 from the common electrode layer 20. For example: the above-mentioned memory unit structure carries on the multiply-accumulate operation in the neural network algorithm; the result of the multiply-accumulate operation may be obtained by the current output from the common electrode layer 20. Therefore, the positive and negative weights of the neural network algorithm are stored in the array circuit based on the memory cell structure, and the output current in the array circuit can be further reduced, so that the influence of the voltage drop of the array circuit on the circuit precision is further reduced.
Therefore, the invention not only can reduce the area of the magnetic memory device in the layout and realize the integrated function of memory calculation by reasonably planning the process structure of the magnetic memory in the 4T2M circuit and complete convolution operation, but also can realize the effects of reducing the output current, reducing the influence of the voltage drop of the array circuit and improving the circuit precision while being compatible with the algorithm with positive and negative weights.
In a possible implementation manner, in the above memory cell structure provided by the embodiment of the present invention, the first magnetic memory M1 and the second magnetic memory M2 may be spin-orbit-torque magnetic random access memories. Of course, the types of the magnetic memory M1 and the second magnetic memory M2 may be other nonvolatile memories, such as a spin transfer torque magnetoresistive magnetic random access memory, which may be determined according to practical situations, and are not limited herein.
Further, in a specific implementation, in the above memory cell structure provided by the embodiment of the present invention, the mirror symmetry stacked structure 10 may include a first heavy metal layer, a first free layer, a first tunneling insulating layer, a first reference layer, a common electrode layer, a second reference layer, a second tunneling insulating layer, a second free layer, and a second heavy metal layer that are stacked;
A first free layer, a first tunneling insulating layer and a first reference layer forming a first magnetic tunnel junction; a second free layer, a second tunneling insulating layer and a second reference layer forming a second magnetic tunnel junction;
The first heavy metal layer, the first free layer, the first tunneling insulating layer, the first reference layer and the common electrode layer form a first magnetic memory M1;
the second heavy metal layer, the second free layer, the second tunneling insulating layer, the second reference layer and the common electrode layer constitute a second magnetic memory M2.
Fig. 2 is a schematic diagram of a stacked structure with mirror symmetry in a memory cell structure according to an embodiment of the present invention. As shown in fig. 2, the mirror-symmetrical stacked structure 10 may include a first heavy metal layer 21, a first free layer 22, a first tunneling insulating layer 23, a first reference layer 24, a common electrode layer 20, a second reference layer 25, a second tunneling insulating layer 26, a second free layer 27, and a second heavy metal layer 28, which are stacked from top to bottom. That is, the mirror stacked structure 10 composed of the first magnetic memory M1 and the second magnetic memory M2 includes one common electrode layer 20, two mirror heavy metal layers (also referred to as coupling layers), two mirror free layers (FREE LAYER, which may be ferromagnetic free layers), two mirror tunneling insulating layers, and two mirror reference layers (REFERENCE LAYER, which may be referred to as pinning layers (PINNING LAYER)).
Wherein the first magnetic tunnel junction of the first magnetic memory M1 is formed by the first free layer 22, the first tunneling insulating layer 23 and the first reference layer 24. The second magnetic tunnel junction of the second magnetic memory M2 is formed by the second free layer 27, the second tunnel insulating layer 26 and the second reference layer 25. And, the first magnetic memory M1 is composed of a first heavy metal layer 21, a first free layer 22, a first tunneling insulating layer 23, a first reference layer 24 and a common electrode layer 20; the second magnetic memory M2 is composed of a second heavy metal layer 28, a second free layer 27, a second tunneling insulating layer 26, a second reference layer 25 and a common electrode layer 20.
In implementation, the first magnetic memory M1 and the second magnetic memory M2 may be disposed in a vertical structure, and the first magnetic memory M1 located at the upper portion and the second magnetic memory M2 located at the lower portion may have a mirror-symmetrical structure. The main structure of the first magnetic memory M1 positioned at the upper part is as follows from top to bottom: a first heavy metal layer 21, a first free layer 22, a first tunneling insulating layer 23, a first reference layer 24, and a common electrode layer 20. The main structure of the first magnetic memory M2 positioned at the lower part is as follows from bottom to top: a second heavy metal layer 28, a second free layer 27, a second tunneling insulating layer 26, a second reference layer 25, and a common electrode layer 20. In the subsequent process of the CMOS process for preparing the magnetic memory, the common electrode layer 20 of the first magnetic memory M1 and the second magnetic memory M2 are formed in a mirror-symmetrical structure.
It should be noted that the first free layer 22, the second free layer 27, the first reference layer 24 and the second reference layer 25 may use, but are not limited to, the following magnetic materials: one or more compounds such as iron palladium (FePd), cobalt palladium (CoPd), cobalt iron boron (CoFeB), cobalt iron aluminum (Co 2 FeAl), cobalt (Co), cobalt iron (CoFe), iron germanium tellurium (Fe 3GeTe2), nickel germanium tellurium (Ni 3GeTe2), and the like. The first tunneling insulating layer 23 and the second tunneling insulating layer 26 may use, but are not limited to, the following materials: magnesium oxide (MgO), aluminum oxide (AlO x), hafnium disulfide (HfO 2), and the like. The first heavy metal layer 21 and the second heavy metal layer 28 may use, but are not limited to, the following materials: one or more heavy metal alloys such as tungsten (W), iridium (Ir), and tantalum (Ta).
Further, in the above-mentioned memory cell structure provided in the embodiment of the present invention, the first transistor T1 and the second transistor T2 may be connected to the first heavy metal layer 21, respectively; the third transistor T3 and the fourth transistor may be connected to the second heavy metal layer 28, respectively.
Fig. 3 is a schematic diagram of a mirror-symmetrical stacked structure, a transistor, and an external connection in a memory cell structure according to an embodiment of the present invention. As shown in fig. 3, the first transistor T1 and the second transistor T2 are connected to the first heavy metal layer 21 on the upper surface of the first magnetic memory M1 located at the upper portion; the third transistor T3 and the fourth transistor T4 are connected to the second heavy metal layer 28 located at the lower surface of the second magnetic memory M2.
Further, in the embodiment of the present invention, as shown in fig. 2, in the above-mentioned memory cell structure, two ends of the first heavy metal layer 21 on the side far away from the first free layer 22 are distributed with a first electrode 201 and a second electrode 202; the second heavy metal layer 28 has a third electrode 203 and a fourth electrode 204 distributed at two ends of the side far away from the second free layer.
In practice, the first electrode 201 and the second electrode 202 may be distributed at two bottom electrodes at both ends of the first heavy metal layer 21. The third electrode 203 and the fourth electrode 204 may be distributed at two bottom electrodes at both ends of the second heavy metal layer 22.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, the drain electrode of the first transistor T1 and the drain electrode of the second transistor T2 are respectively connected to the first electrode 201; a drain electrode of the third transistor T3, and a drain electrode of the fourth transistor T4 are connected to the third electrode 203, respectively; the second electrode 202 is connected to the fourth electrode 204.
In implementation, in the 4TM2 structure, the drain of the first transistor T1 and the drain of the second transistor T2 are connected to the first electrode 201 at one end of the heavy metal layer of the first magnetic memory M1 located on the upper portion to form a 2T1M structure; the drain electrode of the third transistor T3 and the drain electrode of the fourth transistor T4 are connected to the third electrode 203 at one end of the heavy metal layer of the second magnetic memory M2 located below to form a 2T1M structure. The second electrode 202 of the first magnetic memory M1 located at the upper portion is connected to the fourth electrode 204 of the second magnetic memory M2 located at the lower portion. Finally, since the first magnetic memory M1 located at the upper portion is mirror-symmetrical to the second magnetic memory M2 located at the lower portion, the intermediate electrode is provided as the common electrode layer 20.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, the source of the first transistor T1, the source of the second transistor T2, the source of the third transistor T3 and the source of the fourth transistor T4 are respectively connected to the Bit Line (BL) 40.
As shown in fig. 3, the source of the first transistor T1, the source of the second transistor T2, the source of the third transistor T3 and the source of the fourth transistor T4, which are arranged in each column, may be connected through separate bit lines 40, respectively. When the first transistor T1 is turned on, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off, the voltage stimulus is applied to the bit line 40, and the data writing in the first magnetic memory M1 can be completed. The third transistor T3 is turned on, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off, and the data writing of the second magnetic memory M2 can be completed by applying voltage excitation to the bit line 40.
In a specific implementation, in the above memory cell structure provided in the embodiment of the present invention, the second electrode 202 and the fourth electrode 204 are connected to the write source line (Write Source Line, WSL) 50, respectively.
Further, in the above-mentioned memory cell structure provided in the embodiment of the present invention, one end of the read source line 30 is connected to the switch transistor T5 at the read source line; one end of the write source line 50 is connected to a switching transistor T6 at the write source line.
In implementation, the source of the switching transistor T5 at the read source line is connected to one end of the read source line 30, and when the switching transistor T5 at the read source line is in an on state, the current output by the read source line 30 may flow out from the drain of the switching transistor T5 at the read source line. The source of the switching transistor T6 at the write source line is connected to one end of the write source line 50, and when the switching transistor T6 at the write source line is in an on state, an injection current passes through the first heavy metal layer 21 or the second heavy metal layer 28 in parallel, and then the current flows out from the drain of the switching transistor T6 at the write source line through the write source line 50.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, the first transistor T1 and the switching transistor T6 at the write source line are turned on, the second transistor T2, the third transistor T3, the fourth transistor T4 and the switching transistor T5 at the read source line are turned off, and when the bit line is excited by the applied voltage, the injection current flows out from the switching transistor T6 at the write source line through the first heavy metal layer 21 in parallel to complete the data writing of the first magnetic memory M1.
In practice, by applying a voltage stimulus to the bit line 40 connected to the source of the first transistor T1, a horizontal current is generated through the first heavy metal layer 21 of the first magnetic memory M1, which reverses the magnetization direction of the first free layer 22 under the interaction of the spin-orbit coupling effect (Rashba), the spin hall effect, and when the magnetization direction of the first free layer 22 coincides with the magnetization direction of the first reference layer 24, the first magnetic tunnel junction resistance assumes a low resistance state, and is often considered to write binary data "0", and when the magnetization direction of the first free layer 22 is opposite to the magnetization direction of the first reference layer 24, the first magnetic tunnel junction resistance assumes a high resistance state, and is often considered to write binary data "1". For the above writing of binary data, the purpose of writing the weight parameters into the first magnetic memory M1 is considered to be achieved.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, the third transistor T3 and the switching transistor T6 at the write source line are turned on, the first transistor T1, the second transistor T2, the fourth transistor T4 and the switching transistor T5 at the read source line are turned off, and when the bit line 40 is energized by the voltage, the injection current flows from the switching transistor T6 at the write source line through the second heavy metal layer 28 in parallel to complete the data writing of the second magnetic memory M2.
In practice, by applying a voltage stimulus to the bit line 40 connected to the source of the third transistor T3, a horizontal current is generated through the second heavy metal layer 28 of the second magnetic memory M2, which, under the interaction of the spin-orbit coupling effect and the spin hall effect, reverses the magnetization direction of the second free layer 27, and when the magnetization direction of the second free layer 27 coincides with the magnetization direction of the second reference layer 25, the second magnetic tunnel junction resistance assumes a low resistance state, and is often considered to write binary data "0", and when the magnetization direction of the second free layer 27 is opposite to the magnetization direction of the second reference layer 25, the second magnetic tunnel junction resistance assumes a high resistance state, and is often considered to write binary data "1". For the above writing of binary data, it is considered that the purpose of writing the weight parameters into the second magnetic memory M2 is thereby achieved.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, the second transistor T2, the fourth transistor T4 and the switching transistor T5 at the read source line are turned on, the first transistor T1, the third transistor T3 and the switching transistor T6 at the write source line are turned off, and when the bit line 40 is excited by the voltage, the current is converged at the common electrode layer 20 through the first magnetic tunnel junction and the second magnetic tunnel junction, respectively, and is outputted through the switching transistor T5 at the read source line.
In implementation, by applying voltage excitation to the bit line 40 connected to the source of the second transistor T2, a current is generated through the first heavy metal layer 21, the first free layer 22, the first tunneling insulating layer 23, the first reference layer 24 and the common electrode layer 20 of the first magnetic memory M1, and finally the current is output through the read source line connected to the common electrode layer 20, thereby achieving the purpose of outputting the read current of the first magnetic memory M1.
Similarly, by applying voltage excitation to the bit line 40 connected to the source of the fourth transistor T4, a current is generated through the second heavy metal layer 28, the second free layer 27, the second tunneling insulating layer 26, the second reference layer 25 and the common electrode layer 20 of the second magnetic memory M2, and finally the current is outputted through the read source line connected to the common electrode layer 20, thereby achieving the purpose of outputting the read current of the second magnetic memory M2.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3 and the gate of the fourth transistor T4 are respectively connected to the word line (WRITE LINE, WL). Wherein the word lines may include a write word line (READ WRITE LINE, WWL) and a read word line (READ WRITE LINE, RWL); the switching states of the first transistor T1 and the third transistor T3 are controlled by the write word line; the switching states of the second transistor T2 and the fourth transistor T4 are controlled by the read word line.
In implementation, the gates of all the above transistors are connected by separate word lines, for example, one write word line is used to connect all the first transistors T1 arranged in each row, another write word line is used to connect all the third transistors T3 arranged in each row, one read word line is used to connect all the second transistors T2 arranged in each row, and another read word line is used to connect all the fourth transistors T4 arranged in each row. That is, when it is necessary to write data to the first magnetic memory M1, the first transistor T1 is turned on through the write word line. When data needs to be written into the second magnetic memory M2, the third transistor T3 is turned on through the write word line. When data needs to be read in the first magnetic memory M1, the second transistor T2 is turned on by the read word line. When data needs to be read in the second magnetic memory M2, the fourth transistor T4 is turned on by the read word line.
It should be noted that the above-mentioned memory cell structure provided in the embodiment of the present invention may be used in an array structure to implement a neural network algorithm. The first magnetic memory M1 and the second magnetic memory M2 can respectively store algorithm weight parameters through mapping, the weight parameters can be designed to be weight parameters with positive and negative signs, or can be weight parameters without signs, and the weight parameters are written into the first magnetic memory M1 and the second magnetic memory M2 in the manner described above. The in-memory calculation method can be used to read out the currents from the first magnetic memory M1 and the second magnetic memory M2 simultaneously in the above-described manner, and the read current is output from the common electrode layer 20, where the output read current is the sum of the read currents of the first magnetic memory M1 and the second magnetic memory M2, and the output read current completes the multiply-accumulate operation (in-memory calculation).
In practical application, when the magnetic memory in the traditional memory cell structure writes data, the injection current direction enters from one electrode at the lower part and passes through the heavy metal layer to be output from the other electrode at the lower part; when reading data, the reading current passes through the upper electrode layer, passes through the magnetic tunnel junction and the heavy metal layer and is output by the other electrode at the lower part: when the reading voltage is fixed, the reading current is larger when the magnetic tunnel junction is in a low resistance state, and the reading current is smaller when the magnetic tunnel junction is in a high resistance state, so that data stored in the corresponding magnetic memory are obtained. When the memory cell structure in the memory integrated technology is applied to an array circuit, the array circuit contains a large number of scattered memory cell structures, and cannot be effectively integrated in a miniature way; in addition, the external writing circuit and the external reading circuit are separated, the circuit is complex, and when the neural network convolution operation is carried out, the output current has the problem of voltage drop, and the accuracy of the output result is easily influenced. The memory unit structure provided by the invention comprises an upper magnetic memory and a lower magnetic memory, wherein the middle is separated by the common electrode layer 20, and the first magnetic memory M1 positioned at the upper part and the second magnetic memory M2 positioned at the lower part can realize the functions of data writing and reading.
The above-mentioned memory cell structure provided by the invention can realize the functions of two 2T1M memory cells, and mainly comprises a mirror symmetry lamination structure 10, a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; the external wiring structure comprises a bit line 40, a read source line 30, a write source line 50, a switch transistor T5 at the read source line and a switch transistor T6 at the write source line. The first transistor T1 and the second transistor T2 are respectively connected to the first electrode 201 of the mirror symmetry stacked structure 10 (the first electrode, the second electrode, the third electrode and the fourth electrode are not emphasized and shown in the schematic diagram, and only the connection relationship is shown), and the second electrode 202 is connected to the write source line 42; the third transistor T3 and the fourth transistor T4 are respectively connected to the third electrode 203 of the mirror-symmetrical stacked structure 10, and the fourth electrode 204 is connected to the read source line 41.
The memory cell structure and the external connection provided by the invention can finish the writing operation and the reading operation of the upper and the lower magnetic memories of the mirror symmetry lamination structure 10 respectively. The specific data writing operation steps are as follows:
When the data writing operation is performed on the first magnetic memory M1 of the mirror symmetry stacked structure 10, the first transistor T1 and the switching transistor T6 at the writing source are turned on, the rest of transistors are turned off, voltage excitation is provided through the bit line 40, the injection current flows out of the switching transistor T6 at the writing source line through passing through the first heavy metal layer 21 in parallel, and the magnetization direction of the first free layer 22 is turned over, so that binary data "0" or "1" is written correspondingly. When the second magnetic memory M2 of the mirror symmetry lamination structure 10 is subjected to data writing operation, the third transistor T3 and the switching transistor T6 at the writing source line are turned on, the rest of transistors are turned off, voltage excitation is provided through the bit line 40, and the injection current flows out of the switching transistor T6 at the writing source line by passing through the second heavy metal layer 28 in parallel, so that the magnetization direction of the second free layer 27 is turned over, and binary data "0" or "1" is written correspondingly. The bit width of the bit line 40 can be set according to the neural network algorithm, and the bit width is changed and modified without departing from the spirit and scope of the present disclosure.
The write operation described above may enable the mapping of the neural network algorithm weight parameters into the magnetic memory. When the multiply-accumulate operation in the neural network algorithm is performed, that is, the data reading operation of the above-mentioned memory cell structure provided by the present invention, the current result output by the reading source line 30 obtains the obtained multiply-accumulate operation result.
The specific data reading operation steps are as follows:
The second transistor T2, the fourth transistor T4, the switching transistor T5 at the read source line are turned on, the remaining transistors are turned off, voltage excitation is provided by the bit line 40, and current is converged at the middle common electrode layer 20 through the first magnetic tunnel junction of the first magnetic memory M1 and the second magnetic tunnel junction of the second magnetic memory M2 of the mirror symmetry layered structure 10, respectively, and current is outputted through the switching transistor T5 at the read source line. The current can be used as a multiplication and accumulation operation result to be converted into voltage signals by other circuits such as a current-voltage converter, an analog-digital signal converter and the like for processing by other circuits.
The data reading operation finally utilizes ohm law and kirchhoff law to complete multiply-accumulate operation in a neural network algorithm, weight data of the multiply-accumulate operation are stored in the upper part and the lower part of the mirror symmetry laminated structure 10, and meanwhile, the operation process occurs in situ in a magnetic memory, so that the characteristic of a typical memory-calculation integrated technology is achieved.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, when the weight parameter stored in the first magnetic memory M1 is a positive weight and the weight parameter stored in the second magnetic memory M2 is a negative weight, the calculation formula corresponding to the current value output by the read source line 30 may be:
；（1）
wherein, For reading the current value output by the source line 30,/>Positive weight stored for first magnetic memory M1,/>Negative weights stored for the second magnetic memory M2,/>For positive voltage excitation input from the bit line 40 when the second transistor T2 is on,/>For negative voltage stimulus input from the bit line 40 when the fourth transistor T4 is on,/>For the influence of the resistance of the wire in the line on the current when the second transistor T2 is turned on,/>The effect on the current caused by the resistance of the wire in the line when the fourth transistor T4 is turned on.
It should be noted that the first magnetic memory M1 of the mirror-symmetrical stacked structure 10 stores the weights of the neural network algorithmThe second magnetic memory M2 stores the weights/>, of the neural network algorithm. In the multiply-accumulate operation, the second transistor T2 is turned on by the read word line, and the full voltage stimulus/> is input from the bit line 40The effect of wire resistance on current in the line is noted as/>; By turning on the fourth transistor T4 on another read word line, a negative voltage stimulus/> is input from the bit line 40The effect of wire resistance on current in the line is noted as/>Finally, the operation result output by the memory cell structure is recorded as current/>，/>The operation formula of (2) is the above formula (1). Due to the symmetrical design of the mirror-symmetrical stacked structure 10, the sign of the operation is performed,/>It can be considered that the approach to zero and the final output current on the read source line 30 can obtain a more accurate value, and the symmetrical structure has simple process and easy realization, improves the circuit precision from the device level and reduces the complexity of circuit connection.
Further, in the above-mentioned memory cell structure according to the embodiment of the present invention, when the weight parameters stored in the first magnetic memory M1 and the second magnetic memory are in the non-positive and negative weight states, the calculation formula corresponding to the current value output by the read source line 30 may be:
；（2）
wherein, For reading the current value output by the source line 30,/>Weights stored for the first magnetic memory M1,/>Weights stored for the second magnetic memory M2,/>Is stimulated by the voltage input from bit line 40 when second transistor T2 is on,/>Is stimulated by the voltage input from bit line 40 when fourth transistor T4 is on,/>For the influence of the resistance of the wire in the line on the current when the second transistor T2 is turned on,/>The effect on the current caused by the resistance of the wire in the line when the fourth transistor T4 is turned on.
It should be noted that the first magnetic memory M1 of the mirror-symmetrical stacked structure 10 stores the weights of the neural network algorithmThe second magnetic memory M2 stores the weights/>, of the neural network algorithm. During multiply-accumulate operation, the second transistor T2 is turned on by the read word line, and voltage excitation/> is input from the bit lineThe effect of wire resistance on current in the line is noted as/>; By turning on the fourth transistor T4 on another read word line, voltage stimulus/>, is input from the bit lineThe effect of wire resistance on current in the line is noted as/>Finally, the operation result output by the storage unit structure is recorded as current，/>The operation formula of (2) is the above formula.
In the foregoing embodiments, the details of the memory unit structure are described, and based on the same inventive concept, the embodiments of the present invention further provide a control method, an array circuit, an apparatus, and a corresponding embodiment of an electronic device for the memory unit structure.
The control method of the memory unit structure provided in this embodiment specifically includes the following steps:
Firstly, when a data writing operation is carried out on a first magnetic memory, a first transistor and a switching transistor at a writing source line are turned on, a second transistor, a third transistor, a fourth transistor and a switching transistor at a reading source line are turned off, voltage excitation is provided through a bit line, injection current flows out of the switching transistor at the writing source line through a first heavy metal layer which passes through the first magnetic memory in parallel, and data writing of the first magnetic memory is completed;
then, when the data writing operation is performed on the second magnetic memory, the third transistor and the switch transistor at the writing source line are turned on, the first transistor, the second transistor, the fourth transistor and the switch transistor at the reading source line are turned off, voltage excitation is provided through the bit line, the injection current passes through the second heavy metal layer of the second magnetic memory in parallel, and flows out of the switch transistor at the writing source line, so that the data writing of the second magnetic memory is completed.
In the implementation, taking fig. 3 as an example, the first transistor T1 and the switching transistor T6 at the write source are turned on, the remaining transistors are turned off, voltage excitation is provided through the bit line 40, and the injection current flows out from the switching transistor T6 at the write source line through the first heavy metal layer 21 parallel to pass through the first magnetic memory M1, so as to complete the inversion of the magnetization direction of the first free layer 22, and correspondingly write binary data "0" or "1". In addition, the third transistor T3 and the switching transistor T6 at the write source line are turned on, the remaining transistors are turned off, voltage excitation is provided through the bit line 40, and the injection current flows out from the switching transistor T6 at the write source line through the second heavy metal layer 28 parallel to pass through the second magnetic memory M2, so that the magnetization direction of the second free layer 27 is inverted, and binary data "0" or "1" is written correspondingly.
In the control method of the memory cell structure provided by the embodiment of the invention, the related data can be written into the two magnetic memories by executing the steps, so that the memory integrated function can be realized, and in the operation process, the output current in the array circuit formed by the memory cell structure can be reduced, thereby reducing the influence of voltage drop on the accuracy of the array circuit, achieving the purpose of improving the calculation accuracy of the circuit, further improving the calculation capability and the storage capability, and promoting the development and application of artificial intelligence technology.
Since the embodiments of the control method portion and the embodiments of the storage unit structure portion correspond to each other, the embodiments of the control method portion are referred to the description of the embodiments of the storage unit structure portion, and are not repeated herein. And has the same advantageous effects as the above-mentioned memory cell structure.
Further, in a specific implementation, the method for controlling the storage unit structure according to the embodiment of the present invention may further include:
When data reading operation is carried out, the second transistor, the fourth transistor and the switching transistor at the reading source line are turned on, the first transistor is turned off, the third transistor and the switching transistor at the writing source line are provided with voltage excitation through the bit line, current respectively passes through the first magnetic tunnel junction of the first magnetic memory and the second magnetic tunnel junction of the second magnetic memory, current is converged at the common electrode layer, and current is output through the switching transistor at the reading source line.
In the implementation, taking fig. 3 as an example, the second transistor T2, the fourth transistor T4, the switching transistor T5 at the read source line are turned on, the remaining transistors are turned off, voltage excitation is provided through the bit line 40, and current flows through the first magnetic tunnel junction of the first magnetic memory M1 and the second magnetic tunnel junction of the second magnetic memory M2 of the mirror symmetry layered structure 10, respectively, and is converged at the middle common electrode layer 20, and current is outputted through the switching transistor T5 at the read source line. The current can be used as a multiplication and accumulation operation result to be converted into voltage signals by other circuits such as a current-voltage converter, an analog-digital signal converter and the like for processing by other circuits.
For more specific working procedures of the above steps, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
Based on the same inventive concept, the embodiment of the invention also provides an array circuit, which comprises a plurality of storage unit structures arranged in an array manner.
The array circuit provided by the embodiment of the invention comprises a plurality of memory cell structures arranged in an array, each memory cell structure can carry out mirror symmetry lamination design on two magnetic memories M1 and M2, and the two magnetic memories M1 and M2 share a common electrode layer 20, so that the layout area of the two magnetic memories M1 and M2 can be reduced, the process integration level is improved, the array circuit can realize effective miniature integration, the complexity of the process structure is reduced, and a first transistor T1 and a second transistor T2 in each memory cell structure are respectively connected with the first magnetic memory M1; the third transistor T3 and the fourth transistor T4 are respectively connected with the second magnetic memory M2, under the control of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can enable the two magnetic memories M1 and M2 to write related data, so that a calculation integrated function can be realized, and because the common electrode layer 20 is connected with the read source line 30, the common electrode layer 20 can output read current through the read source line 30, in the operation process, the output current in the array circuit is reduced, thereby reducing the influence of voltage drop on the accuracy of the array circuit, achieving the purpose of improving the calculation accuracy of the circuit, further being beneficial to optimizing the design of the device structure of the chip bottom layer, further improving the calculation capability and the storage capability, and promoting the development and the application of the artificial intelligence technology.
Fig. 4 is a schematic structural diagram of an array circuit according to an embodiment of the present invention. As shown in FIG. 4, the array circuit has the characteristic of integration of memory and calculation, and can realize multiply-accumulate operation commonly used in convolutional neural network algorithm. The array circuit can be understood as an array circuit for in-memory computation.
It should be noted that, the array circuit scale shown in fig. 4 is mxn, M, N is a positive integer greater than 1, that is, each row is provided with M4T 2M-based memory cell structures, and each column is provided with N4T 2M-based memory cell structures.
The following takes the neural network algorithm with positive and negative weights as an example of the array circuit, and the switching state of the transistor in the 4T 2M-based memory cell structure is controlled through the writing line and the reading line. As shown in fig. 4, the read word line 61 (rwl+), the write word line 62 (wwl+) and the write word line 64 (WWL-), and the read word line 63 (RWL-) control the switch states of the first transistor T1 and the third transistor T3, and the fourth transistor T4, respectively, of the memory cell structure, the write word line 61 (rwl+), the write word line 62 (wwl+), and the write word line 64 (WWL-), and the read word line 63 (RWL-) control the switch states of the third transistor T3 and the fourth transistor T4, respectively, of the upper and lower magnetic memories of the mirror-symmetrical stacked structure 10, and the multiply-accumulate operation output result can be accomplished by the data writing operation and the reading operation described above.
It is noted that the sign of the weight is mapped to the magnetic memory device itself, and the resistance (or conductance) is still physically positive.
In the array circuit provided by the invention, the first magnetic memory M1 of the mirror symmetry lamination structure 10 stores the positive weight of the neural network algorithm, which is recorded asThe second magnetic memory M2 stores the negative weights of the neural network algorithm, noted/>. The array circuit shown in FIG. 4, in performing the multiply-accumulate operation, at the 4T2M structure with coordinates (1, 1), takes the form of data reading described above, and inputs a positive voltage stimulus, denoted/>, from the corresponding multi-bit wide bit line 40 by turning on the second transistor T2 through the read word line 61 (RWL+) corresponding to the positive weight parameterThe effect of the resistance of the wire in the line on the current is recorded as; By turning on the fourth transistor T4 on the read word line 63 (RWL-) corresponding to the negative weight parameter, a negative voltage stimulus is input from BL of the corresponding multi-bit-width, denoted/>The effect of wire resistance on current in the line is noted as/>Finally, the operation result output by the 4T2M structure with the line resistance of the circuit being (1, 1) is recorded as current/>，/>The operation formula of (a) is as in the above formula (1).
Due to the symmetrical design of the mirror-symmetrical stacked configuration 10, when signed operations are performed,It can be considered that the approach to zero and the final output current on the read source line 30 can obtain a more accurate value, and the symmetrical structure has simple process and easy realization, improves the circuit precision from the device level and reduces the complexity of circuit connection. After the same calculation is completed on the 4T2M structures of the same first column, all the currents are collected on the read source line 30, and the output current value Σi is output to the next stage circuit through the on-state read source switching transistor T5.
It should be noted that, the current output by each 4T2M structure in the array circuit has been reduced by the multiply-accumulate operation with positive and negative weight signs, and the current value Σi finally converged on the read source line 30 is necessarily reduced compared with the multiply-accumulate operation without positive and negative weight signs, which clearly improves the design margin of the line width on the read source line 30 and reduces the pressure of the sum of all the current flows required to bear on the line.
The current value Σi finally collected on the read source line 30 is input to the next stage circuit, and can be continuously converted into a voltage signal through the next stage circuit modules such as a current-voltage converter, an analog-digital signal converter and the like, so as to become a voltage input signal of the next step of the neural network algorithm.
The following takes the neural network algorithm with no positive and negative weights as an example of the array circuit, and controls the switching state of transistors in the 4T 2M-based memory cell structure through the writing line and the reading line.
In the array circuit provided by the invention, the first magnetic memory M1 of the mirror symmetry lamination structure 10 stores the weight of the neural network algorithm, which is recorded asThe second magnetic memory M2 stores the weights of the neural network algorithm, noted as. In the multiplication and accumulation operation of the array circuit, at the 4T2M structure with the coordinates of (1, 1), the second transistor T2 is started through the read word line in the data reading mode, and voltage excitation is input from the bit line with the corresponding multi-bit width and recorded as/>The effect of wire resistance on current in the line is noted as/>; By turning on the fourth transistor T4 on another read word line, a voltage stimulus is input from the bit line corresponding to the multi-bit width, denoted/>The effect of wire resistance on current in the line is noted as/>Finally, the operation result output by the 4T2M structure with the line resistance of the circuit being (1, 1) is recorded as current/>，/>The operation formula of (2) is as described above.
After the same calculation is completed on the same 4T2M structures of the first column, all currents are collected on the read source line, and the output current value Σi is output to the next stage of circuit through the switch transistor T5 at the read source line in the on state. The above procedure may refer to most of the operation steps of the example of the array circuit using the neural network algorithm with positive and negative weights, and will not be described herein.
Since the principle of the array circuit for solving the problem is similar to that of the foregoing one memory cell structure, the embodiments of the array circuit portion and the embodiments of the memory cell structure portion correspond to each other, and thus, please refer to the description of the embodiments of the memory cell structure portion, and the repetition is omitted herein for brevity. And has the same advantageous effects as the above-mentioned memory cell structure.
Based on the same inventive concept, the embodiment of the invention also provides an array device, which comprises the array circuit and a peripheral circuit connected with the array circuit.
Further, in the implementation, in the array device provided by the embodiment of the invention, the peripheral circuit includes a bit line driving module, a word line driving module and an operation output processing module;
A word line driving module for transmitting signals to the word lines and applying stimulus;
the bit line driving module is used for writing in and reading out signals and applying various input signals;
And the operation output processing module is used for processing the signal before the next stage of circuit of the output signal.
Fig. 5 is a schematic structural diagram of an array device according to an embodiment of the present invention. As shown in fig. 5, the array device includes a possible array circuit and peripheral circuits required for performing the multiply-accumulate operation. The peripheral circuit may include: the device comprises a word line driving module, a bit line driving module, an operation output processing module and other driving modules; the word line driving module can finish the application of signals and excitation on various word lines; the bit line driving module can write in and read out signals and apply various input signals; the operation output processing module can process the signal before the next stage of circuit of the output signal; other driving modules can complete the control of other switching transistors and signals.
Since the principle of the array device for solving the problem is similar to that of the aforementioned array circuit, the embodiment of the array device portion corresponds to the embodiment of the array circuit portion, and the embodiment of the array circuit portion corresponds to the embodiment of the aforementioned memory cell structure portion, the embodiment of the array device is referred to the description of the embodiment of the aforementioned memory cell structure portion, and the repetition is omitted herein. And has the same advantageous effects as the above-mentioned memory cell structure.
Based on the same inventive concept, the embodiment of the invention also provides electronic equipment, which comprises the array device. Since the principle of the electronic device for solving the problem is similar to that of the aforementioned array device, the implementation of the electronic device can be referred to the implementation of the array device, and the repetition is omitted.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
Finally, it is also to be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprises," "comprising," and "having," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
For the foregoing embodiments, for simplicity of explanation, the same is shown as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or communication connection shown or discussed as being between each other may be an indirect coupling or communication connection between devices or elements via some interfaces, which may be in the form of telecommunications or otherwise.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
It will be apparent that the described embodiments are merely some, but not all, embodiments of the invention. Based on these embodiments, all other embodiments that may be obtained by one of ordinary skill in the art without inventive effort are within the scope of the invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art may still combine, add or delete features of the embodiments of the present invention or make other adjustments according to circumstances without any conflict, so as to obtain different technical solutions without substantially departing from the spirit of the present invention, which also falls within the scope of the present invention.
The memory unit structure, the control method, the array circuit, the device and the electronic equipment provided by the invention are described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, which are intended to be merely illustrative of the methods of the present invention and their core ideas and not limiting the scope of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (20)

1. A memory cell structure comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, and a mirror-symmetrical stacked structure composed of a first magnetic memory and a second magnetic memory;
the first transistor and the second transistor are respectively connected with the first magnetic memory; the third transistor and the fourth transistor are respectively connected with the second magnetic memory;
The first magnetic memory and the second magnetic memory share a common electrode layer; the common electrode layer is connected with the reading source line.
2. The memory cell structure of claim 1, wherein the mirror-symmetrical stacked structure comprises a stacked arrangement of a first heavy metal layer, a first free layer, a first tunneling insulating layer, a first reference layer, the common electrode layer, a second reference layer, a second tunneling insulating layer, a second free layer, and a second heavy metal layer;
The first free layer, the first tunneling insulating layer and the first reference layer form a first magnetic tunnel junction; the second free layer, the second tunneling insulating layer and the second reference layer forming a second magnetic tunnel junction;
the first heavy metal layer, the first free layer, the first tunneling insulating layer, the first reference layer and the common electrode layer form the first magnetic memory;
the second heavy metal layer, the second free layer, the second tunneling insulating layer, the second reference layer and the common electrode layer constitute the second magnetic memory.
3. The memory cell structure of claim 2, wherein the first transistor and the second transistor are each connected to the first heavy metal layer;
the third transistor and the fourth transistor are respectively connected with the second heavy metal layer.
4. The memory cell structure of claim 3, wherein a first electrode and a second electrode are distributed at two ends of the first heavy metal layer on a side away from the first free layer;
And a third electrode and a fourth electrode are distributed at two ends of one side of the second heavy metal layer, which is far away from the second free layer.
5. The memory cell structure of claim 4, wherein a drain of the first transistor and a drain of the second transistor are respectively connected to the first electrode;
The drain electrode of the third transistor is connected with the third electrode respectively;
The second electrode is connected with the fourth electrode.
6. The memory cell structure of claim 5, wherein a source of the first transistor, a source of the second transistor, a source of the third transistor, and a source of the fourth transistor are each connected to a bit line.
7. The memory cell structure according to claim 6, wherein the second electrode and the fourth electrode are connected to a write source line, respectively.
8. The memory cell structure of claim 7, wherein one end of the read source line is connected to a switching transistor at the read source line; one end of the writing source line is connected with a switching transistor at the writing source line.
9. The memory cell structure of claim 8, wherein the first transistor and the switching transistor at the write source line are turned on, the second transistor, the third transistor, the fourth transistor and the switching transistor at the read source line are turned off, and an injection current flows from the switching transistor at the write source line by passing through the first heavy metal layer in parallel when the bit line is energized by a voltage, to complete data writing of the first magnetic memory.
10. The memory cell structure of claim 9, wherein the third transistor and the switching transistor at the write source line are in an on state, the first transistor, the second transistor, the fourth transistor, and the switching transistor at the read source line are in an off state, and an injection current flows from the switching transistor at the write source line by passing through the second heavy metal layer in parallel when the bit line is energized by a voltage, to complete data writing of the second magnetic memory.
11. The memory cell structure of claim 10, wherein the second transistor, the fourth transistor, and the switching transistor at the read source line are in an on state, the first transistor, the third transistor, and the switching transistor at the write source line are in an off state, and wherein when the bit line is stimulated by an applied voltage, current flows through the first magnetic tunnel junction and the second magnetic tunnel junction, respectively, and is converged at the common electrode layer, and current is output through the switching transistor at the read source line.
12. The memory cell structure of claim 6, wherein a gate of the first transistor, a gate of the second transistor, a gate of the third transistor, and a gate of the fourth transistor are each connected to a word line.
13. The memory cell structure of claim 12, wherein the word lines comprise write word lines and read word lines;
the switching states of the first transistor and the third transistor are controlled by the write word line;
the switching states of the second transistor and the fourth transistor are controlled by the read word line.
14. The memory cell structure of claim 6, wherein when the weight parameter stored in the first magnetic memory is in a positive weight state and the weight parameter stored in the second magnetic memory is in a negative weight state, the calculation formula corresponding to the current value output by the read source line is:
；
wherein, For the current value output by the reading source line,/>Positive weight stored for the first magnetic memory,/>Negative weights stored for the second magnetic memory,/>For positive voltage excitation input from the bit line when the second transistor is on,/>For negative voltage excitation input from the bit line when the fourth transistor is on,/>For the influence of the resistance of the wires in the circuit on the current when the second transistor is turned on,/>The effect of the resistance of the wire in the line on the current when the fourth transistor is turned on.
15. The memory cell structure of claim 6, wherein when the weight parameters stored in the first magnetic memory and the second magnetic memory are in a state without positive and negative weights, a calculation formula corresponding to the current value output by the read source line is:
；
wherein, For the current value output by the reading source line,/>Weights stored for the first magnetic memory,/>Weights stored for the second magnetic memory,/>Exciting a voltage input from the bit line when the second transistor is on,/>Exciting a voltage input from the bit line when the fourth transistor is on,/>For the influence of the resistance of the wires in the circuit on the current when the second transistor is turned on,/>The effect of the resistance of the wire in the line on the current when the fourth transistor is turned on.
16. A control method of the memory cell structure according to any one of claims 1to 15, comprising:
When a data writing operation is carried out on the first magnetic memory, a first transistor and a switching transistor at a writing source line are turned on, a second transistor, a third transistor, a fourth transistor and a switching transistor at a reading source line are turned off, voltage excitation is provided through a bit line, injection current flows out of the switching transistor at the writing source line through a first heavy metal layer which passes through the first magnetic memory in parallel, and data writing of the first magnetic memory is completed;
When the data writing operation is carried out on the second magnetic memory, the third transistor and the switching transistor at the writing source line are turned on, the first transistor is turned off, the second transistor, the fourth transistor and the switching transistor at the reading source line are provided with voltage excitation through the bit line, and the injection current flows out of the switching transistor at the writing source line through the second heavy metal layer which passes through the second magnetic memory in parallel, so that the data writing of the second magnetic memory is completed.
17. The control method according to claim 16, characterized by further comprising:
When data reading operation is carried out, the second transistor is started, the fourth transistor and the switching transistor at the reading source line are closed, the first transistor is closed, the third transistor and the switching transistor at the writing source line are provided with voltage excitation through the bit line, current respectively passes through the first magnetic tunnel junction of the first magnetic memory and the second magnetic tunnel junction of the second magnetic memory, and current is converged at the common electrode layer and is output through the switching transistor at the reading source line.
18. An array circuit comprising a plurality of memory cell structures according to any one of claims 1 to 15 arranged in an array.
19. An array device comprising the array circuit of claim 18, and peripheral circuitry coupled to the array circuit.
20. An electronic device comprising an array arrangement as claimed in claim 19.
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