CN114694704A - Magnetic memory and read-write method thereof - Google Patents

Magnetic memory and read-write method thereof Download PDF

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Publication number
CN114694704A
CN114694704A CN202011596090.7A CN202011596090A CN114694704A CN 114694704 A CN114694704 A CN 114694704A CN 202011596090 A CN202011596090 A CN 202011596090A CN 114694704 A CN114694704 A CN 114694704A
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China
Prior art keywords
conductive line
plane
magnetic
layer
magnetic memory
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吴保磊
王晓光
吴玉雷
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202011596090.7A priority Critical patent/CN114694704A/en
Priority to PCT/CN2021/095841 priority patent/WO2022142097A1/en
Priority to US17/480,357 priority patent/US20220208853A1/en
Publication of CN114694704A publication Critical patent/CN114694704A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Abstract

The invention provides a magnetic memory and a reading and writing method thereof, wherein the magnetic memory comprises at least one unit layer, and the unit layer comprises: the plurality of parallel first conducting wires are positioned in a first plane; the plurality of parallel second conducting wires are positioned in a second plane, the first plane is parallel to the second plane, and the projection of the second conducting wires on the first plane is crossed with the first conducting wires; a number of storage elements disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bidirectional gating devices disposed in series in a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first conductive lines, the bidirectional gating devices being connected to the second conductive lines, the bidirectional gating devices being configured to conduct when a threshold voltage and/or current is applied. The magnetic memory changes the traditional magnetic memory design and greatly improves the storage density of the magnetic field memory.

Description

Magnetic memory and read-write method thereof
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a magnetic memory and a read/write method thereof.
Background
Mram (magnetic Random Access memory) is a non-volatile magnetic memory that provides comparable performance to volatile Static Random Access Memory (SRAM) and comparable density and lower power consumption to volatile Dynamic Random Access Memory (DRAM). MRAM provides faster access times and suffers minimal degradation over time compared to non-volatile memory (NVM) flash memory, which can only be rewritten a limited number of times.
The core of an MRAM element is a Magnetic Tunnel Junction (MTJ), which may include a fixed Magnetic layer whose magnetization polarity is not changeable and a free Magnetic layer whose magnetization polarity is changeable. Due to the tunneling magnetoresistance effect, the resistance value between the fixed magnetic layer and the free magnetic layer changes with the switching of the magnetization polarity in the free magnetic layer, thereby realizing the writing of the magnetic memory.
However, memory density is one of the key limiting factors in the push of MRAM to the main memory/storage market, and therefore, how to increase the density of magnetic memories is a problem that needs to be solved.
Disclosure of Invention
The invention provides a high-density magnetic memory and a reading and writing method thereof.
In order to solve the above problems, the present invention provides a magnetic memory including at least one cell layer, the cell layer including: the plurality of parallel first conducting wires are positioned in a first plane; the plurality of parallel second conducting wires are positioned in a second plane, the first plane is parallel to the second plane, and the projection of the second conducting wires on the first plane is crossed with the first conducting wires; a number of storage elements disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bidirectional gating devices disposed in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first conductive line, the bidirectional gating devices being connected to the second conductive line, the bidirectional gating devices being configured to conduct when a threshold voltage and/or current is applied.
Further, the magnetic tunnel junction includes: a free layer connected to the first conductive line; a non-magnetic insulating layer disposed on an upper surface of the free layer; the fixed layer is arranged on the upper surface of the nonmagnetic insulating layer, the direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the fixed layer is fixed; one end of the bidirectional gating device is connected with the fixed layer, and the other end of the bidirectional gating device is connected with the second wire.
Further, the first conductive line includes a first end and a second end, the magnetic memory further includes a plurality of write bit lines and a plurality of first select transistors configured to electrically connect the first end of the first conductive line and the write bit lines in response to a first control signal.
Further, the magnetic memory also includes a source line electrically connected to the second end of the first conductive line.
Further, the magnetic memory further includes a number of bit lines and a number of second select transistors configured to electrically connect the second conductive lines and the bit lines in response to a second control signal.
Further, the projection of the second wire on the first plane perpendicularly crosses the first wire.
Further, the magnetic memory includes a plurality of the unit layers, the plurality of the unit layers are sequentially arranged in a direction perpendicular to the first plane, and adjacent unit layers share the same wire, wherein the wire is used as the first wire in an upper unit layer and used as the second wire in a lower unit layer.
Further, the magnetic memory includes a plurality of the unit layers, the plurality of unit layers are sequentially arranged in a direction perpendicular to the first plane, and adjacent unit layers share the same wire, wherein the wire is used as the first wire or the second wire in both the upper unit layer and the lower unit layer.
Further, different storage elements are used as control switches through the bidirectional gating device to realize respective control.
Further, the material of the bidirectional gating device is doped hafnium oxide.
The invention also provides a read-write method of a magnetic memory, wherein the magnetic memory comprises at least one unit layer, and the unit layer comprises: the plurality of parallel first conducting wires are positioned in a first plane; the plurality of parallel second conducting wires are positioned in a second plane, the first plane is parallel to the second plane, and the projection of the second conducting wires on the first plane is crossed with the first conducting wires; a number of storage elements disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bidirectional gating devices disposed in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first conductive line, the bidirectional gating devices being connected to the second conductive line, the bidirectional gating devices being configured to conduct when a threshold voltage and/or current is applied;
the reading and writing method comprises the following steps: providing a first current to the magnetic memory, the first current flowing through the first conductive line and not through the storage element, placing the storage element in a first storage state; a second current is provided to the magnetic memory, the second current flowing through the selected storage element causing the selected storage element to change from the first storage state to a second storage state.
Further, the magnetic tunnel junction includes: a free layer connected to the first conductive line; a non-magnetic insulating layer disposed on an upper surface of the free layer; the fixed layer is arranged on the upper surface of the nonmagnetic insulating layer, the direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the fixed layer is fixed; one end of the bidirectional gating device is connected with the fixed layer, and the other end of the bidirectional gating device is connected with the second wire; the reading and writing method comprises the following steps: the first current and the second current make the magnetic moment direction of the free layer change in opposite directions.
Further, the first current changes the direction of the magnetic moment of the free layer in a direction opposite to the direction of the magnetic moment of the fixed layer, and the second current changes the direction of the magnetic moment of the free layer in a direction same as the direction of the magnetic moment of the fixed layer.
Further, the first current changes the direction of the magnetic moment of the free layer in the same direction as the direction of the magnetic moment of the fixed layer, and the second current changes the direction of the magnetic moment of the free layer in the opposite direction to the direction of the magnetic moment of the fixed layer.
Further, the first conductive line includes a first end and a second end, the magnetic memory further includes a number of write bit lines and a number of first select transistors configured to electrically connect the first end of the first conductive line and the write bit lines in response to a first control signal; the reading and writing method comprises the following steps: the first selection transistor is controlled by the first control signal, so that the first selection transistor electrically connects the first end of the first wire and the write bit line in response to the first control signal, so that the first current flows through the first wire.
Further, the magnetic memory further includes a source line electrically connectable to the second end of the first conductive line, the method of reading and writing including: the first current flows from the write bit line to the source line through the first conductive line, or the first current flows from the source line to the write bit line through the first conductive line.
Further, the magnetic memory further includes a number of bit lines and a number of second select transistors configured to electrically connect the second conductive lines and the bit lines in response to a second control signal; the reading and writing method comprises the following steps: controlling the second select transistor by a second control signal, such that the second select transistor electrically connects the second conductive line and the bit line in response to the second control signal, causing the second current to flow through the selected memory element.
Further, the read-write method further comprises: in a read operation, a third current is provided to the magnetic memory, the third current flowing from the second conductive line through the memory element to the first conductive line.
Further, different storage elements are used as control switches through the bidirectional gating device to realize respective control; in the step of providing a second current to the magnetic memory, the selected storage element is configured as the storage element when a threshold voltage and/or current is applied to the ovonic gating device.
The invention has the advantages that the design of the traditional magnetic memory is changed, and the storage density of the magnetic field memory is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a magnetic memory according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a magnetic memory according to a second embodiment of the present invention;
FIG. 3 is a front view of the structure shown in FIG. 2;
FIG. 4 is a front elevational view of a magnetic memory in accordance with a third embodiment of the present invention;
FIG. 5 is a front view of a magnetic memory according to a fourth embodiment of the present invention;
FIG. 6 is a front elevational view of a fifth embodiment of the magnetic memory of the present invention;
FIG. 7 is a timing diagram illustrating a read/write method of a magnetic memory according to a sixth embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of the magnetic memory and the read/write method thereof according to the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a magnetic memory according to a first embodiment of the present invention, and referring to FIG. 1, the magnetic memory according to the present invention includes at least one cell layer 100. In this embodiment, the magnetic memory includes a cell layer 100.
The cell layer 100 includes a plurality of parallel first conductive lines 110, a plurality of parallel second conductive lines 120, and a plurality of memory elements 130. The number of the first conductive lines 110, the second conductive lines 120 and the storage elements 130 can be set according to the storage requirement of the magnetic memory. Only two parallel first conductive lines 110, three parallel second conductive lines 120 and six memory elements 130 are schematically illustrated in fig. 1, which does not limit the present invention.
The first conductive line 110 is located in a first plane (not shown). In this embodiment, the first conductive lines 110 extend along the X direction and are arranged in parallel along the Y direction, so that the first plane is an XY plane.
The second conductive line 120 is located in a second plane (not shown), and the first plane is parallel to the second plane. In this embodiment, the second wires 120 extend along the Y direction and are arranged in parallel along the X direction, so that the second plane is also an XY plane, and the first plane and the second plane are parallel planes.
Wherein the projection of the second conducting wire 120 on the first plane intersects the first conducting wire 110, or the projection of the first conducting wire 110 on the second plane intersects the second conducting wire 120. Specifically, the projection of the second conductive line 120 on the first plane intersects the first conductive line 110 in a direction perpendicular to the first plane, or the projection of the first conductive line 110 on the second plane intersects the second conductive line 120 in a direction perpendicular to the second plane. Since the first plane is parallel to the second plane, the first conductive line 110 and the second conductive line 120 do not directly intersect, but the projections of the two intersect on a certain plane.
Further, in the present embodiment, the projection of the second conductive line 120 on the first plane is perpendicular to the first conductive line 110, while in other embodiments of the present invention, the projection of the second conductive line 120 on the first plane is not perpendicular to the first conductive line 110, but intersects the first conductive line 110 at an acute angle or an obtuse angle.
Further, in order to improve the conductivity of the first conductive line 110 and the second conductive line 120, the following materials may be used for the first conductive line 110 and the second conductive line 120: heavy metals (e.g., Pt, Ta, etc.), semi-metals (e.g., MoTe)2) Or chalcogenides (e.g. Bi)xTe1-x)。
A number of the memory elements 130 are disposed between the first plane and the second plane. I.e. several of said memory elements 130 are arranged in a sandwich formed by said first plane and said second plane. Each of the memory elements 130 includes a magnetic tunnel junction 131 and a bidirectional pass device 132 arranged in series along a direction perpendicular to the first plane. In the present embodiment, the memory element 130 is disposed at the intersection of the first conductive line 110 and the second conductive line 120, the magnetic tunnel junction 131 is connected to the first conductive line 110, and the bidirectional gating device 132 is connected to the second conductive line 120. In other embodiments of the present invention, the magnetic tunnel junction 131 can also be interchanged with the location of the bidirectional gating device 132, i.e., the magnetic tunnel junction 131 is connected to the second conductive line 120 and the bidirectional gating device 132 is connected to the first conductive line 110.
Wherein the bidirectional pass device 132 is configured to conduct when a threshold voltage and/or current is applied. The conduction refers to the bidirectional gating device 132 transitioning from a high resistance state to a low resistance state. Specifically, when the voltage or current applied to the bidirectional gate device 132 is a threshold voltage or current, or exceeds a threshold voltage or current, the bidirectional gate device 132 is changed from a high resistance state to a low resistance state, thereby electrically connecting the magnetic tunnel junction 131 and the second conductive line 120. Wherein the threshold voltage or current depends on the material properties of the magnetic tunnel junction 131. For example, in this embodiment, the material of the bidirectional gating device 132 is doped hafnium oxide, the turn-on threshold voltage of the material is 0.25V, the bidirectional gating device 132 is turned on when the voltage applied to the bidirectional gating device 132 is 0.25V or exceeds 0.25V, and the bidirectional gating device 132 is not turned on when the voltage applied to the bidirectional gating device 132 is less than 0.25V. The doped hafnium oxide has high on/off ratio and low on-resistance, and is an ideal material for the bidirectional gating device. Of course, other materials capable of performing the threshold conduction function may be used as the material of the bidirectional gating device 132, and the present invention is not limited thereto.
Since the ovonic gating device 132 is capable of turning on when a threshold voltage and/or current is applied, different memory elements 130 may act as control switches through the ovonic gating device to enable individual control of the memory elements 130. Specifically, if an operation is required to be performed on one or some of the storage elements 130, the bidirectional gating device 132 corresponding to the one or some of the storage elements 130 may be controlled to be conductive, and the bidirectional gating device 132 corresponding to other non-selected storage elements 130 may be controlled to be non-conductive, so as to implement selective operation on the storage elements 130.
Further, the magnetic tunnel junction 131 includes a free layer 131A connected to the first conductive line 110, a non-magnetic insulating layer 131B disposed on an upper surface of the free layer 131A, and a fixed layer 131C disposed on an upper surface of the non-magnetic insulating layer 131B. The magnetic moment direction of the free layer 131A is changeable, and the magnetic moment direction of the fixed layer 131c is fixed. Due to the tunneling magnetoresistance effect, the resistance value between the fixed layer 31C and the free layer 131A changes as the direction of magnetic moment in the free layer 131A is switched, thereby realizing writing of the magnetic memory.
The bidirectional gating device 132 has one end connected to the fixed layer 131C and the other end connected to the second conductive line 120. The first terminal and the second terminal of the bidirectional gating device 132 are only provided for convenience of description, and the first terminal and the second terminal of the bidirectional gating device 132 are not different, that is, any terminal of the bidirectional gating device 132 may be connected to the fixed layer 131C.
The magnetic memory changes the traditional magnetic memory design and greatly improves the storage density of the magnetic field memory.
Further, the first conductive line 110 includes a first end and a second end. The magnetic memory also includes a number of write bit lines WBL and a number of first select transistors WWL. The first selection transistor WWL is configured to electrically connect a first end of the first conductive line 110 and the write bit line WBL in response to a first control signal.
Specifically, only two write bit lines WBL and two first selection transistors WWL, which are the write bit line WBL [00] and the write bit line WBL [01], the first selection transistor WWL [00] and the first selection transistor WWL [01], are schematically illustrated in fig. 1. Here, since the write bit line WBL is not a point of improvement of the present invention, it is illustrated with only a hanging line segment in the drawing. The first selection transistor WWL [00] is configured to electrically connect a first end of the first conductive line 110 and the write bit line WBL [00] in response to a first control signal, and the first selection transistor WWL [01] is configured to electrically connect a first end of the other first conductive line 110 and the write bit line WBL [01] in response to a first control signal.
Further, the magnetic memory further includes a source line WSL electrically connected to the second end of the first conductive line 110, for example, through a transistor switch. Specifically, only two source lines WSL, source line WSL [00] and source line WSL [01], are schematically shown in FIG. 1. The source line WSL [00] is electrically connected to a second end of the first conductive line 110, and the source line WSL [01] is electrically connected to a second end of another of the first conductive lines 110.
Further, the magnetic memory also includes a number of bit lines BBL and a number of second select transistors BWL, the second select transistors BWL configured to electrically connect the second conductive line 120 and the bit lines BBL in response to a second control signal. Specifically, only three bit lines BBL and three second select transistors BWL are schematically illustrated in fig. 1, which are bit lines BBL [00], bit lines BBL [01], bit lines BBL [02], second select transistors BWL [00], second select transistors BWL [01], and second select transistors BWL [02 ]. The second select transistor BWL [00] is configured to electrically connect the second conductive line 120 and the bit line BBL [00] in response to a second control signal, the second select transistor BWL [01] is configured to electrically connect the second conductive line 120 and the bit line BBL [01] in response to a second control signal, and the second select transistor BWL [02] is configured to electrically connect the second conductive line 120 and the bit line BBL [02] in response to a second control signal.
In order to further increase the storage density of the magnetic memory, the present invention provides a second embodiment. The second embodiment is different from the first embodiment in that the second embodiment includes a plurality of unit layers, which are stacked. Specifically, please refer to fig. 2 and 3, wherein fig. 2 is a schematic structural diagram of a magnetic memory according to a second embodiment of the present invention, and fig. 3 is a front view of the structure shown in fig. 2. In a second embodiment, the magnetic memory includes a plurality of unit layers sequentially arranged in a direction perpendicular to the first plane. In this embodiment, the magnetic memory includes two unit layers, i.e., an upper unit layer 100A and a lower unit layer 100B, and the upper unit layer 100A and the lower unit layer 100B are sequentially disposed along a direction perpendicular to the first plane.
Adjacent unit layers share the same conductive line, and the conductive line is used as the first conductive line in the upper unit layer 100A and used as the second conductive line in the lower unit layer 100B. Specifically, in the present embodiment, the upper unit layer 100A and the lower unit layer 100B are adjacent unit layers, and the common conductive line is the conductive line 200. In the upper cell layer 100A, the conductive line 200 is connected to the magnetic tunnel junction 131 of the memory element 130, and thus, in the upper cell layer 100A, the conductive line 200 serves as a first conductive line, and in the lower cell layer 100B, the conductive line 200 is connected to the bidirectional gate device 132, and thus, in the lower cell layer 100B, the conductive line 200 serves as a second conductive line.
While the magnetic memory in the second embodiment described above includes only two unit layers, in other embodiments of the present invention, in order to further increase the storage density of the magnetic memory, the magnetic memory may include a plurality of unit layers, which are sequentially arranged in a direction perpendicular to the first plane. Referring to fig. 4, which is a front view of a magnetic memory according to a third embodiment of the present invention, in the third embodiment, the magnetic memory may include a plurality of unit layers, and the unit layers are sequentially disposed along a direction perpendicular to the first plane. Fig. 4 schematically illustrates 5 unit layers, namely, a unit layer 100A, a unit layer 100B, a unit layer 100C, a unit layer 100D, and a unit layer 100E, which are sequentially arranged in a direction perpendicular to the first plane.
And the adjacent unit layers share the same wire, and the wire is used as the first wire in the upper unit layer and used as the second wire in the lower unit layer. For example, in the third embodiment, the cell layer 100A is adjacent to the cell layer 100B, and both share the conductive line 200, then in the cell layer 100A, the conductive line 200 is used as the first conductive line, and in the cell layer 100B, the conductive line 200 is used as the second conductive line; the unit layer 100B is adjacent to the unit layer 100C, and both share the conductive line 300, so that in the unit layer 100B, the conductive line 300 is used as a first conductive line, and in the unit layer 100C, the conductive line 300 is used as a second conductive line; the unit layer 100C is adjacent to the unit layer 100D, and both of them share the wire 400, so that in the unit layer 100C, the wire 400 is used as a first wire, and in the unit layer 100D, the wire 400 is used as a second wire; the cell layer 100D is adjacent to the cell layer 100E, and both share the conductive line 500, so that in the cell layer 100D, the conductive line 500 is used as a first conductive line, and in the cell layer 100E, the conductive line 500 is used as a second conductive line.
In the second and third embodiments, the bidirectional gating devices 132 of the memory cells 130 of all the cell layers are located above the magnetic tunnel junction 131, so that the conductive line shared by the adjacent cell layers is used as the first conductive line in the upper cell layer and used as the second conductive line in the lower cell layer. In other embodiments of the present invention, the bidirectional gating device 132 of the memory cell 130 may also be located below the magnetic tunnel junction 131, and the principle is the same as that of the second and third embodiments, and is not repeated.
In the second embodiment or the third embodiment of the present invention, the connection relationship of the conductive line shared by the adjacent unit layers and the memory element 130 is different in the two layers, that is, the function of the conductive line shared by the adjacent unit layers is different in the two layers. Yet another embodiment of the present invention also provides a magnetic memory that is different from the second embodiment in that the connection relationship of the conductive lines shared by the adjacent cell layers with the memory element 130 is the same in two layers, i.e., the functions of the conductive lines shared by the adjacent cell layers are the same in two layers. That is, the wires shared by the adjacent unit layers are used as the first wires or the second wires in both the upper unit layer and the lower unit layer.
Specifically, please refer to fig. 5, which is a front view of a magnetic memory according to a fourth embodiment of the present invention. In the fourth embodiment, the magnetic memory includes two unit layers, i.e., an upper unit layer 100A and a lower unit layer 100B, and the upper unit layer 100A and the lower unit layer 100B are sequentially disposed along a direction perpendicular to the first plane.
The upper unit layer 100A and the lower unit layer 100B share the same conductive line, and the conductive line is used as the first conductive line or the second conductive line in both the upper unit layer 100A and the lower unit layer 100B. Specifically, in the present embodiment, the conducting line shared by the upper unit layer 100A and the lower unit layer 100B is the conducting line 200. In the upper unit layer 100A, the conductive line 200 is connected to the magnetic tunnel junction 131 of the memory element 130, and therefore, in the upper unit layer 100A, the conductive line 200 is used as a first conductive line, and in the lower unit layer 100B, the conductive line 200 is connected to the magnetic tunnel junction 131 of the memory element 130, and therefore, in the lower unit layer 100B, the conductive line 200 is also used as a first conductive line. In other embodiments of the present invention, the memory elements of each layer may also be turned around so that the conductive line 200 is respectively coupled to the magnetic tunnel junctions 131 of the memory elements of the upper unit layer 100A and the lower unit layer 100B, and the conductive line 200 is used as the second conductive line.
While the magnetic memory in the fourth embodiment described above includes only two unit layers, in other embodiments of the present invention, in order to further increase the storage density of the magnetic memory, the magnetic memory may include a plurality of unit layers, which are sequentially arranged in a direction perpendicular to the first plane. Referring to fig. 6, which is a front view of a magnetic memory according to a fifth embodiment of the present invention, in the fifth embodiment, the magnetic memory may include a plurality of unit layers, and the unit layers are sequentially disposed along a direction perpendicular to the first plane. Fig. 6 schematically illustrates 5 unit layers, which are a unit layer 100A, a unit layer 100B, a unit layer 100C, a unit layer 100D, and a unit layer 100E, respectively, and the five unit layers are sequentially disposed in a direction perpendicular to the first plane.
The adjacent unit layers share the same wire, and the wire is used as the first wire or the second wire in the upper unit layer and the lower unit layer. For example, in the fifth embodiment, the cell layer 100A is adjacent to the cell layer 100B, and both share the conductive line 200, then in the cell layer 100A, the conductive line 200 is used as the first conductive line, and in the cell layer 100B, the conductive line 200 is also used as the first conductive line; the unit layer 100B is adjacent to the unit layer 100C, and both share the conductive line 300, so that in the unit layer 100B, the conductive line 300 is used as a second conductive line, and in the unit layer 100C, the conductive line 300 is also used as a second conductive line; the unit layer 100C is adjacent to the unit layer 100D, and both share the conductive line 400, so that the conductive line 400 is used as a first conductive line in the unit layer 100C, and the conductive line 400 is also used as a first conductive line in the unit layer 100D; the cell layer 100D is adjacent to the cell layer 100E, and both share the conductive line 500, so that the conductive line 500 is used as a second conductive line in the cell layer 100D, and the conductive line 500 is also used as a second conductive line in the cell layer 100E.
It is understood that in other embodiments of the present invention, the direction of the memory cell 130 in each layer may also be turned, and the connection relationship between the magnetic tunnel junction and the bidirectional gating device and the common conductive line is changed.
Furthermore, the drawings of the present invention only schematically illustrate the mutual position relationship among the first conductive lines, the memory cells and the second conductive lines, and in the actual semiconductor process, the blank spaces except the first conductive lines, the memory cells and the second conductive lines are also filled with insulating materials or other structural materials, which are not described herein again.
The invention also provides a reading and writing method of the magnetic memory. Referring to fig. 1 and 7, fig. 7 is a timing diagram illustrating a read/write method of a magnetic memory according to a sixth embodiment of the present invention.
The reading and writing method comprises the following steps;
erase operation (Eraser): a first current Ieraser is provided to the magnetic memory, which flows through the first conductive line 110 but not through the storage element 130, placing the storage element 130 in a first storage state.
Wherein the first current Ieraser flows only through the first conductive line 110, and the first current Ieraser acts on the magnetic tunnel junction 131 through the first conductive line 110, so that the magnetic moment direction of the free layer 131A of the magnetic tunnel junction 131 is changed to the same direction, for example, the same direction or opposite direction to the magnetic moment direction of the fixed layer 131C. After the first current Ieraser is applied to the first conducting wire 110, all the memory cells connected to the first conducting wire 110 are in the same memory state, i.e. the first memory state. The first storage state may be storing a "0" or storing a "1". For example, in the present embodiment, under the action of the first current Ieraser, the magnetic moment direction of the free layer 131A is opposite to the magnetic moment direction of the fixed layer 131C, i.e. the first storage state is storage "1", which can make the storage "1" only need to be modified to storage "0" in performing the write operation, and greatly reduce the loss of the magnetic tunnel junction. It should be noted that the memory state "1" can also be expressed as the magnetic moment direction of the free layer 131A is the same as the magnetic moment direction of the fixed layer 131C, and the design can be designed by one skilled in the art according to the requirement.
In this embodiment, the first selection transistor WWL is controlled by the first control signal, such that the first selection transistor WWL electrically connects the first end of the first conductive line 110 and the write bit line WBL in response to the first control signal, the write bit line WBL is at a high level, the source line WSL is at a low level, and the first current Ieraser passes through the first conductive line 110 from the write bit line WBL to the source line WSL. Alternatively, in another embodiment of the present invention, the write bit line WBL is at a low level, the source line WSL is at a high level, and the first current Ieraser is from the source line WSL to the write bit line WBL through the first conductive line 110.
Write operation (Write): a second current Iwrite is provided to the magnetic memory, the second current Iwrite flowing through the selected storage element causing the selected storage element to change from the first storage state to a second storage state.
Wherein the different storage elements are controlled separately by the bidirectional gating device 132 as control switches. In this write operation step, the selected storage element is configured as the storage element when a threshold voltage and/or current is applied to the bidirectional pass device 132. That is, in this step, if it is necessary to operate one of the memory elements 130, the bidirectional gate device 132 is turned on, and the memory element 130 is electrically connected to the first conductive line 110 and the second conductive line 120.
In the write operation, the second current Iwrite flows through the memory element 130, and the second current Iwrite changes the magnetic moment direction of the free layer 131A, such that the magnetic moment direction of the free layer 131A is in the same direction or opposite direction as the magnetic moment direction of the fixed layer 131C.
Further, the first current Ieraser and the second current Iwrite cause the magnetic moment direction of the free layer to change in opposite directions.
For example, in the present embodiment, in the erase operation, the first current Ieraser changes the magnetic moment direction of the free layer 131A in a direction opposite to the magnetic moment direction of the fixed layer 131C, and the second current Iwrite changes the magnetic moment direction of the free layer 131A in the same direction as the magnetic moment direction of the fixed layer 131C, that is, the first memory state is a memory "1" and the second memory state is a memory "0".
For another example, in another embodiment, in the erase operation, the first current Ieraser changes the magnetic moment direction of the free layer 131A to the same direction as the magnetic moment direction of the fixed layer 131C, and the second current Iwrite changes the magnetic moment direction of the free layer 131A to the opposite direction of the magnetic moment direction of the fixed layer 131C, that is, the first memory state is a memory "0" and the second memory state is a memory "1".
It should be noted that storing "0" can also be expressed as the direction of the magnetic moment of the free layer 131A is opposite to the direction of the magnetic moment of the fixed layer 131C, and storing "1" is the same, and it should be understood by those skilled in the art that this is only a definition difference and can be defined by themselves as required.
In this embodiment, the second selection transistor BWL is controlled by a second control signal, such that the second selection transistor BWL electrically connects the second conductive line 120 and the bit line BBL in response to the second control signal, and the second current Iwrite flows through the selected memory element 130, thereby achieving the purpose of changing the memory state of the memory element 130 from the first memory state to the second memory state.
For example, the second select transistor BWL is controlled to be turned on by the second control signal, the bit line BBL is at a low level, the source line WSL is at a high level, and a second current Iwrite flows from the source line WSL to the bit line BBL from the first conductive line 110, through the memory element 130, through the second conductive line 120. Alternatively, the bit line BBL is at a high level, the source line WSL is at a low level, and a second current Iwrite flows from the bit line BBL from the second conductive line 120 through the memory element 130, the first conductive line 110 to the source line WSL.
Further, the invention also provides a reading operation of the magnetic memory.
A Read operation (Read) provides a third current to the magnetic memory, the third current Iread flowing from the second conductive line 120 through the memory element 130 to the first conductive line 110.
In which different memory elements are controlled separately by the bidirectional gating device 132 as control switches, as in the write operation. In the read operation step, if it is necessary to read one of the memory elements 130, the bidirectional gating device 132 of the memory element is turned on, and the bidirectional gating devices 132 of the other memory elements 130 are turned off, so that the memory element 130 is operated independently, and the read operation is prevented from being affected by the other memory elements 130.
When the read operation is performed, the third current Iread passes through the memory element 130, a potential difference is generated across the memory element 130, and the resistance of the memory element 130 can be determined according to the magnitude of the potential difference, so that the orientation relationship of the magnetic moment directions of the free layer 131A and the fixed layer 131C of the magnetic tunnel junction can be obtained, and the storage state of the memory element 130 can be read. Alternatively, the storage state of the storage element 130 can be determined according to the magnitude of the third current Iread, and a person skilled in the art can design the storage state according to needs.
In this embodiment, the second selection transistor BWL is controlled to be turned on by a third control signal, so that the second selection transistor BWL electrically connects the second conductive line 120 and the bit line BBL in response to the third control signal, and the third current I is enabledreadFlows through the selected memory element 130 to obtain the memory state of the memory element 130.
It should be noted that, in this embodiment, the high level and the low level are both relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and the specific voltage value of the high level and the specific voltage value of the low level are not limited. It is also not limited that the high levels applied to different signal lines in this embodiment are equal, for example, the high level on the bit line and the high level on the word line may be different voltages, or the high levels of specific signal lines in different stages may be equal, for example, the high levels applied to the bit line BBL in the write operation and the high levels applied to the bit line BBL in the read operation may be different voltage values. It will be understood by those skilled in the art that the values of the respective high and low levels may be set on their own, depending on process nodes, speed requirements, reliability requirements, etc.
The above describes the read/write method of only one unit layer, and for a magnetic memory with multiple unit layers, the read/write method is the same as that of a single layer, and is not described again.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (19)

1. A magnetic memory comprising at least one cell layer, the cell layer comprising:
the plurality of parallel first conducting wires are positioned in a first plane;
the plurality of parallel second conducting wires are positioned in a second plane, the first plane is parallel to the second plane, and the projection of the second conducting wires on the first plane is crossed with the first conducting wires;
a number of storage elements disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bidirectional gating devices disposed in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first conductive line, the bidirectional gating devices being connected to the second conductive line, the bidirectional gating devices being configured to conduct when a threshold voltage and/or current is applied.
2. The magnetic memory of claim 1, wherein the magnetic tunnel junction comprises:
a free layer connected to the first conductive line;
a non-magnetic insulating layer disposed on an upper surface of the free layer;
the fixed layer is arranged on the upper surface of the nonmagnetic insulating layer, the direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the fixed layer is fixed;
one end of the bidirectional gating device is connected with the fixed layer, and the other end of the bidirectional gating device is connected with the second wire.
3. The magnetic memory of claim 1, wherein the first conductive line includes a first end and a second end, the magnetic memory further comprising a number of write bit lines and a number of first select transistors configured to electrically connect the first end of the first conductive line and the write bit lines in response to a first control signal.
4. The magnetic memory of claim 3, further comprising a source line electrically connected to the second end of the first conductive line.
5. The magnetic memory of claim 1, further comprising a number of bit lines and a number of second select transistors configured to electrically connect the second conductive lines with the bit lines in response to a second control signal.
6. The magnetic memory of claim 1, wherein the projection of the second conductive line onto the first plane intersects the first conductive line perpendicularly.
7. The magnetic memory according to claim 1, wherein the magnetic memory comprises a plurality of the unit layers, the plurality of the unit layers are sequentially arranged in a direction perpendicular to the first plane, and adjacent unit layers share a same conductive line, wherein the conductive line is used as the first conductive line in an upper unit layer and used as the second conductive line in a lower unit layer.
8. The magnetic memory according to claim 1, wherein the magnetic memory comprises a plurality of the unit layers, the plurality of the unit layers are sequentially arranged in a direction perpendicular to the first plane, adjacent unit layers share a same conductive line, and the conductive line is used as the first conductive line or the second conductive line in each of an upper unit layer and a lower unit layer.
9. The magnetic memory of claim 1, wherein different storage elements are separately controlled by the bidirectional gating device as control switches.
10. The magnetic memory of claim 1 wherein the material of the bidirectional pass device is doped hafnium oxide.
11. A method for reading from and writing to a magnetic memory, the magnetic memory comprising at least one cell layer, the cell layer comprising:
the plurality of parallel first conducting wires are positioned in a first plane;
the plurality of parallel second conducting wires are positioned in a second plane, the first plane is parallel to the second plane, and the projection of the second conducting wires on the first plane is crossed with the first conducting wires;
a number of storage elements disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bidirectional gating devices disposed in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first conductive line, the bidirectional gating devices being connected to the second conductive line, the bidirectional gating devices being configured to conduct when a threshold voltage and/or current is applied;
the reading and writing method comprises the following steps:
providing a first current to the magnetic memory, the first current flowing through the first conductive line and not through the storage element, placing the storage element in a first storage state;
a second current is provided to the magnetic memory, the second current flowing through the selected storage element causing the selected storage element to change from the first storage state to a second storage state.
12. The read-write method according to claim 11, wherein the magnetic tunnel junction includes:
a free layer connected to the first conductive line;
a non-magnetic insulating layer disposed on an upper surface of the free layer;
the fixed layer is arranged on the upper surface of the nonmagnetic insulating layer, the direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the fixed layer is fixed;
one end of the bidirectional gating device is connected with the fixed layer, and the other end of the bidirectional gating device is connected with the second wire;
the reading and writing method comprises the following steps:
the first current and the second current make the magnetic moment direction of the free layer change in opposite directions.
13. The method according to claim 12, wherein the first current changes a direction of a magnetic moment of the free layer in a direction opposite to a direction of a magnetic moment of the pinned layer, and the second current changes a direction of a magnetic moment of the free layer in a direction same as the direction of a magnetic moment of the pinned layer.
14. The method according to claim 12, wherein the first current changes a direction of a magnetic moment of the free layer in a direction in the same direction as a direction of a magnetic moment of the pinned layer, and the second current changes a direction of a magnetic moment of the free layer in a direction opposite to the direction of a magnetic moment of the pinned layer.
15. The method of claim 11, wherein the first conductive line includes a first terminal and a second terminal, the magnetic memory further includes a plurality of write bit lines and a plurality of first select transistors configured to electrically connect the first terminal of the first conductive line and the write bit lines in response to a first control signal;
the reading and writing method comprises the following steps:
the first selection transistor is controlled by the first control signal, so that the first selection transistor electrically connects the first end of the first wire and the write bit line in response to the first control signal, so that the first current flows through the first wire.
16. The method of claim 15, wherein the magnetic memory further comprises a source line electrically connectable to the second end of the first conductive line, the method comprising: the first current flows from the write bit line to the source line through the first conductive line, or the first current flows from the source line to the write bit line through the first conductive line.
17. The method according to claim 11, wherein the magnetic memory further comprises a plurality of bit lines and a plurality of second selection transistors configured to electrically connect the second conductive lines and the bit lines in response to a second control signal;
the reading and writing method comprises the following steps:
controlling the second select transistor by a second control signal, such that the second select transistor electrically connects the second conductive line and the bit line in response to the second control signal, causing the second current to flow through the selected memory element.
18. A method of reading from and writing to claim 11, further comprising: in a read operation, a third current is provided to the magnetic memory, the third current flowing from the second conductive line through the memory element to the first conductive line.
19. A method according to claim 11, wherein different memory elements are controlled separately by said bidirectional gating device as control switches; in the step of providing a second current to the magnetic memory, the selected storage element is configured as the storage element when a threshold voltage and/or current is applied to the ovonic gating device.
CN202011596090.7A 2020-12-29 2020-12-29 Magnetic memory and read-write method thereof Pending CN114694704A (en)

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