CN118057620A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN118057620A
CN118057620A CN202211459339.9A CN202211459339A CN118057620A CN 118057620 A CN118057620 A CN 118057620A CN 202211459339 A CN202211459339 A CN 202211459339A CN 118057620 A CN118057620 A CN 118057620A
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epitaxial
forming
layer
initial
semiconductor structure
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于海龙
韩静利
王晓娟
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202211459339.9A priority Critical patent/CN118057620A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, wherein the method for forming comprises: providing a substrate; forming an initial epitaxial structure in the substrate, wherein the material of the initial epitaxial structure comprises silicon germanium; oxidizing the surface of the initial epitaxial structure, and forming an initial oxidation layer on the surface of the initial epitaxial structure, wherein the initial epitaxial structure becomes an epitaxial layer, the epitaxial layer comprises a first epitaxial region and a second epitaxial region positioned on the first epitaxial region, and the germanium concentration of the second epitaxial region is greater than that of the first epitaxial region; removing the initial oxide layer; and forming a conductive contact structure on the epitaxial layer. The semiconductor structure and the forming method thereof reduce the contact resistance of the device, improve the stability of the device and improve the electrical property.

Description

Semiconductor structure and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.
Background
As semiconductor technology advances, the size of semiconductor devices continues to decrease. The source region and the drain region of the field effect transistor device are connected with an external circuit through a metal contact structure. In recent years, as transistor devices become smaller in size, the contact resistance between the source and drain regions of the transistor and the overlying metal contact structure inevitably increases.
In a transistor device, since the mobility of holes is much smaller than the mobility of electrons, the contact resistance between the source drain region and the metal contact structure is much higher for PMOS transistors than for NMOS transistors. The contact resistance of the transistor device has a great influence on the stability of the transistor, but the contact resistance of the transistor device is often too high at present, so that the device performance is low and the device stability is poor.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, which reduces the contact resistance between a source region and a drain region in a transistor device and a conductive contact structure, improves the stability of the device and improves the electrical property.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate; an epitaxial layer in the substrate, wherein the material of the epitaxial layer comprises silicon germanium, the epitaxial layer comprises a first epitaxial region and a second epitaxial region on the first epitaxial region, and the germanium concentration of the second epitaxial region is greater than that of the first epitaxial region; and a conductive contact structure on the epitaxial layer.
Optionally, the germanium concentration of the second epitaxial region is greater than 50%.
Optionally, the germanium concentration of the second epitaxial region ranges from 80% to 100%.
Optionally, the germanium concentration of the second epitaxial region ranges from 95% to 100%.
Optionally, the epitaxial layer is a source drain region of a PMOS transistor.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming an initial epitaxial structure in the substrate, wherein the material of the initial epitaxial structure comprises silicon germanium; oxidizing the surface of the initial epitaxial structure, and forming an initial oxidation layer on the surface of the initial epitaxial structure, wherein the initial epitaxial structure becomes an epitaxial layer, the epitaxial layer comprises a first epitaxial region and a second epitaxial region positioned on the first epitaxial region, and the germanium concentration of the second epitaxial region is greater than that of the first epitaxial region; removing the initial oxide layer; and forming a conductive contact structure on the epitaxial layer.
Optionally, the germanium concentration of the second epitaxial region is greater than 50%.
Optionally, the germanium concentration of the second epitaxial region ranges from 80% to 100%.
Optionally, the germanium concentration of the second epitaxial region ranges from 95% to 100%.
Optionally, the thickness of the second epitaxial region ranges from 1 nm to 3 nm.
Optionally, the technological parameters of the oxidation treatment include: the adopted temperature range is 600-1200 ℃; the reactant gas employed comprises one or more combinations of oxygen, nitrogen and argon.
Optionally, the material of the initial oxide layer includes silicon oxide.
Optionally, the process of removing the initial oxide layer includes a wet etching process or a dry etching process.
Optionally, before the oxidation treatment is performed on the initial epitaxial structure, the method further includes: and forming a first dielectric layer on the substrate, wherein a groove is formed in the first dielectric layer, and the groove exposes the surface of the initial epitaxial structure.
Optionally, after forming the epitaxial layer, before forming the conductive contact structure, the method further includes: forming a first material layer on the surface of the epitaxial layer and on the side wall of the groove; and annealing the epitaxial layer and the first material layer to form a contact layer on the epitaxial layer.
Optionally, the material of the first material layer includes titanium.
Optionally, the material of the conductive contact structure comprises a metal.
Optionally, the method for forming the conductive contact structure includes: forming an initial contact material layer in the trench; and flattening the initial contact material layer to form a conductive contact structure.
Optionally, the second epitaxial region surface has a recess toward the substrate surface.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the method for forming the semiconductor structure provided by the technical scheme of the invention, before the conductive contact structure is formed, the surface of the initial epitaxial structure is subjected to oxidation treatment, and because silicon in the initial epitaxial structure is easier to oxidize than germanium, an initial oxidation layer is formed on the surface of the initial epitaxial structure, the initial epitaxial structure is made into an epitaxial layer, the epitaxial layer comprises a first epitaxial region and a second epitaxial region positioned on the first epitaxial region, and then the initial oxidation layer is removed, so that the concentration of silicon in the second epitaxial region is reduced, germanium elements are enriched in the second epitaxial region, and the concentration of germanium is greatly improved, so that the fermi level of germanium can be pinned at the top of a valence band, the contact resistance between the epitaxial layer and the conductive contact structure is effectively reduced, and the stability and the electrical performance of a device are improved.
Further, since the surface of the second epitaxial region has a recess facing the surface of the substrate, the contact area between the epitaxial layer and the conductive contact structure is increased, and the contact resistance is further reduced.
In the semiconductor structure provided by the technical scheme of the invention, the material of the epitaxial layer comprises silicon germanium; the epitaxial layer comprises a first epitaxial region and a second epitaxial region positioned on the first epitaxial region, the germanium concentration of the second epitaxial region is larger than that of the first epitaxial region, and the Fermi level of germanium is pinned at the top of a valence band due to the higher germanium concentration in the second epitaxial region, so that the contact resistance between the epitaxial layer and a conductive contact structure is effectively reduced, and the stability and the electrical performance of the device are improved.
Drawings
Fig. 1 to 7 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, for PMOS transistors, the contact resistance between the source drain region and the metal contact structure is much higher than for NMOS transistors, since the mobility of holes is much smaller than for electrons. The contact resistance of the transistor device has a great influence on the stability of the transistor, but the contact resistance between the source and drain regions and the metal contact structure in the transistor device at present is often too high, so that the device performance is low and the device stability is poor.
In some prior art techniques, germanium concentration may be raised by implanting dopant ions within the silicon germanium source and drain regions. However, the saturation limit of the doped ions which can be implanted by the process is lower, so that the doping concentration which can be finally achieved is lower, the improvement of the germanium concentration is limited, and the resistance cannot be effectively reduced.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which is characterized in that before a conductive contact structure is formed, the surface of an initial epitaxial structure is subjected to oxidation treatment, and silicon in the initial epitaxial structure is more easily oxidized than germanium, so that an initial oxidation layer is formed on the surface of the initial epitaxial structure, the initial epitaxial structure is made into an epitaxial layer, the epitaxial layer comprises a first epitaxial region and a second epitaxial region positioned on the first epitaxial region, and then the initial oxidation layer is removed, so that the concentration of silicon in the second epitaxial region is reduced, germanium elements are enriched in the second epitaxial region, the concentration of germanium is greatly improved, the fermi level of germanium can be pinned at the top of a valence band, the contact resistance between the epitaxial layer and the conductive contact structure is effectively reduced, and the stability and the electrical performance of a device are improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 7 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided; an initial epitaxial structure 101 is formed within the substrate 100, the material of the initial epitaxial structure 101 comprising silicon germanium.
In this embodiment, the material of the substrate 100 includes silicon, silicon germanium, silicon carbide, silicon On Insulator (SOI), germanium On Insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate 100 is silicon.
In this embodiment, the initial epitaxial structure 101 provides a raw material for a subsequently formed epitaxial layer that serves as a source drain region for a PMOS transistor device.
In this embodiment, the method for forming the initial epitaxial structure 101 includes a selective epitaxial growth process.
Referring to fig. 2, a first dielectric layer 102 is formed on the substrate 100, and a trench 103 is formed in the first dielectric layer 102, where the trench 103 exposes the surface of the initial epitaxial structure 101.
In this embodiment, the trench 103 provides space for a conductive contact structure to be formed later.
In this embodiment, the method for forming the first dielectric layer 102 includes: forming an initial dielectric material layer (not shown) on the substrate 100; and etching the initial dielectric material layer to form a groove 103, wherein the groove 103 exposes the surface of the initial epitaxial structure 101, and the initial dielectric material layer becomes the first dielectric layer 102.
In this embodiment, the process of etching the initial dielectric material layer includes a wet etching process or a dry etching process.
Referring to fig. 3, an oxidation treatment is performed on the surface of the initial epitaxial structure 101, an initial oxide layer 113 is formed on the surface of the initial epitaxial structure 101, the initial epitaxial structure 101 becomes an epitaxial layer 115, the epitaxial layer 115 includes a first epitaxial region 111 and a second epitaxial region 112 located on the first epitaxial region 111, and the germanium concentration of the second epitaxial region 112 is greater than that of the first epitaxial region 111.
In this embodiment, in the oxidation treatment of the surface of the initial epitaxial structure 101, since silicon in the initial epitaxial structure 101 is more easily oxidized than germanium, an initial oxide layer 113 is formed on the surface of the initial epitaxial structure 101, and the initial epitaxial structure 101 is made into an epitaxial layer 115, and the epitaxial layer 115 includes a first epitaxial region 111 and a second epitaxial region 112 located on the first epitaxial region 111, and since the initial oxide layer 113 is formed on a part of the exposed surface of the initial epitaxial structure 101, the concentration of silicon in the second epitaxial region 112 adjacent to the initial oxide layer 113 is lower, and germanium elements are enriched in the second epitaxial region 112, and the high concentration of germanium can enable the fermi level thereof to be pinned on top of the valence band, thereby effectively reducing the contact resistance between the epitaxial layer 115 and the conductive contact structure formed subsequently, and being beneficial to improving the stability and electrical performance of the device.
In this embodiment, the material of the initial oxide layer 113 includes silicon oxide.
In this embodiment, the process parameters of the oxidation treatment include: the adopted temperature range is 600-1200 ℃; the reactant gas employed comprises one or more combinations of oxygen, nitrogen and argon.
In this embodiment, the thickness of the second epitaxial region 112 ranges from 1 nm to 3 nm, so that the contact resistance between the epitaxial layer 115 and the conductive contact structure can be reduced well after the conductive contact structure is formed later.
In this embodiment, after the surface of the initial epitaxial structure 101 is subjected to the oxidation treatment, the initial epitaxial structure 101 becomes the epitaxial layer 115, specifically, the epitaxial layer 115 includes the first epitaxial region 111 and the second epitaxial region 112 located on the first epitaxial region 111, the concentration of silicon in the second epitaxial region 112 adjacent to the initial oxide layer 113 decreases due to the formation of the initial oxide layer 113, the concentration of germanium increases, and the concentration of germanium and the concentration of silicon in the first epitaxial region 111 are not affected by the oxidation treatment, and substantially coincide with those of the initial epitaxial structure 101 before the oxidation treatment.
In this embodiment, after the oxidation process, the trench 103 exposes the surface of the initial oxide layer 113.
Referring to fig. 4, the initial oxide layer 113 is removed.
In this embodiment, after the initial oxide layer 113 is removed, the second epitaxial region 112 with high concentration of germanium is exposed, so as to facilitate reducing the contact resistance between the epitaxial layer 115 and the conductive contact structure formed later.
In this embodiment, the initial epitaxial structure 101 is subjected to oxidation treatment, and then the initial oxide layer 113 is removed, so that the germanium element is enriched in the second epitaxial region 112, and by this method, the silicon concentration in the second epitaxial region 112 can be effectively reduced, and the germanium concentration can be greatly increased. Specifically, in this embodiment, the germanium concentration in the second epitaxial region 112 may reach 95% -100%, which is significantly higher than the concentration that can be achieved by increasing the ion implantation concentration or increasing the epitaxially grown germanium concentration in the conventional process. Furthermore, the ultra-high concentration germanium can effectively pin the fermi level of the germanium at the top of the valence band, so that the contact resistance between the epitaxial layer 115 and a conductive contact structure formed subsequently is effectively reduced, and the stability and the electrical performance of the device are improved.
In another embodiment, the germanium concentration of the second epitaxial region ranges from 80% to 100%.
In other embodiments, the germanium concentration of the second epitaxial region is greater than 50%. The method for forming the semiconductor structure can adjust the germanium concentration range of the second epitaxial region according to the contact resistance of the device and the specific requirements of the process, and increase the germanium concentration of the second epitaxial region on the basis of meeting the process requirements, thereby reducing the contact resistance of the device.
In addition, in the present embodiment, the surface of the second epitaxial region 112 has a recess facing the surface of the substrate 100, so that the contact area between the epitaxial layer 115 and the conductive contact structure formed later is increased, and the contact resistance is further reduced.
In this embodiment, the process of removing the initial oxide layer 113 includes a wet etching process or a dry etching process.
Referring to fig. 5, a first material layer 120 is formed on the surface of the epitaxial layer 115 and on the sidewalls of the trench 103.
In this embodiment, the material of the first material layer 120 includes titanium.
In this embodiment, the first material layer 120 on the surface of the epitaxial layer 115 provides a raw material for a contact layer to be formed later, and at the same time, the first material layer 120 on the sidewall of the trench 103 also serves as an adhesion layer, so that the conductive contact structure is formed better in the trench 103 in a later process.
In this embodiment, the first material layer 120 is further located on the surface of the first dielectric layer 102.
In this embodiment, the forming process of the first material layer 120 includes an atomic layer deposition process or a chemical vapor deposition process.
Referring to fig. 6, the epitaxial layer 115 and the first material layer 120 are annealed, and a contact layer 131 is formed on the epitaxial layer 115.
In this embodiment, the material of the contact layer 131 includes a titanium silicon germanium compound. Because the germanium concentration of the second epitaxial region 112 in the epitaxial layer 115, which is in contact with the first material layer 120, is high, the contact layer 131 is also formed with a high germanium concentration, so that the fermi level of germanium is pinned on top of the valence band, and the contact resistance between the epitaxial layer 115 and the conductive contact structure formed subsequently is effectively reduced, which is beneficial to improving the stability and electrical performance of the device.
Referring to fig. 7, a conductive contact structure 141 is formed on the epitaxial layer 115.
In this embodiment, the conductive contact structure 141 electrically connects the epitaxial layer 115 with an upper electrical interconnect layer.
In this embodiment, the material of the conductive contact structure 141 includes a metal.
In this embodiment, the method for forming the conductive contact structure 141 includes: forming an initial contact material layer (not shown) within the trench 103; the initial contact material layer is planarized to form a conductive contact structure 141. Wherein, the planarization treatment is performed on the initial contact material layer, and the first material layer 120 on the first dielectric layer 102 is removed, so that the surface of the first dielectric layer 102 is exposed, and the first material layer 120 becomes an adhesion barrier layer 121.
In this embodiment, the planarization process includes a chemical mechanical polishing process.
In this embodiment, the epitaxial layer 115 serves as a source drain region of a PMOS transistor. Because the contact layer 131 has a very high germanium concentration, the fermi level of germanium is pinned at the top of the valence band, so that the contact resistance between the source drain region and the conductive contact structure 141 in the PMOS transistor is effectively reduced, and the stability and the electrical performance of the device are improved.
Correspondingly, the embodiment of the invention also provides a semiconductor structure formed by adopting the method.
With continued reference to fig. 7, the semiconductor structure includes: a substrate 100; an epitaxial layer 115 within the substrate 100, the material of the epitaxial layer 115 comprising silicon germanium, the epitaxial layer 115 comprising a first epitaxial region 111 and a second epitaxial region 112 on the first epitaxial region 111, the second epitaxial region 112 having a germanium concentration greater than the germanium concentration of the first epitaxial region 111; a conductive contact structure 141 located on the epitaxial layer 115.
In this embodiment, the semiconductor structure further includes: and a contact layer 131 between the epitaxial layer 115 and a conductive contact structure 141, the conductive contact structure 141 being in contact with the contact layer 131. The material of the contact layer 131 includes a titanium silicon germanium compound.
In this embodiment, the semiconductor structure further includes: a first dielectric layer 102 on the substrate 100, and the conductive contact structure 141 is located in the first dielectric layer 102.
In this embodiment, an adhesion barrier layer 121 is further disposed between the first dielectric layer 102 and the conductive contact structure 141.
In this embodiment, the epitaxial layer 115 is a source drain region of a PMOS transistor.
In this embodiment, the germanium concentration in the second epitaxial region 112 ranges from 95% to 100%. Due to the higher concentration of germanium in the second epitaxial region 112, the concentration of germanium in the contact layer 131 is also high, so that the fermi level of germanium is pinned on top of the valence band, thereby effectively reducing the contact resistance between the epitaxial layer 115 and the conductive contact structure 141, and improving the stability and electrical performance of the device.
In another embodiment, the germanium concentration of the second epitaxial region ranges from 80% to 100%.
In other embodiments, the germanium concentration of the second epitaxial region is greater than 50%.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A semiconductor structure, comprising:
A substrate;
An epitaxial layer in the substrate, wherein the material of the epitaxial layer comprises silicon germanium, the epitaxial layer comprises a first epitaxial region and a second epitaxial region on the first epitaxial region, and the germanium concentration of the second epitaxial region is greater than that of the first epitaxial region;
and a conductive contact structure on the epitaxial layer.
2. The semiconductor structure of claim 1, wherein a germanium concentration of the second epitaxial region is greater than 50%.
3. The semiconductor structure of claim 2, wherein a germanium concentration of said second epitaxial region ranges from 80% to 100%.
4. The semiconductor structure of claim 3, wherein a germanium concentration of said second epitaxial region ranges from 95% to 100%.
5. The semiconductor structure of claim 1, wherein the epitaxial layer is a source drain region of a PMOS transistor.
6.A method of forming a semiconductor structure, comprising:
Providing a substrate;
Forming an initial epitaxial structure in the substrate, wherein the material of the initial epitaxial structure comprises silicon germanium; oxidizing the surface of the initial epitaxial structure, and forming an initial oxidation layer on the surface of the initial epitaxial structure, wherein the initial epitaxial structure becomes an epitaxial layer, the epitaxial layer comprises a first epitaxial region and a second epitaxial region positioned on the first epitaxial region, and the germanium concentration of the second epitaxial region is greater than that of the first epitaxial region;
removing the initial oxide layer;
and forming a conductive contact structure on the epitaxial layer.
7. The method of forming a semiconductor structure of claim 6, wherein a germanium concentration of said second epitaxial region is greater than 50%.
8. The method of forming a semiconductor structure of claim 7, wherein a germanium concentration of said second epitaxial region ranges from 80% to 100%.
9. The method of forming a semiconductor structure of claim 8, wherein a germanium concentration of said second epitaxial region ranges from 95% to 100%.
10. The method of forming a semiconductor structure of claim 6, wherein a thickness of said second epitaxial region ranges from 1 nm to 3 nm.
11. The method of forming a semiconductor structure of claim 6, wherein the process parameters of the oxidation process comprise: the adopted temperature range is 600-1200 ℃; the reactant gas employed comprises one or more combinations of oxygen, nitrogen and argon.
12. The method of forming a semiconductor structure of claim 6, wherein the material of the initial oxide layer comprises silicon oxide.
13. The method of forming a semiconductor structure of claim 6, wherein the process of removing the initial oxide layer comprises a wet etch process or a dry etch process.
14. The method of forming a semiconductor structure of claim 6, further comprising, prior to the oxidizing the initial epitaxial structure: and forming a first dielectric layer on the substrate, wherein a groove is formed in the first dielectric layer, and the groove exposes the surface of the initial epitaxial structure.
15. The method of forming a semiconductor structure of claim 14, further comprising, after forming the epitaxial layer, prior to forming the conductive contact structure: forming a first material layer on the surface of the epitaxial layer and on the side wall of the groove; and annealing the epitaxial layer and the first material layer to form a contact layer on the epitaxial layer.
16. The method of forming a semiconductor structure of claim 15, wherein the material of the first material layer comprises titanium.
17. The method of forming a semiconductor structure of claim 6, wherein the material of the conductive contact structure comprises a metal.
18. The method of forming a semiconductor structure of claim 14, wherein the method of forming the conductive contact structure comprises: forming an initial contact material layer in the trench; and flattening the initial contact material layer to form a conductive contact structure.
19. The method of forming a semiconductor structure of claim 6, wherein the second epitaxial region surface has a recess toward a substrate surface.
CN202211459339.9A 2022-11-21 2022-11-21 Semiconductor structure and forming method thereof Pending CN118057620A (en)

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CN118057620A true CN118057620A (en) 2024-05-21

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