CN118042828A

CN118042828A - Three-dimensional semiconductor memory device and method of forming the same

Info

Publication number: CN118042828A
Application number: CN202211391444.3A
Authority: CN
Inventors: 李晓杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-11-07
Filing date: 2022-11-07
Publication date: 2024-05-14
Also published as: WO2024098708A1

Abstract

The present disclosure provides a three-dimensional semiconductor memory device and a method of forming the same, the method including: forming a stacked structure on a substrate, and forming an isolation structure in the stacked structure; the isolation structure separates the stacked structure into a conductive line area and a storage area; etching the isolation structure to form a plurality of first openings exposing the capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate; forming a capacitor structure which is arranged in an array along a first direction and a second direction in the capacitor region; the first electrode of the capacitor structure is exposed in the first opening; a common terminal lead-out structure is formed in the first opening that electrically connects the first electrode of the capacitive structure to the substrate. According to the three-dimensional semiconductor storage device, the common electrode of the capacitor structure in the three-dimensional semiconductor storage device is electrically connected to the substrate through the common terminal leading-out structure, and the substrate provides a common power supply for the capacitor structure, so that the number of power supply pads required by a bonding interface can be reduced, and the integration level of the three-dimensional semiconductor storage device is effectively improved.

Description

Three-dimensional semiconductor memory device and method of forming the same

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a three-dimensional semiconductor memory device and a method for forming the same.

Background

The degree of integration of a two-dimensional semiconductor memory device is mainly determined by the area occupied by memory cells, and thus the degree of integration thereof greatly influences the level of fine pattern formation technology. In order to overcome the limitation of the fine pattern technology level on the integration level of the semiconductor memory device, a three-dimensional semiconductor memory device including memory cells arranged in three dimensions has recently been proposed.

However, the conventional three-dimensional semiconductor memory device and the method for forming the same still have certain drawbacks, and how to further improve the integration level and reliability of the three-dimensional semiconductor memory device is a problem that needs to be solved at present.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a three-dimensional semiconductor memory device and a method for forming the same to solve at least one of the problems in the prior art.

In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows:

in a first aspect, embodiments of the present disclosure provide a method of forming a three-dimensional semiconductor memory device, the method including:

forming a storage stack structure on a substrate, and forming an isolation structure in the storage stack structure; the isolation structure separates the storage stack structure into a conductive line area and a storage area;

etching the isolation structure to form a plurality of first openings exposing the capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate;

Forming a capacitor structure which is arranged in an array along a first direction and a second direction in the capacitor region; a first electrode of the capacitive structure is exposed in the first opening; the capacitor structure extends along a third direction;

A common terminal lead-out structure is formed in the first opening that electrically connects the first electrode of the capacitive structure to the substrate.

In an alternative embodiment, before the capacitor areas form the capacitor structures arranged in the array along the first direction and the second direction, the method further includes:

Forming active structures arranged in an array along the first direction and the second direction in the transistor area in the storage area; the active structure extends along a third direction and comprises a first source drain region, a channel region and a second source drain region; the second electrode of the capacitor structure is electrically connected with the first source drain region in the active structure.

In an alternative embodiment, the method for forming a three-dimensional semiconductor memory device further includes:

Etching the isolation structure to form a second opening exposing the channel region; an isolation structure between the bottom of the second opening and the substrate forms a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of an initial oxide layer between the substrate and the storage stack structure;

forming a word line structure extending in the first direction in the second opening;

And forming a bit line structure which is arranged along the first direction, extends along the second direction and is electrically connected with the second source drain region in the conductive line region.

Etching the isolation structure to form a third opening exposing the second source drain region; an isolation structure between the bottom of the third opening and the substrate forms a shallow trench isolation structure; the thickness of the shallow trench isolation structure in the first direction is greater than the thickness of an initial oxide layer between the substrate and the storage stack structure;

forming a plurality of bit line structures extending in the first direction in the third opening, wherein the bit line structures are electrically connected with the second source drain regions;

And forming word line structures which are arranged along the first direction, extend along the second direction and are positioned on two sides of the channel region in the conductive line region.

In an alternative embodiment, the capacitor structures are symmetrically distributed on two sides of the bit line structure along the third direction; or the capacitor structure is distributed on one side of the bit line structure.

In an alternative embodiment, the forming a common terminal lead-out structure in the first opening, which electrically connects the first electrode of the capacitor structure to the substrate, includes:

sequentially forming a metal silicide layer and an adhesive layer on the surface of the substrate exposed by the first opening;

Depositing the conductive material on the adhesive layer to fill the first opening; the conductive material comprises polysilicon.

In an alternative embodiment, the forming an isolation structure in the storage stack structure includes:

Etching the initial stack structure in the first direction to form a plurality of isolation trenches penetrating the initial stack structure and exposing the substrate;

And filling insulating materials in the isolation trenches to form the isolation structures.

In an alternative embodiment, the storage stack structure includes dielectric layers and semiconductor layers alternately stacked along the first direction; the forming of the capacitor structure arranged in the array along the first direction and the second direction in the capacitor region includes:

Etching the dielectric layer in the third direction to form a fourth opening of the semiconductor layer exposing the capacitor region, wherein the fourth opening is communicated with the first opening;

And forming the second electrode, the capacitor dielectric layer and the first electrode of the capacitor structure on the surface of the semiconductor layer exposed by the first opening and the fourth opening in sequence.

And filling the conductive material in the first opening and between the capacitor structures to form the common terminal lead-out structure.

In a second aspect, embodiments of the present disclosure provide a three-dimensional semiconductor memory device including:

A substrate;

a memory structure located on the substrate;

The storage structure comprises capacitor structures which are arranged in an array along a first direction and a second direction; the capacitor structure extends along a third direction; the first direction is the thickness direction of the substrate, and the second direction and the third direction are perpendicular to the first direction;

the bottom surface of the common end leading-out structure is lower than the top surface of the substrate; the common terminal lead-out structure is electrically connected with the first electrode of the capacitor structure and the substrate.

In an alternative embodiment, the storage structure further includes:

An active structure extending along the third direction; the active structure comprises a first source drain region, a channel region and a second source drain region which are sequentially arranged along the third direction; and a second electrode of the capacitor structure is electrically connected with the first source-drain region.

In an alternative embodiment, the three-dimensional semiconductor memory device further includes:

A word line structure extending along the first direction; the word line structures are positioned on two opposite sides of the channel region along the second direction;

a shallow trench isolation structure located between the word line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is larger than that of the initial oxide layer; the initial oxide layer is positioned between the substrate and the storage structure;

and the bit line structure is arranged along the first direction, extends along the second direction and is electrically connected with the second source-drain region.

a bit line structure extending along the first direction; the bit line structure is electrically connected with the second source drain region;

A shallow trench isolation structure located between the bottom of the bit line structure and the substrate; the thickness of the shallow trench isolation structure in the first direction is larger than that of the initial oxide layer; the initial oxide layer is positioned between the substrate and the storage structure;

And the word line structure is arranged along the first direction, extends along the second direction and is positioned at two sides of the channel region.

In an alternative embodiment, the capacitor structures are symmetrically distributed on two sides of the bit line structure along the third direction; or the capacitor structure is located on one side of the bit line structure.

A metal silicide layer positioned between the common terminal lead-out structure and the substrate;

An adhesive layer located between the common terminal lead-out structure and the metal silicide layer; the material of the common terminal lead-out structure comprises polysilicon.

In the technical scheme provided by the disclosure, the common electrode of the capacitor structure in the three-dimensional semiconductor storage device is electrically connected to the substrate by forming the common terminal lead-out structure, so that the common voltage can be provided for the capacitor structure through the substrate, the number of power supply pads required by the bonding interface is reduced, and the integration level of the three-dimensional semiconductor storage device is effectively improved.

Drawings

Fig. 1 is a flow chart illustrating a method for forming a three-dimensional semiconductor memory device according to an embodiment of the disclosure;

FIGS. 2a-2r are schematic diagrams illustrating a three-dimensional semiconductor memory device formation process according to embodiments of the present disclosure;

fig. 3 is a schematic structural diagram of a three-dimensional semiconductor memory device according to another embodiment of the present disclosure;

Fig. 4a-4j are schematic structural diagrams illustrating a three-dimensional semiconductor memory device forming process according to another embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be appreciated that spatially relative terms such as "under … …," "under … …," "under … …," "over … …," "over" and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to improve the storage capacity of semiconductor memory devices, three-dimensional semiconductor memory devices including memory cells arranged in three dimensions have been proposed. The memory array and the peripheral circuit of the three-dimensional semiconductor memory device can be respectively formed in different wafers, and a wafer bonding structure is formed through a wafer bonding technology, so that the integration level of the semiconductor memory device is effectively improved. In the presently proposed wafer bonding structure, a bonding interface on a memory array wafer includes a plurality of bonding pads for wafer bonding and a plurality of power supply pads for providing a common voltage to a common electrode of a capacitor structure. As the number of capacitor structures in the memory array increases, the density of bonding pads disposed on the bonding interface increases, resulting in a larger parasitic capacitance of the bonding interface, which can negatively affect signal transmission between the memory array and peripheral circuitry. Meanwhile, since the area of the bonding interface is limited, the number of pads provided on the bonding interface is limited, which limits the improvement of the integration of the three-dimensional semiconductor memory device.

In addition, in the presently proposed three-dimensional semiconductor memory device forming method, a word line structure or a bit line structure perpendicular to a substrate is generally formed by filling a conductive material after forming a word line opening or a bit line opening in a stacked structure, however, since the thickness of an initial oxide layer between the stacked structure and the substrate is small, there is a risk that leakage occurs between the word line structure or the bit line structure and the substrate due to penetration of the initial oxide layer.

Therefore, it is necessary to further improve the integration and reliability of the three-dimensional semiconductor memory device. In this regard, the present disclosure proposes the following embodiments.

The embodiment of the disclosure provides a forming method of a three-dimensional semiconductor memory device. Fig. 1 is a flowchart illustrating a method for forming a three-dimensional semiconductor memory device according to an embodiment of the disclosure. As shown in fig. 1, the method for forming the three-dimensional semiconductor memory device includes the steps of:

Step 101: forming a storage stack structure on a substrate, and forming an isolation structure in the storage stack structure; the isolation structure separates the storage stack structure into a conductive line area and a storage area;

Step 102: etching the isolation structure to form a plurality of first openings exposing the capacitor region in the storage region and the substrate; the bottom surface of the first opening is lower than the top surface of the substrate;

Step 103: forming a capacitor structure which is arranged in an array along a first direction and a second direction in the capacitor region; a first electrode of the capacitive structure is exposed in the first opening; the capacitor structure extends along a third direction;

step 104: a common terminal lead-out structure is formed in the first opening that electrically connects the first electrode of the capacitive structure to the substrate.

Fig. 2a to 2r are schematic structural views illustrating a process of forming a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. Next, a method of forming the three-dimensional semiconductor memory device provided in the embodiments of the present disclosure will be described in detail with reference to fig. 1, 2a to 2 r.

In some embodiments, referring to fig. 2a, a method of forming a three-dimensional semiconductor memory device includes: an initial stacked structure is formed on the substrate 201.

In some embodiments, the substrate 201 may be a simple substance semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

In some embodiments, the substrate 201 is a P-type substrate or an N-type substrate.

In the embodiment of the present disclosure, before forming the memory stack structure on the substrate 201, the initial oxide layer 202 is formed on the substrate 201, and then the initial stack structure is formed on the initial oxide layer 202. The initial stacked structure includes the semiconductor layers 203 and the sacrificial layers 204 alternately stacked in the first direction. The semiconductor layer 203 may be formed of a semiconductor material such as silicon, germanium, or indium gallium zinc oxide, and the sacrificial layer 204 may be formed of a material having a high etching selectivity with respect to the semiconductor layer 203, for example, the sacrificial layer 203 may be formed of silicon germanium.

In some embodiments, after forming the memory stack structure on the substrate 201, the initial stack structure includes the semiconductor layers 203 and the sacrificial layers 204 alternately stacked in the first direction, including removing the sacrificial layers 204 to expose the surface of the substrate 201, and then forming the initial oxide layer 202 on the surface of the substrate 201.

In the embodiment of the disclosure, the first direction is the thickness direction of the substrate 201, i.e. the Z direction, the second direction is the Y direction, the third direction is the X direction, both the second direction and the third direction are perpendicular to the first direction, and the second direction and the third direction are parallel to the top surface of the substrate.

In some embodiments, as shown in connection with fig. 2a and 2b, the method for forming a three-dimensional semiconductor memory device further includes: the initial stack and the substrate 201 are etched in a first direction to form a plurality of isolation trenches 205 extending through the initial stack and into the substrate 201.

It should be noted that fig. 2b only exemplifies that four isolation trenches 205 are formed in the initial stacked structure, but the embodiments of the present disclosure are not limited thereto, and for example, only a plurality of isolation trenches 205 on a single side may be formed. The structure of fig. 2c is part of the structure of fig. 2b, and in order to facilitate the observation of the structure formed by the subsequent steps, the subsequent steps are described below on the basis of the structure of fig. 2 c.

In some embodiments, as shown in connection with fig. 2c and 2d, the method for forming a three-dimensional semiconductor memory device further includes: after forming the plurality of isolation trenches 205 in the initial stacked structure, the sacrificial layer 204 is replaced with a dielectric material to form a memory stacked structure in which the semiconductor layers 203 and the dielectric layers 206 are alternately stacked in the first direction. As shown in fig. 2d, the isolation trench 205 separates the memory stack structure into a conductive line region extending in the second direction and a memory region located on opposite sides of the conductive line region in the third direction. The conductive line region is a formation region of the bit line structure, the storage region is a formation region of the storage unit, the storage unit comprises a transistor structure and a capacitor structure, the storage region comprises two parts symmetrically distributed relative to the conductive line region, and each part comprises a transistor region connected with the conductive line region and a capacitor region far away from the conductive line region.

In some embodiments, the method of forming a three-dimensional semiconductor memory device further includes: active structures are formed in the semiconductor layer 203 extending in the third direction in the transistor region by ion implantation, each of which includes a first source drain region 207, a channel region 208, and a second source drain region 209. The first source drain region 207 is used as one of a source region or a drain region, and the second source drain region 209 is used as the other of the source region or the drain region. As shown in fig. 2d, the active structure is symmetrically arranged with respect to the conductive line region extending along the second direction, wherein the active structure on one side of the conductive line region includes a first source drain region 207, a channel region 208, and a second source drain region 209 sequentially arranged along the third direction, and the active structure on the other side of the conductive line region includes a second source drain region 209, a channel region 208, and a first source drain region 207 sequentially arranged along the third direction.

In a specific example, the first source drain region 207 and the second source drain region 209 in the active structure are N-type doped, and the channel region 208 is P-type doped. In another specific example, the first source drain region 207 and the second source drain region 209 in the active structure are P-type doped, and the channel region 208 is N-type doped.

In some embodiments, as shown in conjunction with fig. 2d and 2e, the method for forming a three-dimensional semiconductor memory device further includes: the plurality of isolation trenches 205 are filled with an insulating material to form a plurality of isolation structures 210.

In other embodiments, the exposed substrate of the isolation trench 205 may also be oxidized by a thermal oxidation process and then the remaining portion of the isolation trench 205 may be filled with an insulating material to form the plurality of isolation structures 210.

It should be noted that one of the four isolation structures 210 shown in the drawings is a perspective effect, so as to facilitate observation of the structure formed by the subsequent steps.

In a specific example, an insulating material may be deposited in the isolation trenches 205 by low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), or atomic layer Deposition (Atom Layer Deposition, ALD) to form the isolation structures 210, the insulating material comprising silicon oxide. In another specific example, the remaining portion of the isolation trench 205 may also be filled with an insulating material after oxidizing the substrate 201 exposed by the isolation trench 205 by a thermal oxidation process to form the isolation structure 210.

In some embodiments, as shown in connection with fig. 2e and 2f, the method for forming a three-dimensional semiconductor memory device further includes: each of the isolation structures 210 is etched in the first direction and stopped in the isolation structure 210 to form a second opening 211 exposing the plurality of channel regions 208 in the transistor region, a bottom surface of the second opening 211 may be lower than a bottom surface of the lowermost semiconductor layer 203, and a bottom surface of the second opening 211 may also be higher than a top surface of the substrate 201. Referring to fig. 2f, two columns of active structures arranged in a first direction are formed in the three-dimensional semiconductor memory device, and in a second direction, second openings 211 are located at both sides of a channel region 208 in each column of active structures.

Fig. 2g is a cross-sectional view along line AA' of fig. 2f, as shown in fig. 2g, after etching the isolation structure 210 in the first direction, the isolation structure remaining between the bottom of the second opening 211 and the substrate 201 forms a shallow trench isolation structure 212, and a thickness T1 of the shallow trench isolation structure 212 in the first direction is greater than a thickness T2 of the initial oxide layer 202 between the substrate and the storage stack structure.

In some embodiments, as shown in connection with fig. 2f and 2h, the method for forming a three-dimensional semiconductor memory device further includes: the second opening 211 is filled with a conductive material to form a word line structure 213 extending in the first direction on the shallow trench isolation structure 212. Fig. 2i is a cross-sectional view along line AA' of fig. 2h, as shown in fig. 2i, in a specific example, a gate dielectric layer 214 is formed in the second opening 211 on a side close to the channel region 208, and then a conductive material is filled in the second opening 211 to form a word line structure 213. A shallow trench isolation structure 212 is formed between the bottom of the word line structure 213 and the substrate 201, and has a thickness T1 in the first direction that is greater than a thickness T2 of the initial oxide layer 202. In a specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is 3 times the thickness T2 of the initial oxide layer 202. In another specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is 6 times the thickness T2 of the initial oxide layer 202.

In some embodiments, the method of forming a three-dimensional semiconductor memory device further includes: the dielectric layer 206 of the channel region 208 exposed by the second opening 211 is removed to obtain a suspended semiconductor layer 203, a gate dielectric layer 214 is formed on the periphery of the channel region 208 exposed by the semiconductor layer 203, and a conductive material is refilled to form a word line structure 213, where the word line structure 213 may also be located between the semiconductor layers 203 in the first direction.

In the embodiment of the present disclosure, an active structure is formed in the semiconductor layer 203 in the transistor region, the active structure including a first source drain region 207, a channel region 208, and a second source drain region 209, a word line structure 213 extending along a first direction is formed beside the channel region 208 as a gate of the transistor structure, and thus, a transistor structure is formed in the transistor region, and a plurality of transistor structures having the same word line structure 213 as a gate are arranged along the first direction.

In the currently proposed method for forming the three-dimensional semiconductor memory device, the word line opening is generally formed by etching the stacked structure, however, due to the small thickness of the initial oxide layer on the substrate, the initial oxide layer may be penetrated during the etching of the stacked structure, thereby causing leakage between the word line structure and the substrate.

In the embodiment of the disclosure, the isolation structure 210 extending into the substrate 201 is formed in the storage stack structure, then the isolation structure 210 is etched in the first direction to form the second opening 211, the isolation structure between the bottom of the second opening 211 and the substrate 201 forms the shallow trench isolation structure 212, the thickness T1 of the shallow trench isolation structure 212 in the first direction is greater than the thickness T2 of the initial oxide layer 202, and then the second opening 211 is filled with the conductive material to form the word line structure 213 on the shallow trench isolation structure 212, so that the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 has a larger thickness, thereby preventing leakage between the word line structure 213 and the substrate 201 and effectively improving the reliability of the three-dimensional semiconductor memory device.

In some embodiments, the conductive material forming the word line structure 213 may be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The gate dielectric layer 214 may be formed of or include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride. The high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In some embodiments, as shown in fig. 2j, the method for forming a three-dimensional semiconductor memory device further includes: a plurality of bit line structures 220 are formed in the conductive line regions extending in the second direction. The bit line structures 220 extend in the second direction, are alternately arranged with the dielectric layer 206 in the first direction, and are electrically connected with the drain regions 209 at both sides of the conductive line region. The bit line structures 220 and the word line structures 213 extend in directions perpendicular to each other, and for an active structure, the channel region 208 is connected to a word line structure 213 extending in a first direction and the drain region 209 is connected to a bit line structure 220 extending in a second direction.

In a specific example, as shown in connection with fig. 2h and 2j, the step of forming the bit line structure 220 includes: the conductive line region is etched in the second direction to remove the semiconductor layer 203 extending in the second direction in the conductive line region, and the etched openings are filled with a conductive material to form a plurality of bit line structures 220 extending in the second direction.

In embodiments of the present disclosure, an isotropic etching process is employed to form an opening extending in a certain direction in an isolation structure or a stacked structure.

In some embodiments, as shown in connection with fig. 2j and 2k, the method for forming a three-dimensional semiconductor memory device further includes: etching the isolation structure 210 in a first direction to form a plurality of first openings 240 exposing the capacitive regions in the regions and the substrate 201, a bottom surface of the first openings 240 being lower than a top surface of the substrate 201 under the isolation structure 210; the dielectric layer 206 extending in the third direction in the capacitor region is etched through the first opening 240 to form a plurality of fourth openings 230, the fourth openings 230 being in communication with the first opening 240.

In some embodiments, as shown in fig. 2l, the method for forming a three-dimensional semiconductor memory device further includes: after the fourth opening 230 and the first opening 240 are formed, a capacitor structure 231 is formed on the surface of the semiconductor layer 203 exposed by the fourth opening 230 and the first opening 240, and the capacitor structure 231 is symmetrically distributed on both sides of the bit line structure 220 along the third direction.

Note that, in the embodiment of the present disclosure, only the capacitor structure 231 is electrically connected to the first source drain region 207, and the bit line structure 220 is electrically connected to the second source drain region 209. In some embodiments, the second source drain region may also be electrically connected to the capacitor structure, and the first source drain region may be electrically connected to the bit line structure.

In a specific example, the cross-section of the capacitor structure 231 shown in fig. 2l is shown in fig. 2m, and the step of forming the capacitor structure 231 includes: the first source and drain region 207 surrounding the end of the semiconductor layer sequentially forms a second electrode 2311, a capacitor dielectric layer 2312 and a first electrode 2313 of the capacitor structure 231. The second electrode 2311 is electrically connected to the first source/drain region 207. In another specific example, as shown in fig. 2n, the step of forming the capacitor structure 231 includes: etching the semiconductor material layer 203 extending in the third direction in the capacitor region to form a plurality of capacitor openings; a second electrode 2314, a capacitance dielectric layer 2315 and a first electrode 2316 of the capacitance structure 231 are sequentially formed in the capacitance opening; the second electrode 2314 is electrically connected to the first source drain region 207. After forming the capacitor structure 231, the isolation structure 210 is etched in a first direction to form a first opening exposing the capacitor structure 231 and the substrate 201.

It should be noted that, in the embodiment of the present disclosure, the fourth opening 230 and the first opening 240 may be formed first, and then the capacitor structure shown in fig. 2m may be formed, or the capacitor opening and the capacitor structure shown in fig. 2n may be formed first, and then the first opening 240 may be formed, which is not limited in this disclosure. In the following embodiments, the description of the subsequent steps is made taking the formation of the capacitor structure shown in fig. 2m as an example.

In the embodiment of the present disclosure, the capacitor structure 231 is formed in the capacitor region in the memory region, and the second electrode 2311 of the capacitor structure 231 is electrically connected to the first source drain region 207 of the transistor structure located in the same semiconductor layer 203, whereby one capacitor structure 231 corresponds to one transistor structure electrically connected thereto, thereby constituting one memory cell. The memory cells are arranged in an array along a first direction and a second direction to form a memory structure in the three-dimensional semiconductor memory device.

In some embodiments, as shown in fig. 2l and 2o, the method for forming a three-dimensional semiconductor memory device further includes: the plurality of first openings 240 are filled with a conductive material to form a common terminal lead-out structure 241, the common terminal lead-out structure 241 electrically connecting the first electrode of the capacitor structure 231 to the substrate 201. The bottom surface of the common terminal extraction structure 241 may be flush with the bottom surfaces of the isolation structures 210 and the shallow trench isolation structures 212.

In a specific example, fig. 2p is a cross-sectional view along line BB' of fig. 2o, and as shown in fig. 2p, the step of forming the common terminal lead-out structure 241 further includes: the remaining portions of the plurality of fourth openings 230 are filled with a conductive material while the plurality of first openings 240 are filled with a conductive material, whereby the common terminal extraction structure 241 further comprises a portion 241' located between the two capacitor structures 231 in the first direction and extending in the third direction.

In a specific example, as shown in connection with fig. 2l and 2q, the step of forming the common terminal lead-out structure 241 further includes: a metal silicide layer 242 and an adhesive layer 243 are sequentially formed on the exposed substrate surface of the first opening 240, and a conductive material is deposited on the adhesive layer 243 to fill the first opening 240. The metal silicide layer 242 and the adhesive layer 243 may effectively reduce the contact resistance between the common terminal lead-out structure 241 and the substrate 201. The bottom surface of the metal silicide layer 242 may be flush with the bottom surfaces of the isolation structures 210 and the shallow trench isolation structures 212

In embodiments of the present disclosure, the conductive material forming the common terminal lead-out structure 241 may be a doped semiconductor material (e.g., doped polysilicon, doped silicon germanium, etc.); the material of the metal silicide layer 242 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 243 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

In the embodiment of the disclosure, the common electrode of the capacitor structure is electrically connected to the substrate by forming the common terminal lead-out structure, so that the common voltage can be provided to the common electrode of the capacitor structure through the substrate. Therefore, in the formation process of the back-end interconnection layer, a power supply pad for providing a common voltage for the common electrode of the capacitor structure is not required to be arranged in a bonding interface on the storage array wafer, so that the density of the pads in the bonding interface can be reduced, and parasitic capacitance among the pads is reduced. In addition, the density of the capacitor structure in the memory array can be further increased under the condition that the density of the bonding pads in the bonding interface is kept unchanged, so that the integration level of the three-dimensional semiconductor memory device is improved.

In the disclosed embodiments, the common voltage may be half the power supply voltage, i.e., V _CC/2.

In some embodiments, as shown in fig. 2r, the three-dimensional semiconductor memory device finally formed by the above method includes a plurality of three-dimensional structures shown in fig. 2o, the memory structures are symmetrically distributed on two sides of the bit line structure 220, the memory structures include memory cells composed of a transistor structure and a capacitor structure 231, and the memory cells are arranged in an array along a first direction and a second direction; a shallow trench isolation structure 212 is formed between the word line structure 213 and the substrate 201, and has a thickness T1 in the first direction greater than a thickness T2 of the initial oxide layer 202; the common terminal lead-out structure 241 electrically connects the first electrodes 2313 of the plurality of capacitor structures 231 to the substrate 201.

In some embodiments, a thickness T1 of the shallow trench isolation structure 212 between the bottom of the word line structure 213 and the substrate 201 in the first direction is greater than a maximum distance between the memory structure and the substrate 201. Here, the maximum distance between the memory structure and the substrate 201 may be the distance between the bottom of the active structure closest to the substrate 201 and the substrate 201. Thus, leakage between the word line structure 213 and the substrate 201 can be effectively prevented.

In some embodiments, the three-dimensional semiconductor memory device shown in fig. 3 may also be formed by a method similar to the method of forming the three-dimensional semiconductor memory device described above. In the formation of the three-dimensional semiconductor memory device, a memory cell including a transistor structure and a capacitor structure 331 is formed on the same side of the bit line structure 320, and an active structure in the transistor structure includes a second source drain region 309, a channel region 308, and a first source drain region 307 sequentially arranged in a third direction. The formation process of the three-dimensional semiconductor memory device is similar to that of the three-dimensional semiconductor memory device shown in fig. 2q, and thus, a description thereof will not be repeated.

Fig. 4a to 4j are schematic structural diagrams illustrating a three-dimensional semiconductor memory device forming process according to another embodiment of the present disclosure. Next, a description will be given of a difference between a method of forming a three-dimensional semiconductor memory device according to another embodiment of the present disclosure and a method of forming a three-dimensional semiconductor memory device shown in fig. 2a to 2r, with reference to fig. 1, 4a to 4 j.

In order to facilitate observation of the formation process of the three-dimensional semiconductor memory device, the structures shown in fig. 4a to 4j are only partial structures in the three-dimensional semiconductor memory device.

In some embodiments, referring to fig. 4a, a method of forming a three-dimensional semiconductor memory device includes: forming an initial stacked structure on a substrate 401; forming a plurality of isolation trenches 405 and 405' extending through the initial stack structure and into the substrate 401; the sacrificial layer in the initial stack is replaced with a dielectric layer 406 to form a storage stack. Isolation trenches 405 and 405' extend into substrate 401 separating the memory stack structure into two portions that are symmetrical to each other, each portion including a memory region and a conductive line region. The conductive line region extends along the second direction and is a forming region of the word line structure; the memory region is a formation region of a memory cell, the memory cell includes a transistor structure and a capacitor structure, and the memory region includes a transistor region cross-connected with the conductive line region and a capacitor region distant from the conductive line region in a third direction.

In the embodiment of the disclosure, the first direction is the thickness direction of the substrate 401, i.e., the Z direction, the second direction is the Y direction, the third direction is the X direction, and both the second direction and the third direction are perpendicular to the first direction.

In some embodiments, referring to fig. 4a, the method of forming a three-dimensional semiconductor memory device further includes: forming an active structure in each of the semiconductor layers 403 extending in the third direction in the transistor region; the active structure includes a first source drain region 407, a channel region 408, and a second source drain region 409 sequentially arranged in a third direction, the channel region 408 being located at the intersection of the conductive line region and the memory region.

In some embodiments, as shown in connection with fig. 4a and 4b, the method for forming a three-dimensional semiconductor memory device further includes: filling the plurality of isolation trenches 405 and 405 'with an insulating material to form a plurality of isolation structures 410 and 410'; or the substrate 401 exposed by the isolation trenches 405 and 405' is oxidized first by a thermal oxidation process and then the remaining portions of the isolation trenches 405 and 405' are filled with an insulating material to form a plurality of isolation structures 410 and 410'.

It should be noted that, the isolation structure 410' is shown in the figure as a perspective effect, so as to facilitate the observation of the structure formed by the subsequent steps.

In some embodiments, as shown in connection with fig. 4b to 4d, where fig. 4d is a cross-sectional view along line AA' of fig. 4c, the method for forming a three-dimensional semiconductor memory device further includes: etching the isolation structure 410' in the first direction to form a third opening 420 exposing the second source drain region 409, wherein the isolation structure between the bottom of the third opening 420 and the substrate 401 constitutes a shallow trench isolation structure 412; the thickness T3 of the shallow trench isolation structure 412 in the first direction is greater than the thickness T4 of the initial oxide layer 402 between the substrate and the memory stack structure. In a specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 3 times the thickness T4 of the initial oxide layer 402. In another specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 6 times the thickness T4 of the initial oxide layer 402.

In some embodiments, as shown in connection with fig. 4c and 4e, the method for forming a three-dimensional semiconductor memory device further includes: the third opening 420 is filled with a conductive material to form a bit line structure 421 extending in the first direction over the shallow trench isolation structure 412. As shown in fig. 4e, the bit line structure 421 is electrically connected to the second source drain regions 409 on opposite sides thereof in the third direction. In some embodiments, the conductive material forming the bit line structure 421 may be one of a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

In some embodiments, as shown in conjunction with fig. 4e and 4f, the method for forming a three-dimensional semiconductor memory device further includes: a plurality of word line structures 413 are formed in the conductive line region extending in the second direction, are arranged in the first direction, extend in the second direction, and are located at both sides of the channel region 408, and the extending directions of the word line structures 413 and the bit line structures 421 are perpendicular to each other. Note that, referring to fig. 4j, a specific structure of the word line structure 413 may be that, in the first direction, a gate dielectric layer 414 is formed between the word line structure 413 and the channel region 408, and an insulating material is filled between two adjacent word line structures 413.

In the embodiment of the present disclosure, an active structure is formed in the semiconductor layer 403 in the transistor region in the memory region, the active structure including a first source drain region 407, a channel region 408, and a second source drain region 409, and a word line structure 413 located on opposite sides of the channel region 408 in the active structure in the first direction is formed in the conductive line region extending in the second direction as a gate electrode of the transistor structure, whereby a transistor structure is formed in the transistor region, and a plurality of transistor structures having the same word line structure 413 as the gate electrode are arranged in the second direction.

In some embodiments, as shown in connection with fig. 4f and 4g, the method of forming a three-dimensional semiconductor memory device further includes: etching the plurality of isolation structures 410 in a first direction to form a plurality of first openings 440 exposing the capacitor region and the substrate 401, a bottom surface of the first openings being lower than a top surface of the substrate 401 in the storage region; dielectric layer 406, which extends in a third direction, is etched through first opening 440 to form a plurality of fourth openings 430, fourth openings 430 being in communication with first opening 440.

In some embodiments, as shown in connection with fig. 4g and 4h, the method for forming a three-dimensional semiconductor memory device further includes: the capacitor structure 431 is formed on the surface of the semiconductor layer 406 exposed by the fourth opening 430 and the first opening 440, and the capacitor structure 431 is symmetrically distributed on two sides of the bit line structure 421 along the third direction. Here, the capacitor structure 431 is similar to the capacitor structure shown in fig. 2m, and includes a second electrode, a capacitor dielectric layer, and a first electrode sequentially formed around the end of the semiconductor layer 406, wherein the first electrode is located at the outermost layer. It should be noted that, in the embodiment of the present disclosure, the capacitor structure 431 is electrically connected to the source region, and the bit line structure 421 is electrically connected to the drain region. In some embodiments, the drain region may also be electrically connected to a capacitive structure and the source region may be electrically connected to a bit line structure.

In some embodiments, the step of forming the capacitor structure 431 includes: etching the semiconductor material layer 403 extending in the third direction in the capacitor region to form a plurality of capacitor openings; a capacitor structure 431 is formed in the capacitor opening. Here, the capacitance structure 431 is similar to that shown in fig. 2 n. After forming the capacitor structure 431, the isolation structure 410 is etched in a first direction to form a first opening exposing the capacitor structure 431 and the substrate 201.

It should be noted that, in the embodiment of the present disclosure, the fourth opening 430 and the first opening 440 may be formed first, and then the capacitor structure shown in fig. 2m may be formed, or the capacitor opening and the capacitor structure shown in fig. 2n may be formed first, and then the first opening 440 may be formed, which is not limited in this disclosure. In the following embodiments, the description of the subsequent steps is made taking the formation of the capacitor structure shown in fig. 2m as an example.

In the embodiment of the present disclosure, the capacitor structure 431 is formed in the capacitor region in the memory region, and the second electrode 4311 of the capacitor structure 431 is electrically connected to the first source drain region 407 of the transistor structure in the same semiconductor layer 403, whereby one capacitor structure 431 corresponds to one transistor structure electrically connected thereto, thereby constituting one memory cell. The memory cells are arranged in an array along a first direction and a second direction to jointly form a memory structure of the three-dimensional semiconductor memory device.

In some embodiments, as shown in conjunction with fig. 4h and fig. 4i, the method for forming a three-dimensional semiconductor memory device further includes: the remaining portions of the plurality of first openings 440 and fourth openings 430 are filled with a conductive material to form a common terminal lead-out structure 441 that electrically connects the first electrodes of the plurality of capacitor structures 431 to the substrate 401.

In some embodiments, as shown in fig. 4j, the three-dimensional semiconductor memory device finally formed by the above method, in which the memory structures are symmetrically distributed on both sides of the bit line structure 421 along the third direction, the memory structures include a plurality of memory cells which are formed by transistor structures and capacitor structures and are arranged in an array along the first direction and the second direction; a shallow trench isolation structure 412 is formed between the bottom of the bit line structure 421 and the substrate 401, and the thickness T3 of the shallow trench isolation structure in the first direction is greater than the thickness T4 of the initial oxide layer 402; the common terminal lead-out structure 441 electrically connects the first electrodes 4313 of the plurality of capacitor structures 431 to the substrate 401.

In the formation of the three-dimensional semiconductor memory device, a bit line opening (i.e., the third opening 420) exposing the second source/drain region 409 is formed in the isolation structure 410', a shallow trench isolation structure 412 is formed between the bottom of the bit line opening and the substrate 401, and a thickness T3 of the shallow trench isolation structure in the first direction is greater than a thickness T4 of the initial oxide layer, and then the bit line opening is filled with a conductive material to form a bit line structure 421 extending along the first direction. Compared with the method for forming the bit line opening in the stacked structure, the method forms the bit line structure 421 on the shallow trench isolation structure 412 with a larger thickness, so that the occurrence of electric leakage between the bit line structure 421 and the substrate 401 can be effectively prevented, and the reliability of the three-dimensional semiconductor memory device can be improved.

In some embodiments, a thickness T3 of the shallow trench isolation structure between the bottom of the bit line structure 421 and the substrate 401 in the first direction is greater than a distance between the bottom of the active structure closest to the substrate 401 and the substrate 401. Thus, leakage between the bit line structure 421 and the substrate 401 can be effectively prevented.

Further, by the above-described formation method of the three-dimensional semiconductor memory device, the common terminal lead-out structure 441 electrically connecting the first electrodes 4313 of the plurality of capacitor structures 431 to the substrate 401 is formed, so that a common voltage can be supplied to the common electrodes of the capacitor structures 431 through the substrate 401. Therefore, in the formation process of the back-end interconnection layer, a power supply pad for providing a common voltage for the common electrode of the capacitor structure 431 is not required to be arranged in the bonding interface on the storage array wafer, so that the density of the pads in the bonding interface can be reduced, and parasitic capacitance between the pads can be reduced. In addition, under the condition that the density of the bonding pads in the bonding interface is kept unchanged, the density of the capacitor structure in the memory array can be further increased, and the integration level of the three-dimensional semiconductor memory device is improved.

Based on the technical conception that the forming method of the three-dimensional semiconductor memory device is the same, the embodiment of the disclosure provides a three-dimensional semiconductor memory device. Fig. 2r is a perspective view of a three-dimensional semiconductor memory device provided in an embodiment of the present disclosure. As shown in fig. 2r, the three-dimensional semiconductor memory device includes: a substrate 201; a memory structure located on the substrate 201; the storage structure includes capacitor structures 231 arranged in an array along a first direction and a second direction; the capacitor structures 231 all extend along the third direction; the common terminal lead-out structure 241, the bottom surface of the common terminal lead-out structure 241 is lower than the top surface of the substrate 201, and the common terminal lead-out structure 241 is electrically connected with the first electrode 2313 of the capacitor structure 231 and the substrate 201.

In the embodiment of the disclosure, the first direction is the thickness direction of the substrate 201, i.e., the Z direction, the second direction is the Y direction, the third direction is the X direction, and both the second direction and the third direction are perpendicular to the first direction.

In some embodiments, a three-dimensional semiconductor memory device includes: a substrate 201; isolation structures 210 and common terminal extraction structures 241 located on substrate 201; the isolation structures 210 and the common terminal lead-out structures 241 are arranged along a third direction;

A storage structure; the memory structure includes a transistor structure in isolation structure 210 and a capacitor structure 231 in common terminal lead-out structure 241; the transistor structure and the capacitor structure 231 constitute a memory cell;

the storage units are arranged in an array along a first direction and a second direction;

The transistor structure and the capacitor structure 231 each extend in a third direction;

The common terminal lead-out structure 241 is electrically connected to the first electrode 2313 of the capacitor structure 231 and the substrate 201.

In some embodiments, a transistor structure includes: an active structure extending along the third direction, the active structure including a first source drain region 207, a channel region 208, and a second source drain region 209 arranged along the third direction. The second electrode 2311 of the capacitor structure 231 is electrically connected to the first source drain region 207.

In some embodiments, the three-dimensional semiconductor memory device further includes: a word line structure 213 extending in the first direction and located on opposite sides of the channel region 208 in the second direction; shallow trench isolation structure 212, which is located between the bottom of word line structure 213 and substrate 201, has a thickness T1 in the first direction that is greater than a thickness T2 of initial oxide layer 202; the bit line structures 220 extend along the second direction, are alternately arranged with the dielectric layer 206 along the first direction, and the bit line structures 220 are electrically connected with the second source drain regions 209 at two sides.

In the embodiment of the present disclosure, the word line structure 213 is used as a gate of the transistor structure, and the transistor structure and the active structure together form the transistor structure, and the transistor structures using the same word line structure 213 as the gate are arranged along the first direction. In the third direction, the first source drain region 207 of one transistor structure is electrically connected to the second electrode 2311 of one capacitor structure 231, thereby constituting one memory cell. The memory cells are arranged in an array along a first direction and a second direction to jointly form a memory structure of the three-dimensional semiconductor memory device.

In a specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is 3 times the thickness T2 of the initial oxide layer 202. In another specific example, the thickness T1 of the shallow trench isolation structure 212 in the first direction is 6 times the thickness T2 of the initial oxide layer 202.

In some embodiments, the capacitor structures 231 are symmetrically distributed along the third direction on both sides of the bit line structure 220.

In some embodiments, the three-dimensional semiconductor memory device further includes: a metal silicide layer 242 and an adhesive layer 243 between the common terminal lead-out structure 241 and the substrate 201, wherein the adhesive layer 243 is between the common terminal lead-out structure 241 and the metal silicide layer 242.

In an embodiment of the present disclosure, the material of the common terminal extraction structure 241 includes a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.); the material of the metal silicide layer 242 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesive layer 243 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The metal silicide layer 242 and the adhesive layer 243 may effectively reduce the contact resistance between the common terminal lead-out structure 241 and the substrate 201.

In the embodiment of the present disclosure, the three-dimensional semiconductor memory device includes the first electrodes 2313 of the plurality of capacitor structures 231 arranged in the array in the first direction and the second direction are electrically connected to the common terminal lead-out structure 241 of the substrate 201 at the same time, so that the common electrode (i.e., the first electrode 2313) of the capacitor structure 231 can be connected to the common voltage through the substrate 201, and the provision of the power supply pad for supplying the common voltage to the common electrode of the capacitor structure can be omitted during the formation of the back-end interconnection layer, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads. In addition, the density of the capacitor structure in the memory array can be further increased under the condition that the density of the bonding pads in the bonding interface is kept unchanged, so that the integration level of the three-dimensional semiconductor memory device is improved.

In the three-dimensional semiconductor memory device shown in fig. 2r, a shallow trench isolation structure 212 is formed between the bottom of the word line structure 213 and the substrate 201, and the thickness T1 of the shallow trench isolation structure in the first direction is greater than the thickness T2 of the initial oxide layer 202, so that leakage between the word line structure 213 and the substrate 201 can be prevented, and the reliability of the three-dimensional semiconductor memory device can be effectively improved.

In some embodiments, the thickness T1 of the shallow trench isolation structure between the bottom of the word line structure 213 and the substrate 201 in the first direction is greater than the maximum distance between the memory structure and the substrate 201. Here, the maximum distance between the memory structure and the substrate 201 may be the distance between the bottom of the active structure closest to the substrate 201 and the substrate 201. Thus, leakage between the word line structure 213 and the substrate 201 can be effectively prevented.

Fig. 3 is a perspective view of another three-dimensional semiconductor memory device provided in an embodiment of the present disclosure. The three-dimensional semiconductor memory device differs from the three-dimensional semiconductor memory device shown in fig. 2q in that the capacitance structure 331 of the semiconductor memory device is distributed on the same side of the bit line structure 320.

Fig. 4j is a perspective view of a three-dimensional semiconductor memory device according to another embodiment of the present disclosure. As shown in fig. 4j, the three-dimensional semiconductor memory device includes: a substrate 401; a memory structure located on the substrate 401; the storage structure comprises a plurality of capacitor structures 431 arranged in an array along a first direction and a second direction; the capacitor structures 431 all extend along the third direction and include a second electrode 4311, a capacitor dielectric layer 4312 and a first electrode 4313, which sequentially surround the end of the semiconductor layer; the bottom surface of the common terminal lead-out structure 441 is lower than the top surface of the substrate 401, and the common terminal lead-out structure 441 is electrically connected to the first electrode 4313 of the capacitor structure 431 and the substrate 401.

In some embodiments, the storage structure further comprises: an active structure extending along the third direction, the active structure including a first source drain region 407, a channel region 408, and a second source drain region 409 arranged along the third direction. The second electrode 4311 of the capacitor structure 431 is electrically connected to the first source drain region 407.

In some embodiments, the three-dimensional semiconductor memory device further includes: bit line structure 421 extending in the first direction and electrically connected to second source drain region 409; shallow trench isolation structure 412, which is located between the bottom of bit line structure 421 and substrate 401, has a thickness T3 in the first direction that is greater than the thickness T4 of initial oxide layer 402; the word line structures 413 extending in the second direction, the word line structures 413 being arranged in the first direction and located on opposite sides of the channel region 408 in the first direction.

In the embodiment of the present disclosure, the word line structure 413 is used as a gate of the transistor structure, and the transistor structure and the active structure together form the transistor structure, and the transistor structures using the same word line structure 413 as the gate are arranged along the second direction. In the third direction, the first source drain region 407 of one transistor structure is electrically connected to the second electrode 4311 of one capacitor structure 431, thereby constituting one memory cell. The memory cells are arranged in an array along a first direction and a second direction to jointly form a memory structure of the three-dimensional semiconductor memory device.

In a specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 3 times the thickness T4 of the initial oxide layer 402. In another specific example, the thickness T3 of the shallow trench isolation structure 412 in the first direction is 6 times the thickness T4 of the initial oxide layer 402.

In some embodiments, the thickness T3 of the shallow trench isolation structure 412 in the first direction is greater than the distance between the bottom of the active structure closest to the substrate 401 and the substrate 401.

In some embodiments, the three-dimensional semiconductor memory device further includes: a gate dielectric layer 414 is located between the word line structure 413 and the channel region 408.

In some embodiments, the capacitor structures 431 are symmetrically distributed along the third direction on both sides of the bit line structure 421.

In some embodiments, the three-dimensional semiconductor memory device further includes: a metal silicide layer 442 and an adhesion layer 443 between the common terminal lead-out structure 441 and the substrate 401, wherein the adhesion layer 443 is between the common terminal lead-out structure 441 and the metal silicide layer 442.

In an embodiment of the present disclosure, the material of the common terminal extraction structure 441 includes a doped semiconductor material (e.g., doped polysilicon, doped germanium, etc.); the material of the metal silicide layer 442 may be tungsten silicide, cobalt silicide, titanium silicide, etc.; the material of the adhesion layer 443 may be a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The metal silicide layer 442 and the adhesive layer 443 can effectively reduce the contact resistance between the common terminal lead-out structure 441 and the substrate 401.

In the embodiment of the present disclosure, the three-dimensional semiconductor memory device includes the first electrodes 4313 of the plurality of capacitor structures 431 arranged in the first direction and the second direction in an array manner are electrically connected to the common terminal lead-out structure 441 of the substrate 401 at the same time, so that the common electrode of the capacitor structures 431 can be connected to a common voltage through the substrate 401, and the setting of a power supply pad for supplying the common voltage to the common electrode of the capacitor structures can be omitted during the formation of the back-end interconnection layer, thereby reducing the density of the pads in the bonding interface and reducing the parasitic capacitance between the pads.

In the three-dimensional semiconductor memory device shown in fig. 4j, a shallow trench isolation structure 412 is formed between the bottom of the bit line structure 421 and the substrate 401, and the thickness T3 of the shallow trench isolation structure in the first direction is greater than the thickness T4 of the initial oxide layer 402, so that leakage between the bit line structure 421 and the substrate 401 can be prevented, and the reliability of the three-dimensional semiconductor memory device can be effectively improved.

In some embodiments, the three-dimensional semiconductor memory device is a three-dimensional dynamic random access memory (Dynamic Random Access Memory, DRAM).

In some embodiments, the common voltage may be half the supply voltage, i.e., V _CC/2.

In the embodiment of the disclosure, since the three-dimensional semiconductor memory device does not need to be grounded by using the substrate, the common electrode of the capacitor structure arranged in an array can be electrically connected to the substrate by forming the common terminal lead-out structure, and the common voltage can be provided to the capacitor structure through the substrate. Therefore, in the formation process of the back-end interconnection layer, the arrangement of the power supply pads for providing the common voltage for the common electrode of the capacitor structure can be omitted, so that the density of the pads in the bonding interface is reduced, and the parasitic capacitance between the pads is reduced. In addition, under the condition that the density of the bonding pads in the bonding interface is kept unchanged, the density of the capacitor structure in the memory array can be further increased, and the integration level of the three-dimensional semiconductor memory device is improved.

In the embodiment of the disclosure, the three-dimensional semiconductor memory device has a word line structure or a bit line structure perpendicular to a substrate, and a shallow trench isolation structure is formed between the word line structure and the substrate or between the bit line structure and the substrate by forming a word line opening or a bit line opening in the isolation structure, wherein the thickness of the shallow trench isolation structure is greater than that of an initial oxide layer between the substrate and a stacked structure. Therefore, compared with the method for forming the word line opening or the bit line opening in the stacked structure, the method for forming the three-dimensional semiconductor memory device in the embodiment of the disclosure can effectively avoid electric leakage between the word line structure or the bit line structure and the substrate, and remarkably improve the reliability of the three-dimensional semiconductor memory device.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain a new device embodiment.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of forming a three-dimensional semiconductor memory device, comprising:

2. The method of forming a three-dimensional semiconductor memory device according to claim 1, wherein before the capacitor region is formed with the capacitor structures arranged in the first and second direction arrays, further comprising:

Forming active structures arranged in an array along the first direction and the second direction in the transistor area in the storage area; the active structure extends along a third direction and comprises a first source drain region, a channel region and a second source drain region;

The second electrode of the capacitor structure is electrically connected with the first source drain region in the active structure.

3. The method of forming a three-dimensional semiconductor memory device according to claim 2, further comprising:

4. The method of forming a three-dimensional semiconductor memory device according to claim 2, further comprising:

5. The method of forming a three-dimensional semiconductor memory device according to claim 3 or 4, wherein the capacitor structures are symmetrically distributed on both sides of the bit line structure along the third direction; or the capacitance structure is distributed on one side of the capacitance structure.

6. The method of forming a three-dimensional semiconductor memory device according to claim 1, wherein forming a common terminal lead-out structure in the first opening that electrically connects the first electrode of the capacitor structure to the substrate, comprises:

Depositing a conductive material on the adhesive layer to fill the first opening; the conductive material comprises polysilicon.

7. The method of forming a three-dimensional semiconductor memory device according to claim 1, wherein the forming an isolation structure in the memory stack structure comprises:

8. The method of forming a three-dimensional semiconductor memory device according to claim 2, wherein the memory stack structure includes dielectric layers and semiconductor layers alternately stacked in the first direction; the forming of the capacitor structure arranged in the array along the first direction and the second direction in the capacitor region includes:

9. The method of forming a three-dimensional semiconductor memory device according to claim 8, wherein forming a common terminal lead-out structure in the first opening that electrically connects the first electrode of the capacitor structure to the substrate, comprises:

10. A three-dimensional semiconductor memory device, comprising:

A substrate;

a memory structure located on the substrate;

11. The three-dimensional semiconductor memory device according to claim 10, wherein the memory structure further comprises:

12. The three-dimensional semiconductor memory device according to claim 11, further comprising:

And the bit line structure is arranged along the first direction, extends along the second direction and is connected with the second source drain region.

13. The three-dimensional semiconductor memory device according to claim 11, further comprising:

And the word line structure is arranged along the first direction, extends along the second direction and is positioned at two opposite sides of the channel region along the first direction.

14. The three-dimensional semiconductor memory device according to claim 12 or 13, wherein the capacitor structures are symmetrically distributed on both sides of the bit line structure along the third direction; or the capacitor structure is located on one side of the bit line structure.

15. The three-dimensional semiconductor memory device according to claim 11, further comprising: