CN118042698B

CN118042698B - Single-period active energy-changing digital low-level system of synchrotron

Info

Publication number: CN118042698B
Application number: CN202311824481.3A
Authority: CN
Inventors: 丛岩; 许哲; 李世龙; 张瑞锋; 韩小东; 周睿怀
Original assignee: Institute of Modern Physics of CAS
Current assignee: Institute of Modern Physics of CAS
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-07-23
Anticipated expiration: 2043-12-27
Also published as: CN118042698A

Abstract

The application discloses a single-period active energy-changing digital low-level system of a synchrotron, which comprises the following steps: the case analysis module analyzes the optical case signal to obtain a target waveform identifier and a read trigger signal; the delay-free read-write control module reads target electric field amplitude waveform data and target frequency waveform data from the data storage module according to the read trigger signal and the target waveform identifier; the analog-to-digital conversion module collects the cavity electric field sampling signal and converts the cavity electric field sampling signal into a digital signal; the data processing module processes the digital signal according to the electric field amplitude set value extracted from the target electric field amplitude waveform data and the frequency control word extracted from the target frequency waveform data to obtain a target excitation signal; the digital-to-analog conversion module converts the target excitation signal into an analog signal and sends the analog signal to the cavity; the particle extraction module extracts particles subjected to energy conversion treatment from the cavity according to a preset quantity; and after the particles are led out, the judging module determines the quantity of the residual particles in the cavity.

Description

Single-period active energy-changing digital low-level system of synchrotron

Technical Field

The application relates to the technical field of low-level control of particle accelerators, in particular to a single-period active energy-changing digital low-level system of a synchronous accelerator.

Background

The current international most advanced radiotherapy technology is proton heavy ion treatment technology, and when the technology is used for carrying out ray 'beating' on solid tumors, strong irradiation can be carried out on tumor focuses, and normal tissue irradiation is avoided, so that the maximization of curative effect is realized.

The equivalent bragg peak of the heavy ion beam in water is related to the beam energy, different beam energies corresponding to different bragg peak depths. Thus, the depth of the Bragg peak can be varied by controlling the energy of the beam during treatment of the patient, thereby performing accurate layer-by-layer and point-by-point scanning of solid tumors. The heavy ion beam may be provided using a synchrotron. The synchrotron operates in a pulsed mode, each pulse providing a beam of energy, typically requiring about 30 bragg peaks superimposed at the target for a typical tumor lesion, i.e. at least the synchrotron is required to provide about 30 pulsed beams of different energies. For spot scanning or uniform scanning of 2dls and 3dls, the number of particles required per energy layer is typically 0.1e ⁹～1e⁹, whereas the synchrotron can provide 1e ¹⁰ particles per pulse, so that only 1-10% of the particles are transported to the terminal, and the rest of the particles are either totally lost in the synchrotron or sent to the beam dump. This not only results in serious beam waste, but also prolongs the treatment time of the patient, and at the same time, the radiation caused by the beam loss may affect the stable operation and the service life of the synchrotron device, even causes activation of the device, and increases the maintenance difficulty of the device and the treatment cost.

Therefore, how to reduce beam waste and improve treatment efficiency and simultaneously improve the service life of the synchrotron becomes a technical problem to be solved in the field.

Disclosure of Invention

In view of this, the application provides a single-period active energy-changing digital low level system of a synchrotron, which is characterized in that an instance analysis module receives an optical instance signal and realizes the automatic switching of waveforms during single-period active energy-changing through the optical instance signal, the instance analysis module and a non-delay read-write control module; in addition, the method also ensures that the target electric field amplitude waveform data and the target frequency waveform data can be read from the data storage module without delay when the waveforms are transformed, compared with the scheme that each pulse of the synchronous accelerator only extracts the beam current of one energy layer in the prior art, and the corresponding target electric field amplitude waveform data and the corresponding target frequency waveform data are issued by the upper computer each time, the waiting time can be greatly shortened, and the treatment efficiency is greatly improved; through judging the relation between the quantity of the residual particles in the cavity and the preset quantity after the particles are led out, the quantity of the particles corresponding to each Bragg peak can be ensured to be enough, meanwhile, the full use of the particles in a single period can be realized, the use efficiency of the particles is improved, and meanwhile, the service life of the synchrotron is prolonged.

According to one aspect of the application, a single-period active energy-changing digital low level system of a synchrotron is provided, which comprises an instance analysis module, a non-delay read-write control module, a data storage module, an analog-to-digital conversion module, a data processing module, a digital-to-analog conversion module, a particle extraction module and a judgment module:

The case analysis module is used for analyzing the optical case signal to obtain a target waveform identifier and a read trigger signal when the optical case signal is received, and sending the target waveform identifier and the read trigger signal to the non-delay read-write control module;

the delay-free read-write control module is used for reading target electric field amplitude waveform data and target frequency waveform data corresponding to the target waveform identifier from a plurality of groups of preset waveform data corresponding to the data storage module without delay after receiving the read trigger signal according to the target waveform identifier;

The data storage module is used for storing a plurality of groups of preset waveform data, each group of preset waveform data comprises preset electric field amplitude waveform data and preset frequency waveform data, and the plurality of groups of preset waveform data comprises preset waveform data required by at least one treatment;

The analog-to-digital conversion module is used for collecting the electric field sampling signal of the cavity of the synchronous accelerator according to a set sampling clock signal and converting the electric field sampling signal into a digital signal;

The data processing module is used for processing the digital signal according to the electric field amplitude set value extracted from the target electric field amplitude waveform data and the frequency control word extracted from the target frequency waveform data to obtain a target excitation signal;

The digital-to-analog conversion module is used for converting the target excitation signal into an analog signal and sending the analog signal to a cavity of the synchronous accelerator so that the cavity can perform energy conversion processing on particles in the cavity according to the analog signal corresponding to the target excitation signal;

the particle extraction module is used for extracting particles subjected to energy conversion treatment from the cavity according to a preset quantity;

The judging module is used for determining the quantity of the residual particles in the cavity after the particles are led out, comparing the quantity of the residual particles with the preset quantity, and interrupting the acquisition operation of the analog-to-digital conversion module when the quantity of the residual particles is smaller than the preset quantity until the quantity of the particles in the cavity is larger than the preset quantity.

Optionally, the delay-free read-write control module comprises a signal receiving unit, a reset unit, an address determining unit and a data reading unit;

the signal receiving unit is used for receiving the target waveform identification and the reading trigger signal;

the reset unit is used for clearing historical read information based on the read trigger signal;

The address determining unit is configured to determine, after the cleaning process is finished, a first read address and a second read address in a first storage module and a third read address and a fourth read address in a second storage module based on the target waveform identifier, where the data storage module includes the first storage module and the second storage module, the first storage module is configured to store preset electric field amplitude waveform data, and the second storage module is configured to store preset frequency waveform data;

The data reading unit is configured to read first sub-data of an electric field amplitude waveform corresponding to the first reading address from a random access memory of the first memory module, and read second sub-data of an electric field amplitude waveform corresponding to the second reading address from a double-rate memory of the first memory module; and simultaneously reading the first sub-data of the frequency waveform corresponding to the third reading address from the random access memory of the second memory module, and reading the second sub-data of the frequency waveform corresponding to the fourth reading address from the double-rate memory of the second memory module, wherein the target electric field amplitude waveform data comprises the first sub-data of the electric field amplitude waveform and the second sub-data of the electric field amplitude waveform, and the target frequency waveform data comprises the first sub-data of the frequency waveform and the second sub-data of the frequency waveform.

Optionally, the non-delay read-write control module further includes a data writing unit, and the non-delay read-write control module is further configured to:

the signal receiving unit is also used for receiving a plurality of groups of preset waveform data issued by the upper computer;

the address determining unit is further configured to determine a first storage address and a second storage address corresponding to each set of preset electric field amplitude waveform data in the first storage module, and determine a third storage address and a fourth storage address corresponding to each set of preset frequency waveform data in the second storage module;

The data writing unit is configured to split each group of preset electric field amplitude waveform data to obtain first data to be written and second data to be written, write the first data to be written into a random access memory of the first memory module according to the first memory address, and write the second data to be written into a double-rate memory of the first memory module according to the second memory address; splitting each group of preset frequency waveform data to obtain third data to be written and fourth data to be written, writing the third data to be written into a random access memory of the second memory module according to the third memory address, and writing the fourth data to be written into a double-rate memory of the second memory module according to the fourth memory address;

The reset unit is further used for performing reset operation by using reset logic after the writing of each group of waveform data of the preset electric field amplitude is completed; and after the writing of each group of preset frequency waveform data is completed, resetting by using a resetting logic.

Optionally, the first data to be written and the second data to be written are determined based on a read delay time of a double-rate memory of the first memory module, and the third data to be written and the fourth data to be written are determined based on a read delay time of a double-rate memory of the second memory module.

Optionally, the storage space of the random access memory in the first storage module and the storage space of the random access memory in the second storage module are divided into a plurality of groups, and the number of the groups is the same as the number of the groups of the preset waveform data;

The first read address and the third read address comprise addresses corresponding to target group numbers in the random access memory, and the second read address and the fourth read address comprise target initial read addresses and target read data lengths in the double-rate memory;

the first storage address and the third storage address comprise addresses corresponding to target group numbers in the random access memory, and the second storage address and the fourth storage address comprise target initial storage addresses and target storage data lengths in the double-rate memory.

Optionally, the random access memory is a RAM memory, and the double rate memory is a DDR memory.

Optionally, the data processing module adopts an FPGA chip or a DSP chip, and the FPGA chip or the DSP chip mounts two DDR memories.

Optionally, the data processing module comprises a quadrature demodulation unit and a digital signal processing unit;

The quadrature demodulation unit is used for converting the digital signal into two paths of zero-frequency quadrature signals according to frequency control words extracted from the target frequency waveform data read by the delay-free read-write control module;

The digital signal processing unit is used for respectively carrying out logic operation processing on the two paths of zero frequency orthogonal signals by adopting a digital PI algorithm according to the electric field amplitude set value extracted from the target electric field amplitude waveform data read by the non-delay read-write control module and the frequency control word to obtain target excitation signals.

Optionally, the system further comprises a frequency interpolation module and a voltage interpolation module;

The frequency interpolation module is used for performing linear interpolation processing on the target frequency waveform data read by the delay-free read-write control module to obtain processed target frequency waveform data;

The voltage interpolation module is used for performing linear interpolation processing on the target electric field amplitude waveform data read by the delay-free read-write control module to obtain processed target electric field amplitude waveform data.

Optionally, the system further comprises a display module;

The display module is used for displaying the plurality of groups of preset waveform data.

By means of the technical scheme, the single-period active energy-changing digital low-level system of the synchronous accelerator is characterized in that an instance analysis module receives an optical instance signal, and the automatic switching of waveforms during single-period active energy changing is realized through the optical instance signal, the instance analysis module and a non-delay read-write control module; in addition, the method also ensures that the target electric field amplitude waveform data and the target frequency waveform data can be read from the data storage module without delay when the waveforms are transformed, compared with the scheme that each pulse of the synchronous accelerator only extracts the beam current of one energy layer in the prior art, and the corresponding target electric field amplitude waveform data and the corresponding target frequency waveform data are issued by the upper computer each time, the waiting time can be greatly shortened, and the treatment efficiency is greatly improved; through judging the relation between the quantity of the residual particles in the cavity and the preset quantity after the particles are led out, the quantity of the particles corresponding to each Bragg peak can be ensured to be enough, meanwhile, the full use of the particles in a single period can be realized, the use efficiency of the particles is improved, and meanwhile, the service life of the synchrotron is prolonged.

The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 shows a schematic diagram of a single-cycle active energy-converting digital low-level system of a synchrotron according to an embodiment of the present application;

FIG. 2 shows a schematic diagram of a data interrupt at waveform switching;

FIG. 3 is a schematic diagram of a memory and read logic of a double-rate memory according to an embodiment of the present application;

Fig. 4 shows a schematic diagram of a hardware architecture according to an embodiment of the present application;

FIG. 5 shows a schematic diagram of a target electric field amplitude waveform and a target frequency waveform of a single-period energy-variable high-frequency cavity according to an embodiment of the present application;

FIG. 6 shows a schematic diagram of a partial amplification of a waveform of a target electric field amplitude of a single-period energy-variable high-frequency cavity according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of another single-cycle active energy-conversion digital low-level system of a synchrotron according to an embodiment of the present application.

Detailed Description

The application will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.

In this embodiment, a single-period active energy-conversion digital low-level system of a synchrotron is provided, as shown in fig. 1, where the system includes an instance analysis module, a non-delay read-write control module, a data storage module, an analog-to-digital conversion module, a data processing module, a digital-to-analog conversion module, a particle extraction module and a judgment module;

The single-period active energy-changing digital low-level system of the synchrotron provided by the embodiment of the application can specifically comprise an instance analysis module, a non-delay read-write control module, a data storage module, an analog-to-digital conversion module, a data processing module, a digital-to-analog conversion module, a particle extraction module and a judgment module. The modules can enable the high-frequency system of the synchrotron to realize the transformation of the amplitude and the phase of the electric field for a plurality of times in one working period, so that the energy of the beam is actively transformed for a plurality of times, the loss of particles is reduced, the service life of the synchrotron is prolonged, and the treatment efficiency is improved.

Firstly, when a patient needs to be treated, an optical case signal can be sent out through an application terminal, and after the optical case signal is received, the case analysis module can analyze the optical case signal to obtain a target waveform identification and a reading trigger signal. The optical case signal generally includes two cases, one is a case of determining a required waveform, that is, notifying a digital low level system of a target waveform identifier corresponding to a waveform required to be output, specifically, when the optical case signal is a different waveform number, the target waveform identifier may be a target waveform number; the other is the "read trigger" case, informing the digital low system to start outputting a completely new waveform. After the target waveform identification and the read trigger signal are analyzed, the target waveform identification and the read trigger signal can be further sent to the delay-free read-write control module.

After receiving the target waveform identifier and the read trigger signal, the delay-free read-write control module can know that a brand new waveform is about to be output under the notification of the read trigger signal, and reads the waveform indicated by the target waveform identifier from a plurality of groups of preset waveform data stored in the preset storage module without delay, wherein the target electric field amplitude waveform data and the target frequency waveform data are needed simultaneously in order to control the electric field in the cavity of the synchronous accelerator to control the beam energy. The data storage module may store a plurality of sets of preset waveform data in advance, and because when the cavity electric field of the synchrotron is controlled, the electric field amplitude and the frequency set value are required at the same time, each set of preset waveform data may include preset electric field amplitude waveform data and preset frequency waveform data, where the preset electric field amplitude waveform data is used to indicate the electric field amplitude required by the current beam energy variation, that is, the set value of the cavity electric field amplitude, and the preset frequency waveform data is used to indicate the output signal frequency of the digital oscillator, that is, the frequency set value of the cavity electric field. Each set of preset waveform data corresponds to a waveform identifier, that is, the waveform identifier corresponding to the preset electric field amplitude waveform data and the waveform identifier corresponding to the preset frequency waveform data contained in each set of preset waveform data are the same. It should be noted that, in order to ensure smooth treatment without delay for a patient, the data storage module includes a plurality of sets of preset waveform data, at least including preset waveform data corresponding to about 30 bragg peaks required for treatment of the patient, that is, about 30 sets of preset waveform data. In order to cope with complex medical situations, the data storage module of the digital low-level system can comprise 1024 groups of preset waveform data, and further can comprise waveform data corresponding to Bragg peaks required by most different patients. In the embodiment of the application, a plurality of groups of preset waveform data are stored in the data storage module in advance, in addition, the target electric field amplitude waveform data and the target frequency waveform data can be read from the data storage module without delay when the waveforms are transformed, and compared with the scheme that each pulse of the synchronous accelerator only extracts the beam current of one energy layer in the prior art, and the corresponding target electric field amplitude waveform data and the corresponding target frequency waveform data are issued by the upper computer every time, the waiting time can be greatly shortened, and the treatment efficiency is greatly improved.

The analog-to-digital conversion module can collect an electric field sampling signal in the cavity of the synchronous accelerator according to a set sampling clock signal, and then can convert the electric field sampling signal into a digital signal. In the operation of the high-frequency system, the sampling clock signal collects an electric field signal from the cavity at a certain sampling rate, and the electric field signal is sent out by the detection equipment connected in the cavity and contains the voltage information in the current cavity.

The data processing module can then perform a series of processing on the digital signal from the analog-to-digital conversion module according to the electric field amplitude set value extracted from the target electric field amplitude waveform data and the frequency set value, i.e., the frequency control word, extracted from the target frequency waveform data, to finally obtain the target excitation signal. The target excitation signal can realize the function of stably controlling the amplitude and the phase of the electric field of the cavity of the synchronous accelerator. The digital-to-analog conversion module can convert the target excitation signal into an analog signal and send the analog signal to the cavity of the synchrotron, so that the subsequent cavity can perform energy conversion processing on particles in the cavity according to the analog signal corresponding to the target excitation signal.

After energy conversion treatment, the particle extraction module can extract a preset number of particles from the cavity of the synchrotron, and the particles can be used for treating the focus of a patient. After the particles are led out, the judging module can determine the number of the residual particles in the cavity of the synchrotron, determine the size relation between the number of the residual particles and the preset number, if the number of the residual particles is larger than or equal to the preset number through judgment, the application terminal can send out the optical case signal again at the moment, the optical case signal can comprise a new target waveform identifier and a reading trigger signal, the new target waveform identifier is used for indicating the waveform required by the next irradiation of the patient, and the step of analyzing the optical case signal by the case analyzing module is returned. If the number of the residual particles is less than the preset number, the acquisition operation of the analog-to-digital conversion module can be interrupted at the moment, the synchrotron supplies particles again through a new pulse, so that the number of the particles in the cavity is greater than the preset number, the acquisition operation of the analog-to-digital conversion module is restored, and energy conversion processing is continued until the treatment of the patient is finished. According to the embodiment of the application, through judging the relation between the number of the residual particles in the cavity and the preset number after the particles are led out, the sufficient number of the particles corresponding to each Bragg peak can be ensured, meanwhile, the full use of the particles in a single period can be realized, the use efficiency of the particles is improved, and meanwhile, the service life of the synchrotron is prolonged.

By applying the technical scheme of the embodiment, the case analysis module receives the optical case signal, and the automatic switching of the waveform during single-period active energy conversion is realized through the optical case signal, the case analysis module and the delay-free read-write control module; in addition, the method also ensures that the target electric field amplitude waveform data and the target frequency waveform data can be read from the data storage module without delay when the waveforms are transformed, compared with the scheme that each pulse of the synchronous accelerator only extracts the beam current of one energy layer in the prior art, and the corresponding target electric field amplitude waveform data and the corresponding target frequency waveform data are issued by the upper computer each time, the waiting time can be greatly shortened, and the treatment efficiency is greatly improved; through judging the relation between the quantity of the residual particles in the cavity and the preset quantity after the particles are led out, the quantity of the particles corresponding to each Bragg peak can be ensured to be enough, meanwhile, the full use of the particles in a single period can be realized, the use efficiency of the particles is improved, and meanwhile, the service life of the synchrotron is prolonged.

In the embodiment of the present application, optionally, the delay-free read-write control module includes a signal receiving unit, a reset unit, an address determining unit, and a data reading unit; the signal receiving unit is used for receiving the target waveform identification and the reading trigger signal; the reset unit is used for clearing historical read information based on the read trigger signal; the address determining unit is configured to determine, after the cleaning process is finished, a first read address and a second read address in a first storage module and a third read address and a fourth read address in a second storage module based on the target waveform identifier, where the data storage module includes the first storage module and the second storage module, the first storage module is configured to store preset electric field amplitude waveform data, and the second storage module is configured to store preset frequency waveform data; the data reading unit is configured to read first sub-data of an electric field amplitude waveform corresponding to the first reading address from a random access memory of the first memory module, and read second sub-data of an electric field amplitude waveform corresponding to the second reading address from a double-rate memory of the first memory module; and simultaneously reading the first sub-data of the frequency waveform corresponding to the third reading address from the random access memory of the second memory module, and reading the second sub-data of the frequency waveform corresponding to the fourth reading address from the double-rate memory of the second memory module, wherein the target electric field amplitude waveform data comprises the first sub-data of the electric field amplitude waveform and the second sub-data of the electric field amplitude waveform, and the target frequency waveform data comprises the first sub-data of the frequency waveform and the second sub-data of the frequency waveform.

In this embodiment, the delay-free read-write control module may include a signal receiving unit, a reset unit, an address determining unit, and a data reading unit. The signal receiving unit may be configured to receive the target waveform identifier and the read trigger signal sent by the case analysis module, and then the reset unit may perform a clearing process on the history read information according to the read trigger signal. Then, the address determining unit may determine, according to the target waveform identifier, the first read address and the second read address from the first storage module, and determine the third read address and the fourth read address from the second storage module, after the clearing process is finished. The data storage module consists of a first storage module and a second storage module, wherein the preset electric field amplitude waveform data in each set of preset waveform data can be stored in the first storage module, and the preset frequency waveform data can be stored in the second storage module, so that the two sets of waveform data can be conveniently read simultaneously. After the first read address and the second read address in the first memory module and the third read address and the fourth read address in the second memory module are determined, waveform data can be read from the first memory module and the second memory module simultaneously by using the four read addresses. Specifically, the data reading unit may read a first portion of the target electric field amplitude waveform data, i.e., the first sub-data of the electric field amplitude waveform, from the random access memory of the first memory module using the first read address, and may simultaneously read a second portion of the target electric field amplitude waveform data, i.e., the second sub-data of the electric field amplitude waveform, from the double rate memory of the first memory module using the second read address. And the data reading unit may further read a first portion of the target frequency waveform data, i.e., the first sub-data of the frequency waveform, from the random access memory of the second memory module using the third read address, and may simultaneously read a second portion of the target frequency waveform data, i.e., the second sub-data of the frequency waveform, from the double-rate memory of the second memory module using the fourth read address.

It should be noted that the first read address is used to indicate an address for reading data in the random access memory of the first memory module, and the second read address is used to indicate an address for reading data in the double-rate memory of the first memory module; the third read address is used for indicating an address for reading data in the random access memory of the second memory module, and the fourth read address is used for indicating an address for reading data in the double rate memory of the second memory module. In the prior art, the operation mode of the synchrotron device is to provide energy (single cycle and single energy) in one working cycle, and the upper computer issues new waveform data to the digital low-level system again when the energy is replaced, under the background, the digital low-level system of the synchrotron only needs to store one group of electric field amplitude waveform data and frequency waveform data, the storage amount of the data is small, and the on-chip memory of a programmable gate array (FPGA) can be used for realizing the storage function of the data. The single-period active energy-changing digital low-level system needs to store a plurality of groups of preset waveform data, namely a plurality of groups of electric field amplitude waveform data and frequency waveform data, so that large data volume cannot be stored in an on-chip memory of the FPGA, and the data can be stored in a large-capacity memory such as a DDR (double rate memory). However, DDR has an inherent feature in that there is a delay in issuing a read data enable to the first data output, which is referred to as the read data latency (RL). In this way, the data will be interrupted when the two sets of waveforms are switched, as shown in fig. 2, the high-frequency system of the synchrotron will be interrupted when the waveforms are switched, so that the requirement of seamless connection of the waveforms required by the system cannot be met, and the loss of beam current will be caused. Thus, the embodiment of the application adds a delay-free DDR read design, specifically, two parts are arranged in each memory module, one is a Random Access Memory (RAM) and the other is a double rate memory (DDR), wherein one part of each set of waveform data is stored in the random access memory, and the other part of each set of waveform data is stored in the double rate memory. When the data is read, the random access memory is used as a front-stage buffer, a first part of the waveform data is read from the random access memory, and a second part of the waveform data is read from the double-rate memory, so that the whole waveform data is read without delay.

In the embodiment of the present application, optionally, the non-delay read-write control module further includes a data writing unit, where the non-delay read-write control module is further configured to: the signal receiving unit is also used for receiving a plurality of groups of preset waveform data issued by the upper computer; the address determining unit is further configured to determine a first storage address and a second storage address corresponding to each set of preset electric field amplitude waveform data in the first storage module, and determine a third storage address and a fourth storage address corresponding to each set of preset frequency waveform data in the second storage module; the data writing unit is configured to split each group of preset electric field amplitude waveform data to obtain first data to be written and second data to be written, write the first data to be written into a random access memory of the first memory module according to the first memory address, and write the second data to be written into a double-rate memory of the first memory module according to the second memory address; splitting each group of preset frequency waveform data to obtain third data to be written and fourth data to be written, writing the third data to be written into a random access memory of the second memory module according to the third memory address, and writing the fourth data to be written into a double-rate memory of the second memory module according to the fourth memory address; the reset unit is further used for performing reset operation by using reset logic after the writing of each group of waveform data of the preset electric field amplitude is completed; and after the writing of each group of preset frequency waveform data is completed, resetting by using a resetting logic.

In this embodiment, the delay-free read-write control module may further include a data writing unit. The signal receiving unit in the delay-free read-write control module can also be used for receiving a plurality of groups of preset waveform data issued by the upper computer, wherein each group of preset waveform data comprises preset electric field amplitude waveform data and preset frequency waveform data. Then, the address determining unit in the delay-free read-write control module may determine a first storage address and a second storage address corresponding to each set of preset electric field amplitude waveform data from the first storage module, where the first storage address is used to indicate a storage address in the random access memory in the first storage module, and the second storage address is used to indicate a storage address in the double rate memory in the first storage module. Meanwhile, the address determining unit may further determine a third memory address and a fourth memory address corresponding to each set of preset frequency waveform data from the second memory module, the third memory address being used for indicating a memory address in the random access memory in the second memory module, and the fourth memory address being used for indicating a memory address in the double rate memory in the second memory module. Then, the data writing unit splits each group of waveform data with preset electric field amplitude to obtain first data to be written and second data to be written, the first data to be written is written into a random access memory of the first memory module according to a first memory address, and the second data to be written is written into a double-rate memory of the first memory module according to a second memory address; meanwhile, the data writing unit can split each group of preset frequency waveform data to obtain third data to be written and fourth data to be written, the third data to be written is written into the random access memory of the second memory module according to the third memory address, and the fourth data to be written is written into the double-rate memory of the second memory module according to the fourth memory address. After the writing of each group of preset electric field amplitude waveform data is completed, the reset unit in the delay-free read-write control module can also utilize reset logic to carry out reset operation. Similarly, after the writing of each set of preset frequency waveform data is completed, the reset unit in the delay-free read-write control module can also use the reset logic to perform reset operation. Since each write will generate an internal reset, each write will start entirely new.

In a specific waveform data writing process, the random access memory in each memory module can be used as a front-stage buffer, one part of the preset electric field amplitude waveform data and one part of the preset frequency waveform data are respectively stored in the random access memory in the corresponding memory module, and the rest part of the preset electric field amplitude waveform data and the rest part of the preset frequency waveform data are respectively stored in the double-rate memory in the corresponding memory module. When storing in the double rate memory, the data can be written in a FIFO (first in first out) buffer mode.

As shown in fig. 3, it is assumed that the data storage module stores 1024 sets of preset waveform data, each set of preset waveform data including preset electric field amplitude waveform data and preset frequency waveform data. Taking storage of preset frequency waveform data as an example, a RAM is used as a pre-stage buffer, the first 8 data of each set of preset frequency waveform data are respectively written into the RAM of the corresponding set, and the rest data are written into the corresponding DDR address space through FIFO (first in first out) buffering. When updating a group of waveform data with preset frequency, firstly, a write pulse is generated, the group base address, the group number and the data length (write size) are latched, and then the waveform data can be updated after waiting for the reset of the reset logic to finish. Since each write will generate an internal reset, each write will start entirely new.

The process of reading data also uses RAM as a pre-buffer, taking reading a set of preset waveform data as an example, firstly latching the group base address, the group number and the data length (read size) according to a read trigger signal, and then simultaneously taking out the target electric field amplitude waveform data and the preset frequency waveform data when the read request is asserted. The first 8 pieces of read request data are taken out of the RAM, the rest data are taken out of the buffer FIFO of the DDR, the data can be taken out of the data in the next beat from the read request signal, a reset signal can be generated in the data storage module when a trigger pulse is generated each time (namely, the data reading is started by the read-write control module without delay), and the read FIFO and logic can be emptied, so that each reading is completely new.

As shown in fig. 3, the logic diagram of the ram, the double rate memory is shown. In the case of performing a batch data writing operation, it is assumed that 5 sets of preset frequency waveform data are written at a time, the waveform identifiers of the 5 sets of preset frequency waveform data are N0 to N4, and the data format is as follows.

N0: group id-000+ start address 0x00000000: 16 kbytes of data;

n1: group id-001+ start address 0x00001000: 16 kbytes of data;

n2: group id-002+ start address 0x00002000: 16 kbytes of data;

And N3: group id-003+ start address 0x00003000: 16 kbytes of data;

n4: group id-004+ start address 0x00004000: 16 kbytes of data;

a write N0 process ① of latching the group id-000 and the start address 0x00000000 according to the write trigger signal; ② . The first 8 data are written into an id-000-RAM, and the later data are written into DDR (double data Rate) corresponding addresses 0x00000000+;

a write N1 process ① of latching the group id-001 and the start address 0x00001000 according to a write trigger signal; ② . The first 8 data are written into the id-001-RAM, and the later data are written into the DDR corresponding address 0x00001000+;

a write N2 process ① of latching the group id-002 and the start address 0x00002000 according to a write trigger signal; ② . The first 8 data are written into the id-002-RAM, and the later data are written into the DDR corresponding address 0x00002000+;

A write N3 process ① of latching the group id-003 and the start address 0x00003000 according to a write trigger signal; ② . The first 8 data are written into an id-003-RAM, and the later data are written into a DDR corresponding address 0x00003000+;

A write N4 process ① of latching group id-004 and start address 0x00004000 according to a write trigger signal; ② . The first 8 data are written into the id-004-RAM, and the later data are written into the DDR corresponding address 0x00004000+.

When the waveform data is read, 8 data in the id-xxx-RAM are read first, and then the data 0xXXXXXXXX + in the DDR is read. The id-xxx-RAM may be a first storage address, a third storage address, or may be a first read address, a third read address, and 0xXXXXXXXX + may be a second storage address, a fourth storage address, or may be a second read address, a fourth read address. The double rate memory in the first memory module may be DDRG0 and the double rate memory in the second memory module may be DDRG. It should be noted that, delay exists from when the DDR double-rate memory sends out the read data enable to when the first data is output, so when the data is read, the data is read from the ram and the data is read from the double-rate memory simultaneously, but when the data is read from the ram, the data can be directly output without delay, and the delay of the subsequent data read from the ram can be used as a buffer, thereby overcoming the disadvantage of delay of the data read from the ram, and avoiding the problem of data interruption when the waveforms of the two groups are switched.

In an embodiment of the present application, optionally, the first data to be written and the second data to be written are determined based on a read delay time of a double-rate memory of the first memory module, and the third data to be written and the fourth data to be written are determined based on a read delay time of a double-rate memory of the second memory module.

In this embodiment, the first data to be written and the second data to be written corresponding to each set of preset electric field amplitude waveform data may be determined according to a read delay time of the double rate memory in the first memory module. Specifically, for each set of preset electric field amplitude waveform data of 16K bytes, the first 8 waveform data thereof may be taken as first data to be written, and the remaining data may be taken as second data to be written. Similarly, the third data to be written and the fourth data to be written corresponding to each set of preset frequency waveform data may be determined according to the read delay time of the double-rate memory in the second memory module. Specifically, for each set of preset frequency waveform data of 16K bytes, the first 8 waveform data thereof may be taken as third data to be written, and the remaining data may be taken as fourth data to be written. The first data to be written and the third data to be written have the function of avoiding the condition that data is interrupted when waveforms are switched.

In the embodiment of the present application, optionally, the storage space of the random access memory in the first storage module and the storage space of the random access memory in the second storage module are each divided into a plurality of groups, and the number of the groups is the same as the number of the groups of the preset waveform data; the first read address and the third read address comprise addresses corresponding to target group numbers in the random access memory, and the second read address and the fourth read address comprise target initial read addresses and target read data lengths in the double-rate memory; the first storage address and the third storage address comprise addresses corresponding to target group numbers in the random access memory, and the second storage address and the fourth storage address comprise target initial storage addresses and target storage data lengths in the double-rate memory.

In this embodiment, the storage space corresponding to the random access memory in the first storage module and the storage space corresponding to the random access memory in the second storage module may be divided into a plurality of groups, respectively, the number of the groups being the same as the number of groups of the preset waveform data. For example, the preset waveform data issued by the upper computer is 1024 groups, so that the storage space of the random access memory in each storage module can be divided into 1024 parts, the first 8 data of each group of preset electric field amplitude waveform data can be stored in each divided storage space of the random access memory of the first storage module, and the first 8 data of each group of preset frequency waveform data can be stored in each divided storage space of the double-rate memory of the second storage module.

The first read address and the third read address may include addresses corresponding to a target group number in the random access memory, and the second read address and the fourth read address may include a target start read address and a target read data length of the double-rate memory. For example, as shown in FIG. 3, the destination group number may be RAM 0-RAM 1023, the address corresponding to the destination group number may be RAM 0-RAM 1023, and the corresponding address may be id-000 for the destination group number RAM 0. The target start read address may be 0x00000000 or the like, and the target read data length may be the length of the remaining portion of the data stored in the random access memory divided among each set of waveform data.

Similarly, the first memory address and the third memory address include addresses corresponding to the target group number in the random access memory, and the second memory address and the fourth memory address include a target initial memory access address and a target memory data length of the double-rate memory.

In an embodiment of the present application, optionally, the random access memory is a RAM memory, and the double rate memory is a DDR memory.

In this embodiment, the random access memories in the first memory module and the second memory module may be specifically RAM memories, and may specifically be two memory areas on the same RAM memory; the double rate memory in the first memory module and the second memory module may be specifically a DDR memory, which has a characteristic of mass storage.

In the embodiment of the application, optionally, the data processing module adopts an FPGA chip or a DSP chip, and the FPGA chip or the DSP chip mounts two DDR memories.

In this embodiment, the data processing module in the single-cycle active energy-conversion digital low-level system of the synchrotron can use an FPGA chip or a DSP chip. When the DSP chip is used, the advantages of floating point operation of the DSP can be fully exerted, and the data processing capability is improved. In addition, the hardware architecture of the single-period active energy-conversion digital low-level system of the synchrotron can be realized by mounting two DDR memories on an FPGA chip as shown in fig. 4, and the FPGA chip is used as a core digital signal processing board. The hardware system is characterized in that the FPGA chip is provided with two DDR memories, and the DDR memories are respectively used for storing preset electric field amplitude waveform data and preset frequency waveform data, so that the two sets of waveform data can be conveniently read at the same time.

In the embodiment of the present application, optionally, the data processing module includes a quadrature demodulation unit and a digital signal processing unit; the quadrature demodulation unit is used for converting the digital signal into two paths of zero-frequency quadrature signals according to frequency control words extracted from the target frequency waveform data read by the delay-free read-write control module; the digital signal processing unit is used for respectively carrying out logic operation processing on the two paths of zero frequency orthogonal signals by adopting a digital PI algorithm according to the electric field amplitude set value extracted from the target electric field amplitude waveform data read by the non-delay read-write control module and the frequency control word to obtain target excitation signals.

In this embodiment, the data processing module includes two parts, a quadrature demodulation unit and a digital signal processing unit. The quadrature demodulation unit can convert the digital signal into two paths of zero-frequency quadrature signals according to the frequency control word extracted from the target frequency waveform data. Specifically, after the digital signal converted by the analog-to-digital conversion module enters the quadrature demodulation unit, two paths of quadrature signals generated by an NCO1 (digital oscillator 1) in the quadrature demodulation unit are multiplied and then enter a down-sampling subunit and a filtering subunit in the quadrature demodulation unit respectively, and after the down-sampling subunit and the filtering subunit, two paths of zero-frequency quadrature signals can be obtained.

After obtaining the two zero-frequency orthogonal signals, the digital signal processing unit can respectively perform logic operation processing on the two zero-frequency orthogonal signals by adopting a digital PI algorithm according to the electric field amplitude set value extracted from the target electric field amplitude waveform data and the frequency control word extracted from the target frequency waveform data to obtain the target excitation signal. Specifically, after two paths of zero-frequency orthogonal signals enter an amplitude phase computing subunit in a digital signal processing unit, the amplitude phase computing subunit processes the two paths of zero-frequency orthogonal signals to obtain an amplitude value of a cavity electric field sample of the synchrotron and a phase difference value between the cavity electric field and a reference signal. The amplitude value and the phase value of the cavity electric field sampling are determined by the following methods: multiplying the acquired voltage information by sine and cosine signals with corresponding frequencies respectively to obtain two zero-frequency orthogonal signals, and processing the two zero-frequency orthogonal signals to obtain corresponding amplitude values and phase values through a Cordic algorithm; the high frequency system requires a reference signal which is emitted by a signal source; after the amplitude value and the phase value of the two zero-frequency orthogonal signals are obtained through the Cordic algorithm, the phase value is obtained by utilizing the difference between the phase value and the phase value of the reference signal. Then, the amplitude value of the cavity electric field sample is subjected to difference with a set value and then is sent to a Proportional Integral (PI) calculation subunit, and an amplitude modulation signal of an NCO2 (digital oscillator 2) output Sine (SIN) signal is generated; the phase difference value is used for controlling the phase of a Sine (SIN) signal output by the NCO2, a target excitation signal is finally obtained, the target excitation signal can be converted into an analog signal by a subsequent digital-to-analog conversion module, and the analog signal is fed back to the cavity of the synchrotron. The embodiment of the application realizes the closed-loop feedback control of the amplitude and the phase of the cavity electric field through the quadrature demodulation unit and the digital signal processing unit, the amplitude tracking precision is better than 1%, and the phase control error is smaller than 1 degree.

In the embodiment of the present application, optionally, the system further includes a frequency interpolation module and a voltage interpolation module; the frequency interpolation module is used for performing linear interpolation processing on the target frequency waveform data read by the delay-free read-write control module to obtain processed target frequency waveform data; the voltage interpolation module is used for performing linear interpolation processing on the target electric field amplitude waveform data read by the delay-free read-write control module to obtain processed target electric field amplitude waveform data.

In this embodiment, the synchrotron single-cycle active energy digital low-level system can further comprise a frequency interpolation module and a voltage interpolation module. The frequency interpolation module can conduct linear interpolation processing on the target frequency waveform data read by the delay-free read-write control module to obtain processed target frequency waveform data; the voltage interpolation module can conduct linear interpolation processing on the target electric field amplitude waveform data read by the delay-free read-write control module, and processed target electric field amplitude waveform data are obtained. In order to reduce the data storage amount, the embodiment of the application can be used for taking a larger data interval in each group of preset electric field amplitude waveform data and taking a larger data interval in each group of preset frequency waveform data, for example 256us, so that the number of discrete points corresponding to the waveform data can be greatly reduced, and the data storage amount is further reduced. In order to improve the voltage and frequency accuracy of the output waveform at the time of output, waveform data may be linearly interpolated, for example, by updating the time interval interpolation of the waveform data to 2us. Specifically, the frequency interpolation module performs interpolation processing on the preset frequency waveform data to obtain processed target frequency waveform data; and carrying out interpolation processing on the preset electric field amplitude waveform data by a voltage interpolation module to obtain processed target electric field amplitude waveform data. A linear interpolation algorithm based on FPGA (field programmable gate array) is skillfully designed here. The preset electric field amplitude waveform indicated by the preset electric field amplitude waveform data and the preset frequency waveform indicated by the preset frequency waveform data may be as shown in fig. 5 and fig. 6, and it should be noted that in the embodiment of the present application, the electric field amplitude in the preset electric field amplitude waveform is represented in a voltage form. According to the embodiment of the application, through the arrangement of the frequency interpolation module and the voltage interpolation module, the stored data quantity of each group of preset electric field amplitude waveform data and each group of preset frequency waveform data is reduced, and meanwhile, the voltage and frequency precision of an output waveform can be ensured after processing, so that the method is simple and convenient.

In an embodiment of the present application, optionally, the system further includes a display module; the display module is used for displaying the plurality of groups of preset waveform data.

In this embodiment, the single-period active energy-conversion digital low-level system of the synchrotron may further include a display module, through which a plurality of sets of preset waveform data stored in the data storage module may be displayed. Specifically, the user may select one of the preset waveform data to display, or may directly display the currently used set of preset waveform data, or may display the preset waveform data according to other requirements, which is not limited herein.

Further, as a refinement and extension of the foregoing embodiment, for fully explaining the implementation process of the embodiment, another single-period active energy-conversion digital low-level system of the synchrotron is provided, as shown in fig. 7, and the system includes:

The system comprises an instance analysis module, a delay-free read-write control module, a data storage module, an analog-to-digital conversion module, a digital-to-analog conversion module, a particle extraction module, a judgment module, a frequency interpolation module, a voltage interpolation module and a data processing module, wherein the data processing module comprises a quadrature demodulation unit and a digital signal processing unit.

After the upper computer issues a plurality of groups of preset waveform data, the delay-free read-write control module stores the preset waveform data in the data storage module, and concretely, the data storage module comprises a first storage module and a second storage module, wherein the first storage module is used for storing preset electric field amplitude waveform data in each group of preset waveform data, and the second storage module is used for storing preset frequency waveform data in each group of preset waveform data. Each memory module contains two parts, one random access memory and one double rate memory. Wherein the random access memory is used for storing the former part of each set of waveform data, and the double rate memory is used for storing the rest part of each set of waveform data.

Before the treatment of the patient, the application terminal can send out an optical case signal, the case analysis module analyzes the read trigger signal and the target waveform identifier from the optical case signal, and then sends the read trigger signal and the target waveform identifier to the delay-free read-write control module. And after receiving the read trigger signal, the delay-free read-write control module reads a corresponding group of target waveform data from the data storage module according to the target waveform identification without delay, wherein each group of target waveform data comprises target electric field amplitude waveform data and target frequency waveform data. Specifically, at the time of reading, a first portion of the target electric field amplitude waveform data may be read from the random access memory of the first memory module, and a second portion of the target electric field amplitude waveform data may be read from the double rate memory of the first memory module; likewise, a first portion of the target frequency waveform data may be read from the random access memory of the second memory module and a second portion of the target frequency waveform data may be read from the double rate memory of the second memory module, thereby achieving no delay in the reading of the target waveform data. It should be noted that the reading of data from the two memory modules is performed simultaneously; the electric field amplitude is expressed in the form of voltage in the target electric field amplitude waveform data. Then, the frequency interpolation module carries out interpolation processing on the target frequency waveform data to obtain processed target frequency waveform data; the voltage interpolation module performs interpolation processing on the target electric field amplitude waveform data to obtain processed target electric field amplitude waveform data.

The analog-to-digital conversion module can collect an electric field sampling signal in the cavity of the synchronous accelerator according to a set sampling clock signal, and then can convert the electric field sampling signal into a digital signal.

The quadrature demodulation unit in the data processing module can then convert the digital signal into two zero-frequency quadrature signals according to the frequency control word extracted from the interpolation processed target frequency waveform data. Specifically, after the digital signal converted by the analog-to-digital conversion module enters the quadrature demodulation unit, the digital signal is multiplied by two paths of quadrature signals generated by an NCO1 (digital oscillator 1) in the quadrature demodulation unit and then enters a down-sampling subunit and a filtering subunit (including a CIC filter and an FIR filter) in the quadrature demodulation unit respectively, and two paths of zero-frequency quadrature signals can be obtained after passing through the down-sampling subunit and the filtering subunit.

After the two paths of zero-frequency orthogonal signals are obtained, a digital signal processing unit in the data processing module can respectively perform logic operation processing on the two paths of zero-frequency orthogonal signals by adopting a digital PI algorithm according to an electric field amplitude set value extracted from target electric field amplitude waveform data after interpolation processing and a frequency control word extracted from the target frequency waveform data to obtain target excitation signals. Specifically, after two paths of zero-frequency orthogonal signals enter an amplitude phase computing subunit in a digital signal processing unit, the amplitude phase computing subunit processes the two paths of zero-frequency orthogonal signals to obtain an amplitude value of a cavity electric field sample of the synchrotron and a phase difference value between the cavity electric field and a reference signal. The amplitude value and the phase value of the cavity electric field sampling are determined by the following methods: multiplying the acquired voltage information by sine and cosine signals with corresponding frequencies respectively to obtain two zero-frequency orthogonal signals, and processing the two zero-frequency orthogonal signals to obtain corresponding amplitude values and phase values through a Cordic algorithm; the high frequency system requires a reference signal which is emitted by a signal source; after the amplitude value and the phase value of the two zero-frequency orthogonal signals are obtained through the Cordic algorithm, the phase value is obtained by utilizing the difference between the phase value and the phase value of the reference signal. Then, the amplitude value of the cavity electric field sample is subjected to difference with a set value and then is sent to a Proportional Integral (PI) calculation subunit, and an amplitude modulation signal of an NCO2 (digital oscillator 2) output Sine (SIN) signal is generated; the phase difference value is used for controlling the phase of a Sine (SIN) signal output by the NCO2, a target excitation signal is finally obtained, the subsequent digital-to-analog conversion module can convert the target excitation signal into an analog signal, and the analog signal is fed back to the cavity of the synchrotron, so that the cavity can perform energy conversion treatment on internal particles.

After energy conversion treatment, the particle extraction module can extract a preset number of particles from the cavity of the synchrotron, and the particles can be used for treating the focus of a patient. After the particles are led out, the judging module can determine the number of the residual particles in the cavity of the synchrotron, determine the size relation between the number of the residual particles and the preset number, if the number of the residual particles is larger than or equal to the preset number through judgment, the application terminal can send out the optical case signal again at the moment, the optical case signal can comprise a new target waveform identifier and a reading trigger signal, the new target waveform identifier is used for indicating the waveform required by the next irradiation of the patient, and the step of analyzing the optical case signal by the case analyzing module is returned. If the number of the residual particles is less than the preset number, the acquisition operation of the analog-to-digital conversion module can be interrupted at the moment, the synchrotron supplies particles again through a new pulse, so that the number of the particles in the cavity is greater than the preset number, the acquisition operation of the analog-to-digital conversion module is restored, and energy conversion processing is continued until the treatment of the patient is finished.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. The single-period active energy-changing digital low-level system of the synchrotron is characterized by comprising an instance analysis module, a non-delay read-write control module, a data storage module, an analog-to-digital conversion module, a data processing module, a digital-to-analog conversion module, a particle extraction module and a judging module:

2. The single-cycle active energy-changing digital low level system of the synchrotron according to claim 1, wherein the non-delay read-write control module comprises a signal receiving unit, a reset unit, an address determining unit and a data reading unit;

3. The synchrotron single-cycle active energy-changing digital low-level system according to claim 2, wherein the non-delay read-write control module further comprises a data writing unit, and the non-delay read-write control module is further configured to:

4. The synchrotron single-cycle active energy-changing digital low-level system according to claim 3, wherein,

The first data to be written and the second data to be written are determined based on the read delay time of the double-rate memory of the first memory module, and the third data to be written and the fourth data to be written are determined based on the read delay time of the double-rate memory of the second memory module.

5. The synchrotron single-cycle active energy-changing digital low-level system of claim 4, wherein,

The storage space of the random access memory in the first storage module and the storage space of the random access memory in the second storage module are divided into a plurality of groups, and the number of the groups is the same as that of the preset waveform data;

6. The synchrotron single-cycle active-energy digital low-level system according to any one of claims 2 to 5, characterized in that,

The random access memory is a RAM memory, and the double rate memory is a DDR memory.

7. The synchrotron single-cycle active energy-changing digital low-level system of claim 6, wherein,

The data processing module adopts an FPGA chip or a DSP chip, and the FPGA chip or the DSP chip is provided with two DDR memories.

8. The single-cycle active energy-conversion digital low-level system of the synchrotron according to claim 1, wherein the data processing module comprises a quadrature demodulation unit and a digital signal processing unit;

9. The synchrotron single-cycle active energy-changing digital low-level system according to claim 1, wherein the system further comprises a frequency interpolation module and a voltage interpolation module;

10. The synchrotron single-cycle active energy-changing digital low-level system according to claim 1, further comprising a display module;