CN118041260B

CN118041260B - Signal processing method for front-end circuit and front-end circuit

Info

Publication number: CN118041260B
Application number: CN202410430834.XA
Authority: CN
Inventors: 刘伟
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Filing date: 2024-04-11
Publication date: 2024-06-28
Anticipated expiration: 2044-04-11

Abstract

The application relates to the technical field of computers and provides a signal processing method for a front-end circuit and the front-end circuit. The method comprises the following steps: converting the first input differential voltage signal into a first output differential voltage signal by a first stage signal processing circuit; converting the first output differential voltage signal into a second output differential voltage signal through a second stage signal processing circuit; and converting the second output differential voltage signal into a third output differential voltage signal through a third-stage signal processing circuit. Therefore, by utilizing the circuit design details and characteristics of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit, the data receiving and transmitting under the action of different reference voltages in a high-voltage domain can be realized, and the method has the advantages of low power consumption, high bandwidth, large gain and the like.

Description

Signal processing method for front-end circuit and front-end circuit

Technical Field

The present application relates to the field of computer technologies, and in particular, to a signal processing method for a front-end circuit and a front-end circuit.

Background

With the continuous development of semiconductor technology, the size of semiconductor devices, such as channel length, is reduced, improving integration and optimizing power consumption. However, the shorter channel length of the semiconductor device generally means that the voltage resistance of the semiconductor device is reduced, so that the voltage resistance range of the device is smaller as the channel length of the device is shorter and shorter with the popularization of advanced processes. In front-end circuit applications, such as those used in double rate synchronous dynamic random access memories (Double Data Rate Synchronous Dynamic Random Access Memory, DDR), it is desirable to meet different reference voltages under different protocol specifications, and to receive and transmit data in the voltage domain specified by the reference voltages. Some protocols specify high voltage domains, e.g., 1.1 volts, 1.2 volts, and therefore require the reception and transmission of data in the high voltage domain. In the prior art, high voltage devices or input/output devices capable of withstanding high voltages are used. However, with the evolution and popularization of advanced semiconductor technology, high-voltage devices or input/output devices capable of bearing high voltage have larger power consumption, and the high-frequency characteristic of the high-voltage devices becomes a bottleneck for receiving data by a front-end circuit, so that the circuit bandwidth is affected.

Therefore, the application provides a signal processing method for a front-end circuit and the front-end circuit, which are used for solving the technical problems in the prior art.

Disclosure of Invention

In a first aspect, the present application provides a signal processing method for a front-end circuit. The signal processing method comprises the following steps: converting a first input differential voltage signal into a first output differential voltage signal through a first stage signal processing circuit, wherein the first stage signal processing circuit comprises a first field effect transistor pair, a control electrode and a bias electrode of the first field effect transistor pair are respectively and electrically connected with the first input differential voltage signal and the first output differential voltage signal, and the first stage signal processing circuit further comprises a current mode logic structure based on the first field effect transistor pair so as to realize matching between the first input differential voltage signal and the first output differential voltage signal on the first stage signal processing circuit; converting the first output differential voltage signal into a second output differential voltage signal through a second-stage signal processing circuit, wherein the second-stage signal processing circuit comprises a second field effect transistor pair, and a control electrode and a load electrode of the second field effect transistor pair are respectively and electrically connected with the first output differential voltage signal and the second output differential voltage signal; and converting the second output differential voltage signal into a third output differential voltage signal through a third-stage signal processing circuit. The third-stage signal processing circuit comprises a third field effect transistor pair, wherein a control pole and a bias pole of the third field effect transistor pair are respectively and electrically connected with the second output differential voltage signal and the third output differential voltage signal, the first input differential voltage signal and the first output differential voltage signal are positioned in a high voltage domain, the second output differential voltage signal and the third output differential voltage signal are positioned in a low voltage domain relative to the high voltage domain, and a load pole of the second field effect transistor pair is respectively and electrically connected with the control pole of the third field effect transistor pair so as to form a source following structure, so that the voltage resistance of the second output differential voltage signal applied to the control pole of the third field effect transistor pair is matched, and a load device electrically connected with the load pole of the second field effect transistor pair adopts a negative impedance connection structure for providing gain bandwidth compensation for the source following structure.

According to the first aspect of the application, through the three-stage circuit structure consisting of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit, the circuit design details and characteristics of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit are utilized, the input and output electric connection modes of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit are utilized, the current mode logic structure based on the first field effect transistor pair in the first-stage signal processing circuit is combined, the source following structure is utilized so as to ensure that the output voltage does not exceed the withstand voltage of a low-voltage device, and the gain bandwidth compensation aiming at the source following structure is provided by utilizing the negative impedance connection structure, so that the data receiving and transmitting under the action of different reference voltages under the high-voltage domain can be met, and the advantages of low power consumption, high bandwidth, large gain and the like are realized.

In a possible implementation manner of the first aspect of the present application, the negative impedance connection structure used by the load device electrically connected to the load electrode of the second fet pair is a cross-tube coupling connection structure.

In a possible implementation manner of the first aspect of the present application, the load device electrically connected to the load electrode of the second fet pair includes a common-source common-drain N-type fet pair, and the respective control electrodes of the common-source common-drain N-type fet pair are electrically connected to the load electrode of the second fet pair and the first output differential voltage signal according to the cross-tube coupling structure.

In a possible implementation manner of the first aspect of the present application, the second stage signal processing circuit further comprises a positive feedback connection structure for the second output differential voltage signal to thereby boost an output gain of the second stage signal processing circuit, the positive feedback connection structure providing positive feedback from the first output differential voltage signal to the second output differential voltage signal based on the cross-pipe coupling connection structure.

In a possible implementation manner of the first aspect of the present application, the first fet pair is a first fet pair, the control electrode and the bias electrode of the first fet pair are respectively a gate and a drain of the first fet pair, the first stage signal processing circuit further includes a first source degeneration structure based on the first fet pair for providing channel attenuation compensation, the first source degeneration structure includes a first adjustable capacitor and a first adjustable resistor connected in parallel between sources of the first fet pair, and the first source degeneration structure further includes a first current source pair electrically connected to sources of the first fet pair, respectively.

In a possible implementation manner of the first aspect of the present application, the third fet pair is a third fet pair, the control electrode, the bias electrode, and the load electrode of the third fet pair are respectively the gate electrode, the drain electrode, and the source electrode of the third fet pair, the third stage signal processing circuit further includes a second source degeneration structure based on the third fet pair for providing channel attenuation compensation, the second source degeneration structure includes a second adjustable capacitor and a second adjustable resistor connected in parallel between the sources of the third fet pair, and the second source degeneration structure further includes a second current source pair electrically connected to the sources of the third fet pair, respectively.

In a possible implementation manner of the first aspect of the present application, the second current source pair is an adjustable current source for adjusting an output gain of the third stage signal processing circuit, and the third stage signal processing circuit further includes an output feedforward capacitor.

In a possible implementation manner of the first aspect of the present application, the signal processing method further includes: the method further includes increasing a magnitude of a first output current of the first current source pair included in the first source degeneration structure to decrease a magnitude of a common mode level of the first output differential voltage signal output by the first stage signal processing circuit, and increasing a magnitude of the load device electrically connected to a load electrode of the second field effect transistor pair to decrease a level of the second output differential voltage signal output by the second stage signal processing circuit such that the magnitude of the common mode level of the second output differential voltage signal input to the third stage signal processing circuit matches an output gain of the third stage signal processing circuit.

In a possible implementation manner of the first aspect of the present application, the first fet pair and the second fet pair are both high-voltage devices, and the third fet pair is a low-voltage device with respect to the high-voltage devices.

In a possible implementation manner of the first aspect of the present application, the signal processing method is applied to an analog front-end circuit, the analog front-end circuit is used for amplifying and filtering a high-voltage domain electrical signal, the first stage signal processing circuit is a high-voltage interface circuit of the analog front-end circuit, the second stage signal processing circuit is a voltage domain conversion circuit of the analog front-end circuit, and the third stage signal processing circuit is a low-voltage amplifying circuit of the analog front-end circuit.

In a possible implementation manner of the first aspect of the present application, the analog front-end circuit is configured to adapt a plurality of double-rate synchronous dynamic random access memory protocols, each of the plurality of double-rate synchronous dynamic random access memory protocols defining different reference voltages, and is configured to receive an input data signal at the different reference voltages and provide voltage domain conversion, attenuation compensation and swing amplification of the input data signal, thereby outputting a low voltage domain output data signal with respect to the different reference voltages.

In a possible implementation manner of the first aspect of the present application, the low voltage domain output data signal is used for a data decoding circuit or a decision feedback equalization circuit, and the data decoding circuit and the decision feedback equalization circuit are both operated at a low voltage.

In a second aspect, an embodiment of the present application further provides a front-end circuit. The front-end circuit includes: the first-stage signal processing circuit is used for converting a first input differential voltage signal into a first output differential voltage signal, wherein the first-stage signal processing circuit comprises a first field effect transistor pair, a control electrode and a bias electrode of the first field effect transistor pair are respectively and electrically connected with the first input differential voltage signal and the first output differential voltage signal, and the first-stage signal processing circuit further comprises a current mode logic structure based on the first field effect transistor pair so as to realize matching between the first input differential voltage signal and the first output differential voltage signal on the first-stage signal processing circuit; the second-stage signal processing circuit is used for converting the first output differential voltage signal into a second output differential voltage signal, wherein the second-stage signal processing circuit comprises a second field effect transistor pair, and a control electrode and a load electrode of the second field effect transistor pair are respectively and electrically connected with the first output differential voltage signal and the second output differential voltage signal; the third-stage signal processing circuit is used for converting the second output differential voltage signal into a third output differential voltage signal, wherein the third-stage signal processing circuit comprises a third field effect transistor pair, a control electrode and a bias electrode of the third field effect transistor pair are respectively and electrically connected with the second output differential voltage signal and the third output differential voltage signal, the first input differential voltage signal and the first output differential voltage signal are located in a high voltage domain, and the second output differential voltage signal and the third output differential voltage signal are located in a low voltage domain opposite to the high voltage domain. The load electrodes of the second field effect transistor pair are respectively and electrically connected with the control electrodes of the third field effect transistor pair so as to form a source following structure, so that the second output differential voltage signal applied to the control electrodes of the third field effect transistor pair is ensured to match the voltage resistance of the third field effect transistor pair, and a load device electrically connected with the load electrodes of the second field effect transistor pair adopts a negative impedance connection structure for providing gain bandwidth compensation aiming at the source following structure.

In a possible implementation manner of the second aspect of the present application, the negative impedance connection structure adopted by the load device electrically connected to the load electrode of the second fet pair is a cross-tube coupling connection structure, and the load device electrically connected to the load electrode of the second fet pair includes a common-source common-drain N-type fet pair, and the respective control electrodes of the common-source common-drain N-type fet pair are electrically connected to the load electrode of the second fet pair and the first output differential voltage signal according to the cross-tube coupling connection structure.

In one possible implementation manner of the second aspect of the present application, the first fet pair is a first fet pair, the control electrode and the bias electrode of the first fet pair are respectively the gate and the drain of the first fet pair, the first stage signal processing circuit further includes a first source degeneration structure based on the first fet pair for providing channel attenuation compensation, the first source degeneration structure includes a first adjustable capacitor and a first adjustable resistor connected in parallel between the sources of the first fet pair, the first source degeneration structure further includes a first current source pair electrically connected to the sources of the first fet pair, and the third fet pair is a third fet pair, the control electrode, the bias electrode, and the load electrode of the third fet pair are respectively the gate, the drain, and the source of the third fet pair, the third stage signal processing circuit further includes a second adjustable capacitor and a first adjustable resistor connected in parallel between the sources of the first fet pair, the first source degeneration structure further includes a third source degeneration structure based on the third fet pair and the second source degeneration structure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a signal processing method for a front-end circuit according to an embodiment of the present application;

Fig. 2 is a schematic diagram of a front-end circuit according to a first embodiment of the present application;

Fig. 3 is a schematic diagram of a front-end circuit according to a second embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of the application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

Fig. 1 is a schematic flow chart of a signal processing method for a front-end circuit according to an embodiment of the present application. As shown in fig. 1, the signal processing method includes the following steps.

Step S110: the first stage signal processing circuit is used for converting a first input differential voltage signal into a first output differential voltage signal, wherein the first stage signal processing circuit comprises a first field effect transistor pair, a control electrode and a bias electrode of the first field effect transistor pair are respectively and electrically connected with the first input differential voltage signal and the first output differential voltage signal, and the first stage signal processing circuit further comprises a current mode logic structure based on the first field effect transistor pair so as to realize matching between the first input differential voltage signal and the first output differential voltage signal on the first stage signal processing circuit.

Step S120: and converting the first output differential voltage signal into a second output differential voltage signal through a second-stage signal processing circuit, wherein the second-stage signal processing circuit comprises a second field effect transistor pair, and a control electrode and a load electrode of the second field effect transistor pair are respectively and electrically connected with the first output differential voltage signal and the second output differential voltage signal.

Step S130: the second output differential voltage signal is converted into a third output differential voltage signal through a third-stage signal processing circuit, wherein the third-stage signal processing circuit comprises a third field effect transistor pair, a control electrode and a bias electrode of the third field effect transistor pair are respectively and electrically connected with the second output differential voltage signal and the third output differential voltage signal, the first input differential voltage signal and the first output differential voltage signal are located in a high voltage domain, and the second output differential voltage signal and the third output differential voltage signal are located in a low voltage domain opposite to the high voltage domain.

Referring to fig. 1, the load poles of the second fet pair are respectively electrically connected to the control poles of the third fet pair to form a source follower structure so as to ensure that the second output differential voltage signal applied to the control poles of the third fet pair matches the voltage resistance of the third fet pair, and the load devices electrically connected to the load poles of the second fet pair employ a negative impedance connection structure for providing gain bandwidth compensation for the source follower structure. Thus, through the three-stage circuit structure consisting of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit, the advantages of converting the first input differential voltage signal into the first output differential voltage signal, converting the first output differential voltage signal into the second output differential voltage signal and converting the second output differential voltage signal into the third output differential voltage signal are realized, and the data receiving and transmitting under the action of different reference voltages in a high voltage domain can be satisfied by utilizing the circuit design details and characteristics of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit, and the advantages of low power consumption, high bandwidth, large gain and the like are realized.

Referring to fig. 1, in step S110: the first input differential voltage signal is converted into a first output differential voltage signal by a first stage signal processing circuit. Regarding circuit design details and characteristics of the first stage signal processing circuit, the first stage signal processing circuit includes a first fet pair, a control electrode and a bias electrode of the first fet pair are respectively electrically connected to the first input differential voltage signal and the first output differential voltage signal, and the first stage signal processing circuit further includes a current mode logic structure based on the first fet pair to realize matching between the first input differential voltage signal and the first output differential voltage signal on the first stage signal processing circuit. In this way, by the current mode logic (Current Model Logic, CML) structure, it means that the matching of the input and the output is integrated in the current stage circuit, so that the matching between the first input differential voltage signal and the first output differential voltage signal is realized on the first stage signal processing circuit based on the current mode logic structure of the first fet pair, which is helpful for realizing the decoupling design between the first stage signal processing circuit and the subsequent stage circuit and is also helpful for optimizing the subsequent stage circuit. In addition, the first input differential voltage signal is an external input signal from the whole front-end circuit, and the first stage signal processing circuit utilizes the CML structure to realize matching in the stage circuit, so that the voltage domain where the first input differential voltage signal is located can be better adapted, different reference voltages under different protocol regulations can be better adapted, and data can be received and transmitted under the voltage domain regulated by the reference voltages. Here, the control electrode and the bias electrode of the first fet pair are electrically connected to the first input differential voltage signal and the first output differential voltage signal, respectively, and therefore, the first input differential voltage signal is applied to the control electrode of the first fet pair as an input of the first stage signal processing circuit, and the first output differential voltage signal is drawn from the bias electrode of the first fet pair as an output of the first stage signal processing circuit.

With continued reference to fig. 1, in step S120, the first output differential voltage signal is converted into a second output differential voltage signal by a second stage signal processing circuit. Regarding circuit design details and characteristics of the second stage signal processing circuit, the second stage signal processing circuit includes a second fet pair, and a control electrode and a load electrode of the second fet pair are electrically connected to the first output differential voltage signal and the second output differential voltage signal, respectively. As such, the first output differential voltage signal is drawn from the bias electrode of the first fet pair as an output of the first stage signal processing circuit, and the first output differential voltage signal is applied to the control electrode of the second fet pair as an input of the second stage signal processing circuit. The second output differential voltage signal is drawn from the load electrode of the second FET pair as an output of a second stage signal processing circuit.

With continued reference to fig. 1, in step S130, the second output differential voltage signal is converted into a third output differential voltage signal by a third stage signal processing circuit. Regarding circuit design details and characteristics of a third stage signal processing circuit, the third stage signal processing circuit includes a third fet pair having a control electrode and a bias electrode electrically connected to the second output differential voltage signal and the third output differential voltage signal, respectively. As such, the second output differential voltage signal is drawn from the load poles of the second fet pair as an output of a second stage signal processing circuit, and the second output differential voltage signal is applied to the control poles of a third fet pair as an input of the third stage signal processing circuit. The third output differential voltage signal is drawn from the bias electrode of the third fet pair as an output of a third stage signal processing circuit.

With continued reference to fig. 1, the first input differential voltage signal and the first output differential voltage signal are in a high voltage domain, and the second output differential voltage signal and the third output differential voltage signal are in a low voltage domain relative to the high voltage domain. Thus, the input of the first-stage signal processing circuit, that is, the first input differential voltage signal and the output of the first-stage signal processing circuit, that is, the first output differential voltage signal are both located in a high-voltage domain, so that the first-stage signal processing circuit adopts a high-voltage device for meeting the requirements of different reference voltages in the high-voltage domain, and the matching between the first input differential voltage signal and the first output differential voltage signal is realized on the first-stage signal processing circuit based on the current mode logic structure of the first field effect transistor pair. The input of the second stage signal processing circuit, i.e. the first output differential voltage signal, is located in a high voltage domain, and the output of the second stage signal processing circuit, i.e. the second output differential voltage signal, is located in a low voltage domain with respect to the high voltage domain, and therefore the second stage signal processing circuit is arranged to convert the first output differential voltage signal located in the high voltage domain into the second output differential voltage signal located in the low voltage domain, i.e. to effect a voltage domain conversion from the high voltage domain to the low voltage domain. The input of the third-stage signal processing circuit, that is, the second output differential voltage signal and the output of the third-stage signal processing circuit, that is, the third output differential voltage signal, are both in the low voltage domain, and therefore, the third-stage signal processing circuit adopts a low-voltage device. In other words, the third stage signal processing circuit can apply semiconductor advanced process, and the device has smaller size such as shorter channel length, which can promote integration and improve power consumption.

Referring to fig. 1, it should be understood that the first fet pair, the second fet pair, and the third fet pair each refer to a pair of fets of the same type and the same specification, such as a pair of N-Metal-Oxide-Semiconductor (NMOS) transistors or N-type fets, and such as a pair of P-Metal-Oxide-Semiconductor (PMOS) transistors or P-type fets. The respective electrodes, such as the control electrode, bias electrode, and load electrode, of the first fet pair, the second fet pair, and the third fet pair may be determined in conjunction with the particular fet type. In some embodiments, the first fet pair, the second fet pair, and the third fet are NMOS transistors, i.e., N-type fets, and the control electrodes, bias electrodes, and load electrodes of the first fet pair, the second fet pair, and the third fet are gates, drains, and sources of the N-type fet pair, respectively.

As described above, the first input differential voltage signal and the first output differential voltage signal are located in a high voltage domain, and the second output differential voltage signal and the third output differential voltage signal are located in a low voltage domain with respect to the high voltage domain. Therefore, the third stage signal processing circuit may employ a low voltage device and apply semiconductor advanced processes. In order to ensure that the input of the third stage signal processing circuit does not exceed the upper limit of the withstand voltage performance of the low voltage device, specific circuit design details and characteristics are provided between the second fet pair of the second stage signal processing circuit and the third fet pair of the third stage signal processing circuit, in particular, the load poles of the second fet pair are electrically connected to the control poles of the third fet pair respectively so as to form a source follower structure so as to ensure that the second output differential voltage signal applied to the control poles of the third fet pair matches the withstand voltage performance of the third fet pair. In this way, the output of the second output differential voltage signal is led out from the load electrode of the second field effect transistor pair as the output of the second stage signal processing circuit, and the input of the second output differential voltage signal is applied to the control electrode of the third stage signal processing circuit, and the control electrodes of the third field effect transistor pair are respectively and electrically connected through the load electrodes of the second stage signal processing circuit so as to form a source following structure, so that the output voltage does not exceed the withstand voltage of the low-voltage device, the decoupling design between the second stage signal processing circuit and the later stage circuit is facilitated, and the application of more advanced semiconductor manufacturing process and shorter channel length devices on the third stage signal processing circuit is facilitated. In view of the reduced gain bandwidth of the output caused by the source follower structure, the reduced gain bandwidth may be disadvantageous for improving the signal-to-noise ratio and suppressing noise, for this purpose, a load device electrically connected to the load electrode of the second fet pair is provided with a negative impedance connection structure for providing gain bandwidth compensation for the source follower structure. Therefore, the load device electrically connected with the load electrode of the second field effect transistor pair adopts a negative impedance connection structure, so that negative impedance is equivalently generated, namely, the negative resistance characteristic or the characteristic that the voltage is increased and the current is reduced is realized, and the gain bandwidth of the second-stage signal processing circuit can be improved, and further gain bandwidth compensation aiming at the source following structure is provided.

Referring to the steps of fig. 1, it can be seen that the first stage signal processing circuit, the second stage signal processing circuit and the third stage signal processing circuit each include a pair of field effect transistors in the present stage circuit, and the step-by-step processing of signals is realized by a specific electrical connection manner between the pair of field effect transistors. Specifically, in the first stage signal processing circuit, the first input differential voltage signal is applied as an input of the first stage signal processing circuit to the control electrode of the first fet pair, and the first output differential voltage signal is drawn from the bias electrode of the first fet pair as an output of the first stage signal processing circuit; at a second stage signal processing circuit, the first output differential voltage signal is applied as an input to the second stage signal processing circuit to the control electrodes of the second fet pair, the second output differential voltage signal is pulled from the load electrodes of the second fet pair as an output of the second stage signal processing circuit; in the third stage signal processing circuit, the second output differential voltage signal is applied as an input to the third stage signal processing circuit to the control electrode of the third field effect transistor pair, and the third output differential voltage signal is pulled from the bias electrode of the third field effect transistor pair as an output of the third stage signal processing circuit. It should be noted that, on the one hand, the inputs of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit are all applied to the control electrode of the fet pair of the present-stage circuit, and on the other hand, the output of the first-stage signal processing circuit is led out from the bias electrode of the fet pair, the output of the second-stage signal processing circuit is led out from the load electrode of the fet pair, and the output of the third-stage signal processing circuit is led out from the bias electrode of the fet pair, so that the input-output electrical connection modes of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit are combined with other circuit design details and characteristics of the present-stage circuit, including the current-mode logic structure, the source follower structure and the negative impedance connection structure, thereby forming the front-end circuit of the three-stage circuit structure as a whole, satisfying the data receiving and transmitting under the different reference voltages in the high-voltage domain, and having the advantages of low power consumption, high bandwidth, large gain and the like.

In summary, the signal processing method for a front-end circuit shown in fig. 1 utilizes the circuit design details and characteristics of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit through a three-stage circuit structure composed of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit, utilizes the input and output electric connection modes of the first-stage signal processing circuit, the second-stage signal processing circuit and the third-stage signal processing circuit, combines the current mode logic structure based on the first field effect transistor pair in the first-stage signal processing circuit, utilizes a source following structure so as to ensure that the output voltage does not exceed the withstand voltage of a low-voltage device, and utilizes a negative impedance connection structure to provide gain bandwidth compensation for the source following structure, so that the method not only can meet the requirements of data receiving and transmitting under the action of different reference voltages under the high-voltage domain, but also has the advantages of low power consumption, high bandwidth, large gain and the like.

Fig. 2 is a schematic diagram of a front-end circuit according to a first embodiment of the present application. As shown in fig. 2, the front-end circuit includes: a first stage signal processing circuit a201 for converting a first input differential voltage signal a204 into a first output differential voltage signal a205; a second stage signal processing circuit a202, configured to convert the first output differential voltage signal a205 into a second output differential voltage signal a206; the third stage signal processing circuit a203 is configured to convert the second output differential voltage signal a206 into a third output differential voltage signal a207. The first stage signal processing circuit a201 includes a first field effect transistor pair, and a control electrode and a bias electrode of the first field effect transistor pair are respectively electrically connected to the first input differential voltage signal a204 and the first output differential voltage signal a205, and the first stage signal processing circuit a201 further includes a current mode logic structure based on the first field effect transistor pair so as to implement matching between the first input differential voltage signal a204 and the first output differential voltage signal a205 on the first stage signal processing circuit a 201. The second stage signal processing circuit a202 includes a second fet pair, where a control electrode and a load electrode of the second fet pair are electrically connected to the first output differential voltage signal a205 and the second output differential voltage signal a206, respectively. The third stage signal processing circuit a203 includes a third fet pair, where a control electrode and a bias electrode of the third fet pair are electrically connected to the second output differential voltage signal a206 and the third output differential voltage signal a207, respectively. The first input differential voltage signal a204 and the first output differential voltage signal a205 are located in a high voltage domain, and the second output differential voltage signal a206 and the third output differential voltage signal a207 are located in a low voltage domain with respect to the high voltage domain. The load poles of the second fet pair are respectively electrically connected to the control poles of the third fet pair to form a source follower structure so as to ensure that the second output differential voltage signal a206 applied to the control poles of the third fet pair matches the withstand voltage of the third fet pair, and the load devices electrically connected to the load poles of the second fet pair employ a negative impedance connection structure for providing gain bandwidth compensation for the source follower structure.

The front-end circuit shown in fig. 2 uses the three-stage circuit structure composed of the first-stage signal processing circuit a201, the second-stage signal processing circuit a202 and the third-stage signal processing circuit a203, uses the circuit design details and characteristics of the first-stage signal processing circuit a201, the second-stage signal processing circuit a202 and the third-stage signal processing circuit a203, uses the input and output electric connection modes of the first-stage signal processing circuit a201, the second-stage signal processing circuit a202 and the third-stage signal processing circuit a203, combines the current mode logic structure based on the first field effect transistor pair in the first-stage signal processing circuit a201, uses the source following structure so as to ensure that the output voltage cannot exceed the withstand voltage of a low-voltage device, and uses the negative impedance connection structure to provide gain bandwidth compensation for the source following structure, so that the front-end circuit can not only meet the requirements of receiving and transmitting data under the action of different reference voltages in a high-voltage domain, but also has the advantages of low power consumption, high bandwidth, large gain and the like.

Fig. 3 is a schematic diagram of a front-end circuit according to a second embodiment of the present application. The signal processing method for the front-end circuit shown in fig. 1 and the front-end circuit of the first embodiment shown in fig. 2 refer to a first fet pair, a second fet pair and a third fet pair. Fig. 3 shows an exemplary case in which the first fet pair, the second fet pair, and the third fet pair are NMOS transistors or N-type fets. The control electrode, the bias electrode and the load electrode of the first field effect transistor pair, the second field effect transistor pair and the third field effect transistor are respectively the grid electrode, the drain electrode and the source electrode of the N-type field effect transistor pair. Specifically, the first fet pair is a first fet pair (an fet a310 and an fet B320), and the control electrode and the bias electrode of the first fet pair are the gate and the drain of the first fet pair, respectively. The third fet pair is a third fet pair (N-fet E350 and N-fet F360), and the control electrode, bias electrode, and load electrode of the third fet pair are respectively the gate electrode, drain electrode, and source electrode of the third fet pair. It should be appreciated that the first input differential voltage signal B304, the first output differential voltage signal B305, the second output differential voltage signal B306, and the third output differential voltage signal B307 are all differential signal pairs, and thus the electrodes of the corresponding fet pairs electrically connected to these differential signal pairs are also in the sense of differential signal pairs. In addition, the first stage signal processing circuit B301 further includes a peripheral circuit a370 for providing necessary operating voltages and bias conditions. The second stage signal processing circuit B302 further includes a peripheral circuit B380 for providing necessary operating voltages and bias conditions. Drain 332 of fet C330 and drain 342 of fet D340 are electrically connected to peripheral circuit B380. The third stage signal processing circuit B303 further includes a peripheral circuit C390 for providing necessary operating voltages and bias conditions. As described in further detail below in connection with fig. 3.

Referring to fig. 3, the front-end circuit includes: the first stage signal processing circuit B301 is configured to convert the first input differential voltage signal B304 into a first output differential voltage signal B305. The first stage signal processing circuit B301 includes a first fet pair (fet a310 and fet B320). The control electrode and the bias electrode of the first field effect transistor pair are respectively and electrically connected with the first input differential voltage signal B304 and the first output differential voltage signal B305; the control electrode of the first fet pair, that is, the gate 314 of the N-fet a310 and the gate 324 of the N-fet B320, are electrically connected to the first input differential voltage signal B304; the bias electrode of the first fet pair, that is, the drain 312 of the fet a310 and the drain 322 of the fet B320, is electrically connected to the first output differential voltage signal B305. The first input differential voltage signal B304 is applied to the control electrodes (the gate 314 of the N-type field-effect transistor a310 and the gate 324 of the N-type field-effect transistor B320) of the first field-effect transistor pair as an input to the first-stage signal processing circuit B301, and the first output differential voltage signal B305 is extracted from the bias electrodes (the drain 312 of the N-type field-effect transistor a310 and the drain 322 of the N-type field-effect transistor B320) of the first field-effect transistor pair as an output of the first-stage signal processing circuit B301. The first stage signal processing circuit B301 further includes a current mode logic structure based on the first fet pair to enable matching between the first input differential voltage signal B304 and the first output differential voltage signal B305 on the first stage signal processing circuit B301.

Referring to fig. 3, the front-end circuit further includes: the second stage signal processing circuit B302 is configured to convert the first output differential voltage signal B305 into a second output differential voltage signal B306. The second stage signal processing circuit B302 includes a second fet pair (fet C330 and fet D340). The control electrode and the load electrode of the second field effect transistor pair are respectively and electrically connected with the first output differential voltage signal B305 and the second output differential voltage signal B306; the control electrode of the second fet pair, that is, the gate 334 of the fet C330 and the gate 344 of the fet D340 are electrically connected to the first output differential voltage signal B305; the load electrodes of the second fet pair, i.e., the source 336 of the fet C330 and the source 346 of the fet D340, are electrically connected to the second output differential voltage signal B306. The first output differential voltage signal B305 is applied to the control electrodes (the gate 334 of the N-type field-effect transistor C330 and the gate 344 of the N-type field-effect transistor D340) of the second field-effect transistor pair as an input to the second-stage signal processing circuit B302, and the second output differential voltage signal B306 is extracted from the load electrodes (the source 336 of the N-type field-effect transistor C330 and the source 346 of the N-type field-effect transistor D340) of the second field-effect transistor pair as an output of the second-stage signal processing circuit B302.

Referring to fig. 3, the front-end circuit further includes: the third-stage signal processing circuit B303 is configured to convert the second output differential voltage signal B306 into a third output differential voltage signal B307. The third stage signal processing circuit B303 includes a third fet pair (fet E350 and fet F360). The control electrode and the bias electrode of the third fet pair are electrically connected to the second output differential voltage signal B306 and the third output differential voltage signal B307, respectively; the control electrode of the third fet pair, that is, the gate 354 of the fet E350 and the gate 364 of the fet F360 are electrically connected to the second output differential voltage signal B306, and the bias electrode of the third fet pair, that is, the drain 352 of the fet E350 and the drain 362 of the fet F360 are electrically connected to the third output differential voltage signal B307. The second output differential voltage signal B306 is applied as an input to the third-stage signal processing circuit B303 to the control electrodes (the gate 354 of the N-type field-effect transistor E350 and the gate 364 of the N-type field-effect transistor F360) of the third field-effect transistor pair, and the third output differential voltage signal B307 is extracted as an output from the third-stage signal processing circuit B303 from the bias electrodes (the drain 352 of the N-type field-effect transistor E350 and the drain 362 of the N-type field-effect transistor F360) of the third field-effect transistor pair.

Referring to fig. 3, the first input differential voltage signal B304 and the first output differential voltage signal B305 are located in a high voltage domain, and the second output differential voltage signal B306 and the third output differential voltage signal B307 are located in a low voltage domain with respect to the high voltage domain. Therefore, the first stage signal processing circuit B301 uses high voltage devices for satisfying the requirements of different reference voltages in the high voltage domain, and the third stage signal processing circuit B303 can use semiconductor advanced process, and the devices have smaller dimensions such as shorter channel length, which can improve the integration level and improve the power consumption. Therefore, the peripheral circuit C390 of the third stage signal processing circuit B303 can be powered with a low voltage and use a low voltage device, which is advantageous for applying semiconductor advanced process and semiconductor devices with shorter channel length and lower power consumption.

Referring to fig. 3, the load poles (the source 336 of the N-type fet C330 and the source 346 of the N-type fet D340) of the second fet pair are electrically connected to the control poles (the gate 354 of the N-type fet E350 and the gate 364 of the N-type fet F360) of the third fet pair, respectively, so as to form a source follower structure so as to ensure that the second output differential voltage signal applied to the control poles (the gate 354 of the N-type fet E350 and the gate 364 of the N-type fet F360) of the third fet pair matches the voltage resistance of the third fet pair (the N-type fet E350 and the N-type fet F360). As shown in fig. 3, the source 336 of the fet C330 is electrically connected to the gate 364 of the fet F360, and the source 346 of the fet D340 is electrically connected to the gate 354 of the fet E350. In this way, by providing the source follower structure between the second fet pair (the N-type fet C330 and the N-type fet D340) of the second stage signal processing circuit B302 and the third fet pair (the N-type fet E350 and the N-type fet F360) of the third stage signal processing circuit B303, the output voltage does not exceed the withstand voltage of the low-voltage device, which is helpful for implementing the decoupling design between the second stage signal processing circuit B302 and the subsequent stage circuit, and is also helpful for applying more advanced semiconductor process and shorter channel length devices on the third stage signal processing circuit B303. Considering that the source follower structure may result in a reduced gain bandwidth of the output, the reduced gain bandwidth may be detrimental to improving the signal-to-noise ratio and suppressing noise, for this purpose, a load device 382 electrically connected to the load poles of the second fet pair (the source 336 of the fet C330 and the source 346 of the fet D340) is provided with a negative impedance connection structure for providing gain bandwidth compensation for the source follower structure. In this way, the load device 382 electrically connected to the load electrode of the second fet pair (the source 336 of the N-fet C330 and the source 346 of the N-fet D340) adopts a negative impedance connection structure, so that a negative impedance is equivalently generated, that is, a negative resistance characteristic or a characteristic that a voltage is increased and a current is reduced is realized, thereby improving the gain bandwidth of the second signal processing circuit B302 and further providing gain bandwidth compensation for the source follower structure.

Referring to fig. 3, the negative impedance connection structure used by the load device 382 electrically connected to the load electrodes of the second fet pair (source 336 of fet C330 and source 346 of fet D340) is a cross-tube coupling connection structure. In some embodiments, the load device electrically connected to the load electrode of the second fet pair includes a common-source common-drain fet pair (not shown), and the respective control electrodes of the common-source common-drain fet pair are electrically connected to the load electrode of the second fet pair (the source 336 of the fet C330 and the source 346 of the fet D340) and the first output differential voltage signal B305 in accordance with the cross-tube coupling structure. Therefore, a negative resistance is equivalently generated by using the cross tube coupling connection structure, and the problem of reduced output gain bandwidth caused by the source following structure can be solved. Furthermore, a positive feedback connection mode can be adopted for the output, so that the output gain and bandwidth of the second-stage signal processing circuit B302 are effectively improved. In some embodiments, the second stage signal processing circuit B302 further comprises a positive feedback connection structure for the second output differential voltage signal B306 to boost the output gain of the second stage signal processing circuit B302, the positive feedback connection structure providing positive feedback from the first output differential voltage signal B305 to the second output differential voltage signal B306 based on the cross-pipe coupling connection structure.

Referring to fig. 3, the first stage signal processing circuit B301 further includes a first source degeneration structure based on the first fet pair (fet a310 and fet B320) for providing channel attenuation compensation. The first source degeneration structure includes a first adjustable capacitor a372 and a first adjustable resistor a374 connected in parallel between the sources of the first N-type fet pair (source 316 of N-type fet a310 and source 326 of N-type fet B320), and further includes a first current source pair (current source a376 and current source B378) electrically connected to the sources of the first N-type fet pair (source 316 of N-type fet a310 and source 326 of N-type fet B320), respectively. In this way, with the first source degeneration structure of the first stage signal processing circuit B301 based on the first N-type fet pair (N-type fet a310 and N-type fet B320), channel attenuation compensation can be provided, thereby facilitating the increase of the high-speed signal gain and the reduction of the variation range of the output common-mode voltage.

Referring to fig. 3, the third stage signal processing circuit B303 further includes a second source degeneration structure based on the third fet pair (fet E350 and fet F360) for providing channel attenuation compensation. The second source degeneration structure includes a second tunable capacitor B392 and a second tunable resistor B394 connected in parallel between the sources of the third fet pair (source 356 of fet E350 and source 366 of fet F360). The second source degeneration structure further includes a second current source pair (current source C396 and current source D398) electrically connected to the sources of the third N-fet pair (source 356 of N-fet E350 and source 366 of N-fet F360), respectively. As such, channel attenuation compensation may be provided with the second source degeneration structure based on the third N-type fet pair (fet E350 and fet F360) at the third stage signal processing circuit B303. Further, the second current source pair (current source C396 and current source D398) may be made adjustable in size, that is, the second current source pair (current source C396 and current source D398) may be adjustable current sources, such that output gain adjustment may be achieved. Thus, the linearity of the front-end circuit is improved while the signal swing is satisfied. Further, an output feedforward capacitor is provided in the third stage signal processing circuit B303, specifically, the output of the drain 362 of the N-type field effect transistor F360 affects the gate 354 of the N-type field effect transistor E350 through the output feedforward capacitor a391, and the output of the drain 352 of the N-type field effect transistor E350 affects the gate 364 of the N-type field effect transistor F360 through the output feedforward capacitor B393, so that the circuit bandwidth can be further increased by utilizing the output feedforward capacitor a391 and the output feedforward capacitor B393, which is beneficial to improving the signal-to-noise ratio and suppressing noise. In this way, the third stage signal processing circuit B303 can be powered with low voltage and use low voltage devices, which is advantageous for applying semiconductor advanced process and semiconductor devices with shorter channel length and lower power consumption, and also provides tunable gain and channel attenuation compensation while reducing area and power consumption.

In summary, the front-end circuit shown in fig. 3 uses a source follower structure to ensure that the output voltage does not exceed the withstand voltage of the low-voltage device, and uses a negative impedance connection structure to provide gain bandwidth compensation for the source follower structure, so that the front-end circuit not only can meet the requirements of data receiving and transmitting under the action of different reference voltages in a high-voltage domain, but also has the advantages of low power consumption, high bandwidth, large gain and the like; the system can provide functions of voltage conversion, attenuation compensation, swing amplification and the like of input data, and output the data into low-voltage data flow, so that a low-voltage device with wider bandwidth can be used for subsequent further processing of the data, the area and the power consumption can be optimized, and the compatibility to advanced technology is stronger; the method can be applied to an analog front-end circuit of a double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR), for example, and successfully solves the problems of high power consumption of the DDR front-end circuit, insufficient bandwidth of the DDR front-end circuit and compatibility of the DDR front-end circuit to advanced process.

Referring to fig. 1,2 and 3, the signal processing method for the front-end circuit shown in fig. 1 may be combined with the front-end circuit shown in fig. 2 and the front-end circuit shown in fig. 3. The front-end circuit shown in fig. 3 is merely exemplary, and specific circuit details and characteristics thereof may be adjusted according to actual needs, so long as the operating principle of the signal processing method for the front-end circuit shown in fig. 1 is satisfied.

In one possible embodiment, the negative impedance connection employed by the load device electrically connected to the load electrode of the second fet pair is a cross-tube coupled connection. Therefore, a negative resistance is equivalently generated by using the cross tube coupling connection structure, and the problem of reduced output gain bandwidth caused by the source following structure can be solved. In some embodiments, the load device electrically connected to the load electrode of the second fet pair includes a common source common drain N-fet pair, and the respective control electrodes of the common source common drain N-fet pair are electrically connected to the load electrode of the second fet pair and the first output differential voltage signal in accordance with the cross-tube coupling structure. Therefore, a negative resistance is equivalently generated by using the cross tube coupling connection structure, and the problem of reduced output gain bandwidth caused by the source following structure can be solved. In some embodiments, the second stage signal processing circuit further comprises a positive feedback connection structure for the second output differential voltage signal to boost an output gain of the second stage signal processing circuit, the positive feedback connection structure providing positive feedback from the first output differential voltage signal to the second output differential voltage signal based on the cross-tube coupling connection structure. Therefore, the output is connected in a positive feedback mode, and the output gain and bandwidth of the second-stage signal processing circuit are effectively improved.

In one possible implementation, the first fet pair is a first fet pair, the control and bias poles of the first fet pair are the gate and drain of the first fet pair, respectively, the first stage signal processing circuit further includes a first source degeneration structure based on the first fet pair for providing channel attenuation compensation, the first source degeneration structure including a first adjustable capacitance and a first adjustable resistance connected in parallel between the sources of the first fet pair, the first source degeneration structure further including a first current source pair electrically connected to the sources of the first fet pair, respectively. In this manner, channel attenuation compensation may be provided to facilitate increasing high-speed signal gain and reducing the range of variation of the output common-mode voltage.

In some embodiments, the third fet pair is a third fet pair, the control pole, bias pole, and load pole of the third fet pair are respectively the gate, drain, and source of the third fet pair, the third stage signal processing circuit further includes a second source degeneration structure based on the third fet pair for providing channel attenuation compensation, the second source degeneration structure includes a second adjustable capacitance and a second adjustable resistance connected in parallel between the sources of the third fet pair, the second source degeneration structure further includes a second current source pair respectively electrically connected to the sources of the third fet pair. In this way, channel attenuation compensation may be provided. In some embodiments, the second current source pair is an adjustable current source for adjusting an output gain of the third stage signal processing circuit, the third stage signal processing circuit further comprising an output feedforward capacitor. Thus, the output gain can be adjusted, and the output feedforward capacitor can be utilized to further increase the circuit bandwidth, thereby being beneficial to improving the signal-to-noise ratio and suppressing noise.

In some embodiments, the signal processing method further comprises: the method further includes increasing a magnitude of a first output current of the first current source pair included in the first source degeneration structure to decrease a magnitude of a common mode level of the first output differential voltage signal output by the first stage signal processing circuit, and increasing a magnitude of the load device electrically connected to a load electrode of the second field effect transistor pair to decrease a level of the second output differential voltage signal output by the second stage signal processing circuit such that the magnitude of the common mode level of the second output differential voltage signal input to the third stage signal processing circuit matches an output gain of the third stage signal processing circuit. In this way, with the first source degeneration structure at the first stage signal processing circuit and the second source degeneration structure at the third stage signal processing circuit, channel attenuation compensation is provided, and further, by increasing the magnitude of the first output current outputted by the first current source pair included in the first source degeneration structure, the magnitude of the common mode level of the output of the first stage signal processing circuit can be reduced, and at the same time, the size of the load device can be increased, so that it is realized that the output level of the second stage signal processing circuit is further reduced, which is helpful to provide a suitable common mode level for the third stage signal processing circuit, and the gain of the third stage signal processing circuit is ensured.

In one possible embodiment, the first fet pair and the second fet pair are both high voltage devices, and the third fet pair is a low voltage device relative to the high voltage devices. In this way, the third stage signal processing circuit can be powered with low voltage and use low voltage devices, which is advantageous for application of semiconductor advanced process and semiconductor devices with shorter channel lengths and lower power consumption, and also provides tunable gain and channel attenuation compensation while reducing area and power consumption. The characteristic that a high bandwidth can be maintained at a high voltage can be achieved in view of the overall front-end circuit.

In one possible implementation, the signal processing method is applied to an analog front-end circuit, the analog front-end circuit is used for amplifying and filtering a high-voltage domain electric signal, the first-stage signal processing circuit is a high-voltage interface circuit of the analog front-end circuit, the second-stage signal processing circuit is a voltage domain conversion circuit of the analog front-end circuit, and the third-stage signal processing circuit is a low-voltage amplifying circuit of the analog front-end circuit. The voltage withstanding of the low-voltage device of the advanced process is lower and lower, so that the signal processing method is utilized, the analog front-end circuit can fully exert the advantages of the advanced process, wherein the high-voltage interface circuit and the voltage domain conversion circuit work under the high-voltage domain specified by the protocol, and the low-voltage amplifying circuit and the rest of the analog front-end circuit can work under the low-voltage domain, so that the purpose of saving power consumption is achieved.

In some embodiments, the analog front-end circuit is configured to adapt a plurality of double rate synchronous dynamic random access memory protocols each specifying a different reference voltage, to receive an input data signal at the different reference voltages, and to provide voltage domain conversion, attenuation compensation, and swing amplification of the input data signal to output a low voltage domain output data signal relative to the different reference voltages. Thus, the problem that the DDR front-end circuit consumes large power and the problem that the DDR front-end circuit is insufficient in bandwidth and the problem that the DDR front-end circuit is compatible with advanced process are successfully solved.

In some embodiments, the low voltage domain output data signal is used in a data decoding circuit or a decision feedback equalization circuit, both of which operate at low voltages. Therefore, by utilizing the signal processing method, the analog front-end circuit can fully exert the advantages of advanced technology, wherein the high-voltage interface circuit and the voltage domain conversion circuit work under the high-voltage domain specified by the protocol, and the low-voltage amplifying circuit and the rest of the analog front-end circuit can work under the low-voltage domain, so that the purpose of saving power consumption is achieved.

The method and the device provided by the embodiment of the application are based on the same inventive concept, and because the principle of solving the problem by the method and the device is similar, the embodiment, the implementation, the example or the implementation of the method and the device can be mutually referred, and the repetition is not repeated. Embodiments of the present application also provide a system comprising a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), implement the method steps of the method embodiments described above. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the application may be implemented, in whole or in part, in software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. The present application is also intended to include such modifications and alterations if they come within the scope of the claims and the equivalents thereof.

Claims

1. A signal processing method for a front-end circuit, the signal processing method comprising:

Converting a first input differential voltage signal into a first output differential voltage signal through a first stage signal processing circuit, wherein the first stage signal processing circuit comprises a first field effect transistor pair, a control electrode and a bias electrode of the first field effect transistor pair are respectively and electrically connected with the first input differential voltage signal and the first output differential voltage signal, and the first stage signal processing circuit further comprises a current mode logic structure based on the first field effect transistor pair so as to realize matching between the first input differential voltage signal and the first output differential voltage signal on the first stage signal processing circuit;

Converting the first output differential voltage signal into a second output differential voltage signal through a second-stage signal processing circuit, wherein the second-stage signal processing circuit comprises a second field effect transistor pair, and a control electrode and a load electrode of the second field effect transistor pair are respectively and electrically connected with the first output differential voltage signal and the second output differential voltage signal;

Converting the second output differential voltage signal into a third output differential voltage signal by a third stage signal processing circuit, wherein the third stage signal processing circuit comprises a third field effect transistor pair, a control electrode and a bias electrode of the third field effect transistor pair are respectively and electrically connected with the second output differential voltage signal and the third output differential voltage signal, the first input differential voltage signal and the first output differential voltage signal are positioned in a high voltage domain, the second output differential voltage signal and the third output differential voltage signal are positioned in a low voltage domain opposite to the high voltage domain,

Wherein the load poles of the second FET pair are respectively electrically connected to the control poles of the third FET pair to form a source follower structure so as to ensure that the second output differential voltage signal applied to the control poles of the third FET pair matches the voltage resistance of the third FET pair, a load device electrically connected to the load poles of the second FET pair employs a negative impedance connection structure for providing gain bandwidth compensation for the source follower structure,

The first FET pair is a first N-type FET pair, a control electrode and a bias electrode of the first FET pair are respectively a gate electrode and a drain electrode of the first N-type FET pair, the first stage signal processing circuit further comprises a first source degeneration structure based on the first N-type FET pair for providing channel attenuation compensation, the first source degeneration structure comprises a first adjustable capacitor and a first adjustable resistor which are connected in parallel between the sources of the first N-type FET pair, the first source degeneration structure further comprises a first current source pair which is respectively and electrically connected with the sources of the first N-type FET pair,

The third field effect transistor pair is a third N-type field effect transistor pair, a control electrode, a bias electrode and a load electrode of the third field effect transistor pair are respectively a grid electrode, a drain electrode and a source electrode of the third N-type field effect transistor pair, the third-stage signal processing circuit further comprises a second source electrode degradation structure based on the third N-type field effect transistor pair and used for providing channel attenuation compensation, the second source electrode degradation structure comprises a second adjustable capacitor and a second adjustable resistor which are connected between source electrodes of the third N-type field effect transistor pair in parallel, and the second source electrode degradation structure further comprises a second current source pair which is respectively and electrically connected with the source electrodes of the third N-type field effect transistor pair.

2. The signal processing method of claim 1, wherein the negative impedance connection used by the load device electrically connected to the load electrode of the second fet pair is a cross-tube coupled connection.

3. The signal processing method of claim 2, wherein the load device electrically connected to the load electrodes of the second fet pair comprises a common source common drain fet pair, the common source common drain fet pair having their respective control electrodes electrically connected to the load electrodes of the second fet pair and the first output differential voltage signal in accordance with the cross-tube coupling structure.

4. A signal processing method according to claim 3, wherein the second stage signal processing circuit further comprises a positive feedback connection for the second output differential voltage signal to boost the output gain of the second stage signal processing circuit, the positive feedback connection providing positive feedback from the first output differential voltage signal to the second output differential voltage signal based on the cross-tube coupling connection.

5. The signal processing method of claim 1, wherein the second current source pair is an adjustable current source for adjusting an output gain of the third stage signal processing circuit, the third stage signal processing circuit further comprising an output feedforward capacitor.

6. The signal processing method according to claim 5, characterized in that the signal processing method further comprises:

the method further includes increasing a magnitude of a first output current of the first current source pair included in the first source degeneration structure to decrease a magnitude of a common mode level of the first output differential voltage signal output by the first stage signal processing circuit, and increasing a magnitude of the load device electrically connected to a load electrode of the second field effect transistor pair to decrease a level of the second output differential voltage signal output by the second stage signal processing circuit such that the magnitude of the common mode level of the second output differential voltage signal input to the third stage signal processing circuit matches an output gain of the third stage signal processing circuit.

7. The signal processing method of claim 1, wherein the first fet pair and the second fet pair are both high voltage devices and the third fet pair is a low voltage device relative to the high voltage devices.

8. The signal processing method according to claim 1, wherein the signal processing method is applied to an analog front-end circuit for amplifying and filtering a high-voltage domain electric signal, the first stage signal processing circuit is a high-voltage interface circuit of the analog front-end circuit, the second stage signal processing circuit is a voltage domain conversion circuit of the analog front-end circuit, and the third stage signal processing circuit is a low-voltage amplification circuit of the analog front-end circuit.

9. The signal processing method of claim 8, wherein the analog front-end circuit is configured to adapt a plurality of double rate synchronous dynamic random access memory protocols each defining a different reference voltage, the analog front-end circuit is configured to receive an input data signal at the different reference voltages and provide voltage domain conversion, attenuation compensation, and swing amplification of the input data signal to output a low voltage domain output data signal relative to the different reference voltages.

10. The signal processing method of claim 9, wherein the low voltage domain output data signal is used in a data decoding circuit or a decision feedback equalization circuit, both of which operate at a low voltage.

11. A front-end circuit, the front-end circuit comprising:

the first-stage signal processing circuit is used for converting a first input differential voltage signal into a first output differential voltage signal, wherein the first-stage signal processing circuit comprises a first field effect transistor pair, a control electrode and a bias electrode of the first field effect transistor pair are respectively and electrically connected with the first input differential voltage signal and the first output differential voltage signal, and the first-stage signal processing circuit further comprises a current mode logic structure based on the first field effect transistor pair so as to realize matching between the first input differential voltage signal and the first output differential voltage signal on the first-stage signal processing circuit;

The second-stage signal processing circuit is used for converting the first output differential voltage signal into a second output differential voltage signal, wherein the second-stage signal processing circuit comprises a second field effect transistor pair, and a control electrode and a load electrode of the second field effect transistor pair are respectively and electrically connected with the first output differential voltage signal and the second output differential voltage signal;

A third stage signal processing circuit for converting the second output differential voltage signal into a third output differential voltage signal, wherein the third stage signal processing circuit includes a third fet pair, a control electrode and a bias electrode of the third fet pair are respectively electrically connected to the second output differential voltage signal and the third output differential voltage signal, the first input differential voltage signal and the first output differential voltage signal are located in a high voltage domain, the second output differential voltage signal and the third output differential voltage signal are located in a low voltage domain opposite to the high voltage domain,

And

12. The front-end circuit of claim 11, wherein the negative impedance connection used by the load device electrically connected to the load electrode of the second fet pair is a cross-tube coupling connection, the load device electrically connected to the load electrode of the second fet pair comprises a common-source common-drain N-fet pair, and the respective control electrodes of the common-source common-drain N-fet pair are electrically connected to the load electrode of the second fet pair and the first output differential voltage signal in accordance with the cross-tube coupling connection.