CN104539373A - High-speed CMOS monolithic integration light receiver front end of cross coupling structure - Google Patents

Abstract

The invention discloses a high-speed CMOS monolithic integration light receiver front end of a cross coupling structure. The high-speed CMOS monolithic integration light receiver front end comprises a photoelectric detector of a completely-symmetric structure, a trans-impedance amplifier of a difference structure, a direct current excursion eliminating unit, a three-stage sequence cascaded difference limiting amplifier and an output buffer stage; the trans-impedance amplifier of the difference structure is used for converting current signals output by the photoelectric detector into voltage signals and conducting preliminary amplification; the direct current excursion eliminating unit is used for eliminating direct current excursion led in by non-balanced signals at the input end of the trans-impedance amplifier and enables common mode levels at the output end of the trans-impedance amplifier to be coincident; the three-stage sequence cascaded difference limiting amplifier is used for amplifying the voltage signals output by the trans-impedance amplifier to be at the voltage level needed by a digital processing unit. Through the adoption of the cross coupling structure, the noise in-phase counteraction technology and the parallel type active inductor design, a high-speed and high-sensitivity standard CMOS monolithic integration light receiver can be achieved.

Description

The high-speed cmos monolithic integrated photoreceiver front-end circuit of cross coupling structure

Technical field

The present invention relates to optical fiber telecommunications system and light network field, particularly relate to a kind of high-speed cmos monolithic integrated photoreceiver front-end circuit of cross coupling structure.

Background technology

Along with communication and the development of multimedia technology, the demand of people to data message continues to increase.There is due to optical fiber communication the advantages such as high speed, Large Copacity, therefore be used widely in main line network.But for user terminal, the cost by photoelectricity integrated chip limits, fiber-to-the-home " last one kilometer " is difficult to continue to advance.Therefore, the study hotspot that low cost, high performance photoelectricity integrated chip become integrated opto-electronic field is developed.

Optical fiber telecommunications system usually by optical sender, fiber channel and optical receiver three part form.The Main Function of optical receiver is that the faint optical signal that Optical Fiber Transmission is come is changed into the signal of telecommunication, and through processes such as amplification, equilibrium, timing and judgements, is reduced into the data message consistent with information source of making a start.Photoreceiver front-end is as the important component part of complete optical receiver, and its performance index directly decide the transmission quality of the even whole communication system of optical receiver.In order to unfavorable factors such as the cost overcoming existing hybrid integrated or hybrid package optical receiver is high, poor reliability, scientific research personnel has carried out large quantifier elimination to the monolithic integrated photoreceiver of silica-based standard CMOS process.

At present, the monolithic photoreceiver front-end circuit based on standard CMOS can be divided into two types: high bandwidth optical receiver and low noise optical receiver.In high bandwidth front-end circuit, general dependence reduces input impedance and adopts bandwidth compensation technology to expand bandwidth.Reduce the mode of input impedance usually to adopt to regulate the transistor size of input point or introduce feedback arrangement and realize, but this with sacrifice circuit noiseproof feature for cost.Low noise front-end circuit often adopts high input impedance to realize, and obviously this also can sacrifice bandwidth.In addition, also have the example adopting noise cancellation structure or introduce equalizer, but these measures still can not solve trading off between bandwidth and noise well.

Summary of the invention

The invention provides a kind of high-speed cmos monolithic integrated photoreceiver front-end circuit of cross coupling structure, the present invention is based on the technology such as cross-couplings, noise in-phase counteracting and parallel active inductance, overcome the deficiencies in the prior art, develop the monolithic integrated photoreceiver of low cost, high-performance, feature richness, described below:

A high-speed cmos monolithic integrated photoreceiver front-end circuit for cross coupling structure, comprising: the photodetector of structure full symmetric, the trans-impedance amplifier of differential configuration, direct current offset eliminate unit, the differential limiting amplifier of three grades of concatenated in order, output buffer stage;

Wherein, a detector is used for converting the faint optical signal of optical fiber input to electric impulse signal, and another detector, for maintaining the load balance of Differential input circuit, increases receiver bandwidth;

The trans-impedance amplifier of described differential configuration, is converted into voltage signal for the current signal exported by photodetector, and tentatively amplifies;

Described direct current offset eliminates unit, for eliminating the direct current offset that trans-impedance amplifier input non-equilibrium signal is introduced, makes trans-impedance amplifier difference output end common mode electrical level consistent;

The differential limiting amplifier of described three grades of concatenated in order, the voltage signal for being exported by trans-impedance amplifier is amplified to digital processing element required voltage level;

Described output buffer stage, the differential voltage signal for being exported by differential limiting amplifier converts the voltage signal of Single-end output to, and provides driving force.

The trans-impedance amplifier of described differential configuration is:

On the basis of traditional adjustment type cascode amplifier structure, change single-stage common-source stage circuit into two-stage common-source stage circuits cascading, and use cross coupling structure to build the trans-impedance amplifier of described differential configuration.

Two-stage common-source stage circuit is respectively first order common-source stage circuit and second level common-source stage circuit;

At output and the butt coupling electric capacity between corresponding trans-impedance amplifier output of described first order common-source stage circuit.

The beneficial effect of technical scheme provided by the invention is: compared with existing standard CMOS monolithic integrated photoreceiver, tool of the present invention has the following advantages:

1, in trans-impedance amplifier circuit, change the common-source stage structure of adjustment type cascade (RGC) structure into two-stage cascade, improve the gain of inverting amplifier between RGC circuit common gate metal-oxide-semiconductor grid and source electrode, increase the equivalent transconductance of common gate metal-oxide-semiconductor, thus input impedance is reduced, increase output impedance, expanded the bandwidth of trans-impedance amplifier simultaneously, improve circuit repercussion isolation and strengthen the self-regulating function of RGC structure.

2, adopt noise in-phase cancellation technology, eliminate the partial noise of first order common-source stage circuit, thus effectively reduce circuit overall noise, improve the sensitivity of optical receiver.

3, adopt parallel active inductance designing technique, active electrical of breaking the normal procedure inductance value, to the restriction at zero point, achieves resistance constant, the function that zero point is adjustable, therefore, can obtain best frequency compensation effect.

4, use direct current offset to eliminate unit, ensure that the difference output end common mode electrical level of trans-impedance amplifier is consistent, limiting amplifier is only three grades, restrained effectively the decline of integrated circuit bandwidth.

In sum, by cross coupling structure, noise in-phase cancellation technology and the parallel active inductance design adopting the present invention to propose, high speed, highly sensitive standard CMOS monolithic integrated photoreceiver can be realized.

Accompanying drawing explanation

Fig. 1 gives the structured flowchart of photoreceiver front-end circuit designed by the present invention;

Fig. 2 gives the circuit theory diagrams of the RGC trans-impedance amplifier of difference cross coupling structure;

Fig. 3 gives schematic diagram (a) and the equivalent circuit diagram (b) of traditional collapsible active inductance;

Fig. 4 gives the circuit theory diagrams that direct current offset eliminates unit (DC Offset Dismiss Unit);

Fig. 5 is limiting amplifier (LA) circuit theory diagrams;

Fig. 6 exports buffer stage (Buffer) circuit theory diagrams.

1: the first photodetector; 2: the second photodetectors;

3: the trans-impedance amplifier of difference cross coupling structure; 4: direct current offset eliminates unit;

5: differential limiting amplifier; 6: export buffer stage.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below embodiment of the present invention is described further in detail.

See Fig. 1, the high-speed cmos monolithic integrated photoreceiver front-end circuit of the cross coupling structure that the present invention proposes comprises:

The photodetector of two structure full symmetrics, wherein, the first photodetector 1 converts the faint optical signal that optical fiber inputs to electric impulse signal, and the second photodetector 2, for maintaining the load balance of Differential input circuit, increases receiver bandwidth;

The trans-impedance amplifier 3 of a difference cross coupling structure, its effect is that the current signal that photodetector (first photodetector 1 and the second photodetector 2) exports is converted into voltage signal, and tentatively amplifies;

A direct current offset eliminates unit 4, and its effect is the direct current offset eliminating the introducing of trans-impedance amplifier 3 input non-equilibrium signal, makes trans-impedance amplifier 3 difference output end common mode electrical level consistent;

The differential limiting amplifier 5 of three grades of concatenated in order, its effect is that the voltage signal that trans-impedance amplifier 3 exports is amplified to digital processing element required voltage level;

One exports buffer stage 6, and its effect is the voltage signal differential voltage signal that limiting amplifier 6 exports being converted to Single-end output, and provides driving force.

See Fig. 2, give a preferred embodiment of adjustment type cascade (RGC) trans-impedance amplifier of difference cross coupling structure.This structural circuit mainly comprises common grid level amplifying circuit and common-source stage branch road two parts, and its effect is amplified, is converted to voltage signal by the output current signal of photodetector (first photodetector 1 and the second photodetector 2).

The input In of trans-impedance amplifier 3 _2aconnect the anode of the first photodetector 1, another input In _2bconnect the anode of the second photodetector 2.For expanding the bandwidth of adjustment type cascade (RGC) structure trans-impedance amplifier, the simultaneously equivalent input noise current of not increasing circuit, trans-impedance amplifier provided by the invention, on the basis of traditional RGC structure, introduces the second common-source stage, and adopts cross-couplings to connect.Wherein, transistor M _21aand M _25aand resistance R _24aand R _25aform the Zuo Banzhi grid level amplifying circuit altogether of difference RGC structure; Transistor M _21band M _25band resistance R _24band R _25bform right half and be total to grid level amplifying circuit.Transistor M _22awith resistance R _22aform the first common-source stage of left half RGC structure, transistor M _23awith resistance R _23aform the second common-source stage; Transistor M _22bwith resistance R _22bform the first common-source stage of right half RGC structure, transistor M _23bwith resistance R _23bform the second common-source stage.Half, the left side common-source stage circuit output point A and transistor M of difference channel _21bgrid be connected, half, the right side common-source stage circuit output point B and transistor M of difference channel _21agrid be connected.Transistor M _24abe the tail current source of the first common-source stage amplifying circuit differential pair, its source ground, grid meets bias voltage V _b2; Transistor M _24bthe tail current source of the second common-source stage amplifying circuit differential pair, its source ground, grid and transistor M _24agrid be connected, and meet bias voltage V _b2.Electric capacity C _2maand C _2mbas negative Miller capacitance, wherein, electric capacity C _2mabe connected on input In _2awith transistor M _23adrain electrode between, electric capacity C _2mbbe connected on input In _2bwith transistor M _23bdrain electrode between.Electric capacity C _2naand C _2nbcoupling capacitance, wherein, electric capacity C _2nabe connected on M _21adrain electrode and M _22adrain electrode between, electric capacity C _2nbbe connected on M _21bdrain electrode and M _22bdrain electrode between.Transistor M _25a, resistance R _24aand R _25aform the active inductance in parallel that half, a left side is total to grid level amplifying circuit, and transistor M _25b, resistance R _24band R _25bthen form the active inductance in parallel that half, the right side is total to grid level amplifying circuit.The left and right branch road full symmetric of adjustment type cascodes trans-impedance amplifier, is namely total to grid to pipe M _21aand M _21bsize and layout shape, the first common source is to pipe M _22aand M _22bsize and layout shape, the second common source is to pipe M _23aand M _23bsize and layout shape, tail current source M _24aand M _24bsize and layout shape, load pipe M _25aand M _25bsize and layout shape, resistance is to R _21awith R _21b, resistance is to R _22awith R _22b, resistance is to R _23awith R _23b, resistance is to R _24awith R _24band resistance is to R _25awith R _25bsize all identical with layout shape, and domain arrangement on full symmetric.

The operation principle of this trans-impedance amplifier 3 is as follows:

The photoelectric current that first photodetector 1 exports is from input In _2ainput trans-impedance amplifier, half common-source stage circuit (transistor M through a left side for difference channel _22a, resistance R _22awith transistor M _23a, resistance R _23aform the first and second common-source stages of RGC structure respectively) homophase amplification, at output node A, photo-signal is input to the common gate device M of right half of difference channel _21bgrid.In like manner, the dark current of the second photodetector 2 output is from input In _2binput trans-impedance amplifier, half common-source stage circuit (M through the right side of difference channel _22b, R _22band M _23b, R _23bform the first and second common-source stages of RGC structure respectively) homophase amplification, at output node B, dark current signals is input to the common gate device M of left half of difference channel _21agrid.Due to the signal inversion of half about difference channel, this is just equivalent to, and input signal is anti-phase is amplified to difference channel grid level transistor M altogether _21aand M _21bgrid on, thus improve transistor M _21awith transistor M _21bequivalent transconductance.Grid level transistor M altogether _21aand M _21bequivalent transconductance G _mfor:

G _m＝g _m21(1+g _m22R ₂₂g _m23R ₂₃) (1)

In formula, g _m21, g _m22and g _m23represent transistor M respectively ₂₁, M ₂₂and M ₂₃small-signal transconductance.R ₂₂and R ₂₃represent resistance R respectively ₂₂and R ₂₃resistance.Compare traditional RGC circuit, altogether the equivalent transconductance G of grid level transistor _mlarger, thus trans-impedance amplifier circuit designed by the present invention has lower input impedance and the bandwidth of Geng Gao.

According to Miller effect, the electric capacity being connected on inverting amplifier two ends can be equivalent to the positive electric capacity amplified of input.C _2maand C _2mbit is connected on the two ends of in-phase amplifier respectively, so can be equivalent to a negative capacitance at the input of two-stage common-source stage amplifying circuit.Therefore, C _2maand C _2mbinput (In can be offset to a certain extent _2aand In _2b) electric capacity, promote further the bandwidth of trans-impedance amplifier.

The equivalent input noise current of trans-impedance amplifier for:

$I_{n,\mathrm{in}}^2=I_{n,R21}^2+I_{n,R1}^2+\frac{I_{n,R22}^2+I_{n,M22}^2}{g_{m22}^2{R}_{22}^2}+\frac{I_{n,R23}^2+I_{n,M23}^2}{g_{m22}^2{R}_{22}^2{g}_{m23}^2{R}_{23}^2}---\left(2\right)$

In formula, with represent R respectively ₂₁, parallel active inductance equiva lent impedance R ₁, R ₂₂, R ₂₃, M ₂₂and M ₂₃the noise current produced.Wherein, (2) Section 4 in formula is the noise that the second common-source stage amplifying circuit produces, although the ratio that this noise accounts for overall noise is very little, but the object of circuit designed by the present invention is exactly reduce circuit noise as much as possible, therefore, noise in-phase cancellation technology is adopted the Section 4 in (2) formula to be balanced out in design.Coupling capacitance C _2naand C _2nbthe partial noise of the first common source amplifying circuit can be offset, thus reduce circuit overall noise.M _22aand R _22anoise be amplified to the output of trans-impedance amplifier from both direction: a direction is that noise signal is through electric capacity C _2nabe coupled to common gate transistor M _21adrain terminal; Other direction is that noise signal is through transistor M _23aand the transistor M of right half of difference channel _21bbe amplified to the output that half, the right side is total to grid level amplifying circuit.In like manner, M _22band R _22bnoise be amplified to two outputs of Zuo Banzhi altogether grid level amplifying circuit in an identical manner.Because two noise signals are produced by identical device, so can linear superposition, lay respectively at two outputs of difference channel because of the two homophase again, therefore, these two noise signals be done to differ from and are disappeared mutually.Final noise current equals initial noisc electric current and deducts coupled noise equivalent inpnt electric current.

During low frequency, coupling capacitance C _2nimpedance very large, input signal can not pass through C _2ntransmit, and during high frequency, coupling capacitance C _2nconducting, becomes the path of Signal transmissions.Due to the present invention pay close attention to be high frequency time equivalent input noise current, therefore, setting C _2ncapacitance at f _-3dBplace meets the following conditions:

$\frac{(I_{n,R22}^2+I_{n,M22}^2)R_{22}^2}{{(R_1+1/\left({\mathrm{sC}}_{2n}\right))}^2}=\frac{(I_{n,R23}^2+I_{n,M23}^2)}{g_{m22}^2{R}_{22}^2{g}_{m23}^2{R}_{23}^2}---\left(3\right)$

Namely $C_{2n}=\left|\frac{j}{{2\mathrm{\πf}}_{-3\mathrm{dB}}}(\frac{I_{n,2}{R}_{22}A}{I_{n,3}}-R_1)\right|---\left(4\right)$

Wherein, f _-3dBbe trans-impedance amplifier-three dB bandwidth, j is imaginary unit, R ₁the equiva lent impedance of parallel active inductance, A=g _m22r ₂₂g _m23r ₂₃, $I_{n,2}=\sqrt{I_{n,R22}^2+I_{n,M22}^2},I_{n,3}=\sqrt{I_{n,R23}^2+I_{n,M23}^2}.$

When coupling capacitance gets above-mentioned optimal value, final equivalent inpnt electric current is decreased to:

$I_{n,\mathrm{in}}^2=I_{n,R21}^2+I_{n,R1}^2+\frac{I_{n,R22}^2+I_{n,M22}^2}{g_{m22}^2{R}_{22}^2}---\left(5\right)$

Although introduce coupling capacitance C _2ncan circuit noise be reduced, but also can reduce transistor M ₂₁and M ₂₂drain terminal limit.Noise is through C _2nwhile disappearing mutually, the input signal that the first common-source stage amplifies is also through C _2nbe coupled to output, disappear mutually with original output signal, output signal V _outbecome

$V_{\mathrm{out}}\≈I_{\mathrm{in}}{R}_1-I_{\mathrm{in}}{R}_{\mathrm{in}}{g}_{m22}{R}_{22}\frac{R_1{C}_{2n}s}{1+R_1{C}_{2n}s}=I_{\mathrm{in}}{R}_1\frac{1+(R_1-R_{\mathrm{in}}{g}_{m22}{R}_{22})C_{n}s}{1+R_1{C}_{2n}s}---\left(6\right)$

Wherein, R _infor input impedance.

As can be seen here, output signal can zero, the form of limit shows.Coupling capacitance C _2nproduce a pole and zero respectively, and pole value is less than value at zero point.The transistor M of this limit and reduction ₂₁with M ₂₂drain terminal limit all can worsen the bandwidth characteristic of trans-impedance amplifier.In order to compensate the reduction of bandwidth, in trans-impedance amplifier, introduce parallel active inductance peaking technique.

In order to the advantage of outstanding parallel active inductance peaking technique, first introduce classical collapsible active inductance, see Fig. 3.Wherein, Fig. 3 (a) is the schematic diagram of collapsible active inductance, and figure (b) is its equivalent circuit diagram.The equiva lent impedance of collapsible active inductance is

$Z_{\mathrm{in}}=\frac{1+{\mathrm{sC}}_{31b}{R}_{31b}}{g_{m31}(1+s{C}_{31b}/g_{m31})}---\left(7\right)$

Collapsible active inductance introduce in circuit one zero point z _iwith limit p _i, usual z _ibe less than p _i, and near dominant pole, so just improve three dB bandwidth f _-3dB.For making active inductance the optimal compensation C _2nthe bandwidth reduction introduced, needs appropriate increase z at zero point _i.This is by regulating transistor M ₃₁grid source electric capacity C ₃₁or load resistance R ₃₁realize.Due to load pipe M ₃₁size determine the gain of trans-impedance amplifier, thus can not at will change, i.e. grid source electric capacity C ₃₁can not free adjustment.If by reducing R ₃₁promote z at zero point _i, then z can be caused _iwith p _iclose to even overlapping, active inductance frequency acquisition and tracking is finally caused to lose efficacy.The effective way addressed this problem is on the basis of collapsible active inductance, then a resistance in parallel, forms the parallel active inductance as shown in Fig. 2 dotted line frame.Wherein, the resistance of parallel resistance is equal with the former load resistance of collapsible active inductance, namely

$\frac{R_{24}}{1+g_{m25}{R}_{24}}=\frac{1}{g_m}---\left(8\right)$

Wherein, g _m25and g _mrepresent transistor M respectively ₂₅with transistor M in collapsible active inductance ₃₁mutual conductance.Parallel resistance R ₂₄after, the equiva lent impedance of active inductance is:

$Z_{\mathrm{in}}=\frac{R_{24}(1+{\mathrm{sC}}_{31}{R}_{25})}{(R_{24}{g}_{m25}+1)(1+\frac{{\mathrm{sC}}_{31}}{R_{24}{g}_{m25}+1}(R_{24}+R_{25}))}---\left(9\right)$

Zero point z _iwith limit p _iratio be

$\frac{z_i}{p_i}=\frac{R_{24}/R_{25}+1}{R_{24}{g}_{m25}+1}---\left(10\right)$

R is had in active inductance ₂₅>g _m25, so z at zero point can be ensured _ibe less than limit p _i, can not overlap between the two.Due to transistor M in parallel active inductance ₂₅size than transistor M in collapsible active inductance ₃₁size less, there is lower grid source electric capacity, thus zero point z _iwith limit p _ibe placed in high frequency.By regulating resistance R ₂₅, make the z at zero point of parallel active inductance _imove closer to the dominant pole of trans-impedance amplifier, to reach the optimal compensation effect.Although the z at zero point of parallel active inductance _iwith limit p _iclose to some extent, but at adjustment R ₂₅time zero point z _idecrease than limit p _idecrease larger, therefore the close of the two can be made up.

Theory analysis shows, the noise current of collapsible active inductance:

$I_{n1}^2=4{\mathrm{kT\γg}}_{m31}---\left(11\right)$

Wherein, γ represents channel noise coefficient.The noise current of parallel active inductance:

$I_{n2}^2={4\mathrm{kT\γg}}_{m25}+\frac{4\mathrm{kT}}{R_{24}}={4\mathrm{kT\γg}}_m+\frac{4\mathrm{kT}}{R_{24}}(1-\mathrm{\γ})---\left(12\right)$

For short channel device, γ >1.So namely the traditional collapsible active inductance of the noise ratio of parallel active inductance is lower.

Due to the first photodetector 1 detection fiber input optical signal, and produce corresponding photoelectric current, and the second photodetector is dummy detector, its output only has dark current, so easily cause difference trans-impedance amplifier circuit to occur DC maladjustment.For this reason, the present invention inserts a direct current offset and eliminates unit 4 (DC OffsetDismiss Unit) between trans-impedance amplifier and limiting amplifier, as shown in Figure 4.Resistance R _41aa termination supply voltage VDD, another termination transistor M _41adrain electrode, and with crystal M _42bdrain electrode be connected, transistor M _41agrid meet input In _4a, source electrode and transistor M _42a, M _42band M _41bsource electrode be connected, and with tail current source M ₄₃drain electrode be connected, tail current source M ₄₃source ground, grid meets bias voltage V _b4.Transistor M _42adrain electrode connecting resistance R _41band transistor M _41bdrain electrode, grid connecting resistance R _4awith electric capacity C _4aone end, electric capacity C _4aother end ground connection, resistance R _4aanother termination input In _4a.Resistance R _41ba termination supply voltage VDD, another termination transistor M _41bdrain electrode, and with crystal M _42adrain electrode be connected, transistor M _41bgrid meet input In _4b, transistor M _42bdrain electrode connecting resistance R _41aand transistor M _41adrain electrode, grid connecting resistance R _4bwith electric capacity C _4bone end, electric capacity C _4bother end ground connection, resistance R _4banother termination input In _4b.

The operation principle that direct current offset eliminates unit 4 is as follows: input In _4asignal one tunnel control transistor M _41asource and drain direct current, another road through low pass filter (by resistance R _4awith electric capacity C _4aforming) after filtering, the DC component of input signal controls transistor M _42asource and drain direct current, so the DC level of left branch road output is by transistor M _41aand M _42asource and drain direct current sum determine.In like manner, the DC level of right branch road output is by transistor M _41band M _42bsource and drain direct current sum determine.Therefore, no matter input In _4aand In _4bdC level how, the DC level of two outputs is all equal, thus achieves direct current offset and eliminate function.

Differential limiting amplifier 5 of the present invention adopts thtee-stage shiplock structure, and every grade is all structure identical difference common-source stage amplifier.Fig. 5 gives the circuit structure schematic diagram of single-stage limiting amplifier.Single-stage limiting amplifier is by NMOS tube M _51a, M _51b, M _52a, M _52band M ₅₃, and resistance R _5aand R _5bcomposition.Wherein, M ₅₃for tail current source, for limiting amplifier provides bias current; NMOS tube M _51aand M _51bfor Differential Input is to pipe; NMOS tube M _52aand M _52band resistance R _5aand R _5bform collapsible active inductance, to expand the bandwidth of limiting amplifier.These NMOS tube of mutually matching are identical with the size and dimension of resistance, domain structure are also full symmetrics.

See Fig. 6, difference turns single-ended output buffer stage by NMOS offset M ₆₄, Differential Input is to pipe M _61aand M _61b, NMOS load pipe M _62aand M _62b, PMOS transistor M _63aand M _63band resistance R _6aand R _6bformed.Differential Input is to pipe M _61aand M _61bsize and dimension, NMOS load pipe M _62aand M _62bsize and dimension, PMOS transistor M _63aand M _63bsize and dimension and resistance R _6aand R _6bsize and dimension identical, domain arrangement on full symmetric.Wherein, NMOS offset M ₆₄effect be to provide bias current; Transistor M _62awith resistance R _6aand transistor M _62bwith resistance R _6bform two collapsible active inductances respectively; PMOS load pipe M _63agrid and M _63bgrid be shorted together, and with transistor M _61adrain electrode be connected, form a both-end and turn single-ended structure, realize Single-end output; NMOS load pipe M _62aand M _62bdrain electrode, PMOS load pipe M _63aand M _63bsource class and resistance R _6aand R _6bone end be all connected with VDD, resistance R _6aand R _6bthe other end respectively with transistor M _62aand M _62bgrid be connected.

The embodiment of the present invention is to the model of each device except doing specified otherwise, and the model of other devices does not limit, as long as can complete the device of above-mentioned functions.

It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (5)

1. the high-speed cmos monolithic integrated photoreceiver front-end circuit of a cross coupling structure, it is characterized in that, comprising: the photodetector of structure full symmetric, the trans-impedance amplifier of differential configuration, direct current offset eliminate unit, the differential limiting amplifier of three grades of concatenated in order, output buffer stage;

Wherein, a detector is used for converting the faint optical signal of optical fiber input to electric impulse signal, and another detector, for maintaining the load balance of Differential input circuit, increases receiver bandwidth;

The trans-impedance amplifier of described differential configuration, is converted into voltage signal for the current signal exported by photodetector, and tentatively amplifies;

Described direct current offset eliminates unit, for eliminating the direct current offset that trans-impedance amplifier input non-equilibrium signal is introduced, makes trans-impedance amplifier difference output end common mode electrical level consistent;

The differential limiting amplifier of described three grades of concatenated in order, the voltage signal for being exported by trans-impedance amplifier is amplified to digital processing element required voltage level;

Described output buffer stage, the differential voltage signal for being exported by differential limiting amplifier converts the voltage signal of Single-end output to, and provides driving force.

2. the high-speed cmos monolithic integrated photoreceiver front-end circuit of a kind of cross coupling structure according to claim 1, is characterized in that, the trans-impedance amplifier of described differential configuration is:

On the basis of traditional adjustment type cascode amplifier structure, change single-stage common-source stage circuit into two-stage common-source stage circuits cascading, and use cross coupling structure to build the trans-impedance amplifier of described differential configuration.

3. the high-speed cmos monolithic integrated photoreceiver front-end circuit of a kind of cross coupling structure according to claim 2, is characterized in that, two-stage common-source stage circuit is respectively first order common-source circuits and second level common-source circuits;

At output and the butt coupling electric capacity between corresponding trans-impedance amplifier output of described first order common-source stage circuit.

4. the high-speed cmos monolithic integrated photoreceiver front-end circuit of a kind of cross coupling structure according to claim 1, it is characterized in that, described output buffer stage uses Double-end-to-singlecircuit circuit structure, and the metal-oxide-semiconductor that load is connected by diode is in parallel with current mirror to be formed.

5. the high-speed cmos monolithic integrated photoreceiver front-end circuit of a kind of cross coupling structure according to claim 1, is characterized in that, described output buffer stage adopts active inductance structure.