CN118041074A - Buck converter control circuit and adaptive voltage positioning implementation method thereof - Google Patents
Buck converter control circuit and adaptive voltage positioning implementation method thereof Download PDFInfo
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Abstract
The invention provides a Buck converter control circuit and a self-adaptive voltage positioning implementation method thereof, wherein the circuit structure comprises a self-adaptive on-time generating circuit based on PLL control, a comparator, an error amplifier, an inductance current sampling circuit and a self-adaptive voltage positioning circuit of a logic control driving circuit, and the self-adaptive on-time generating circuit is a control circuit which is suitable for the Buck converter to realize quick transient response and supports an AVP function, determines the on-time, compares an inductance current sampling signal Vs with an output V ITH of the error amplifier to determine the off-time, thereby controlling a switch to be conducted and regulating the output voltage. The control circuit provided by the invention can adaptively control the on-time and realize the function of self-adaptive voltage positioning, thereby greatly enhancing the transient response speed of the system, realizing the rapid transient response speed under various different conditions and reducing the requirements on off-chip elements.
Description
Technical Field
The invention relates to the technical field of electricity, in particular to a Buck converter control circuit and a self-adaptive voltage positioning implementation method thereof.
Background
With the development of moore's law, the working frequency of the processor is higher and higher nowadays, the working current is also larger and the current change slew rate is larger and larger. The ever-evolving processor performance places ever-increasing demands on the transient response performance of power management chips.
COT control is widely applied because of the characteristics of high transient response speed and high light load efficiency, but the fixed on time of COT control can not perform rapid transient response when load rising jump occurs at a low duty cycle and load falling occurs at a high duty cycle.
In order to meet the requirements of processors for power management chips, adaptive Voltage Positioning (AVP) techniques have evolved. The basic idea is to control the output voltage level such that the value at full load is slightly above the minimum value and the light load is slightly below the maximum value, as shown in fig. 1. AVP technology allows for smaller output capacitance and reduces output power at full load, facilitating heat dissipation design.
The BUCK circuit is a DC-DC converter, converts a direct current voltage into a high-frequency power supply through an oscillating circuit, and outputs the required direct current voltage through a pulse transformer and a rectifying and filtering loop, and is a single-tube non-isolated direct current converter with an output voltage smaller than an input voltage.
The COT-controlled BUCK circuit is combined with the AVP technology, so that output voltage change during output load jump can be reduced, and system stability is improved, but at present, the situation of low transient response speed possibly exists, and therefore, an adaptive voltage positioning control circuit and a control method capable of further improving the transient response speed are needed.
Disclosure of Invention
The invention provides a Buck converter control circuit and a self-adaptive voltage positioning implementation method thereof, aiming at solving the problem of transient response speed of self-adaptive voltage positioning, wherein the circuit structure comprises a self-adaptive conduction time generation circuit based on PLL control, a comparator, an error amplifier, an inductance current sampling circuit and a logic control driving circuit. The control circuit provided by the invention can adaptively control the on-time and realize the function of self-adaptive voltage positioning, thereby greatly enhancing the transient response speed of the system, realizing the rapid transient response speed under various different conditions and reducing the requirements on off-chip elements.
The invention provides a Buck converter control circuit, which comprises a Buck converter circuit, an error amplifier EA, an AVP control circuit, an inductive current sampling circuit, a comparator CMP1, an RS trigger, a logic driving circuit, a self-adaptive on-time generation circuit and a logic driving circuit, wherein the feedback voltage V FB of the Buck converter circuit is compared with a reference voltage V REF and the output voltage V ITH, the AVP control circuit is connected with the output end of the error amplifier EA and is used for adjusting the voltage V ITH, the inductive current sampling circuit is connected with one end of R DCR of the Buck converter circuit and is used for sampling inductive current I L and generating current sampling voltage V S in a specified proportion, the comparator CMP1 is used for inputting the current sampling voltage V S as a negative phase and comparing the voltage V ITH input by a positive phase, the S end of the RS trigger is connected with the output end of the comparator CMP1, the self-adaptive on-time generation circuit is connected with the Q end and the R end of the RS trigger, the logic driving circuit is connected with the switching tube S 1、S2 of the Buck converter circuit, the Buck converter circuit generates output voltage V OUT and load current I LOAD, and the RS trigger outputs a switching tube control signal D to the self-adaptive on-time generation circuit and the logic driving circuit;
The self-adaptive on-time generation circuit based on the PLL control detects the frequency phase difference between the switching tube control signal D and the clock signal f clk so as to generate different on-times; the AVP control circuit provides an additional current path to the output node ITH of the error amplifier EA such that the corresponding amount of V FB voltage change increases as the ITH node voltage changes for adaptive voltage positioning.
The invention relates to a Buck converter control circuit, which is characterized in that as a preferable mode, the self-adaptive on-time generation circuit based on PLL control comprises a phase frequency detector charge pump PFD/CP for detecting the frequency phase difference of a switching tube control signal D and a clock signal f clk, a low-pass filter LPF connected with the output end of the phase frequency detector charge pump PFD/CP, a transconductance amplifier OTA with a positive input end connected with the low-pass filter LPF and an inverse input end connected with a fixed voltage V B, a fixed charging current I r externally input, a capacitor C r connected with the output end of the transconductance amplifier OTA and the fixed charging current I r, and a comparator CMP2 with a positive input end connected with the capacitor C r;
One input end of a charge pump PFD/CP of the phase frequency detector is connected with a Q end of an RS trigger, a switching tube control signal D is a duty ratio signal, the other end of a capacitor C r is grounded, a capacitor C r outputs a ramp voltage signal S r, an inverting input of a comparator CMP2 is a fixed voltage V TH, an output end of the comparator CMP2 is connected with an R end of the RS trigger, and the Q end of the RS trigger outputs the duty ratio signal D;
The NMOS transistor switch is connected to two ends of the capacitor C r, the NMOS transistor switch inputs an inverted signal D of a switching transistor control signal D, and the NMOS transistor switch clears the voltage of the capacitor C r in each period so that the ramp voltage signal Sr rises from zero in each period;
The sampling coefficient of the inductive current sampling circuit is R i, the sampling voltage is V S, and the inductive current sampling circuit is connected with the inverting output end of the comparator CMP 1.
The invention relates to a Buck converter control circuit, which comprises an inductor L and a resistor R DCR which are connected, a resistor R ESR, a resistor R L and a resistor R F1 which are all connected in parallel with the other end of the resistor R DCR, a capacitor C OUT connected with the other end of the resistor R ESR, a resistor R F2 connected with the other end of the resistor R F1 and a switch tube S 1、S2 connected with the other end of the inductor L;
The source electrode input voltage V in and the drain electrode of the switch tube S 1 are connected with the inductor L, the grid electrode of the switch tube S 2 is connected with the logic driving circuit, the source electrode of the switch tube S 2 is grounded, the drain electrode of the switch tube S 2 is connected with the inductor L, the grid electrode of the switch tube S is connected with the logic driving circuit, the other ends of the capacitor C OUT, the resistor R L and the resistor R F2 are grounded, a feedback voltage V FB is output between the resistor R F1 and the resistor R F2, the feedback voltage V FB is connected with the inverting input end of the error amplifier EA, and the resistor R L outputs the voltage V OUT and the load current I LOAD;
The switching tube S 1 is a PMOS tube, and the switching tube S 2 is an NMOS tube.
The invention relates to a Buck converter control circuit, which is characterized in that as a preferable mode, an AVP control circuit comprises a resistor R 1 with one end connected with the output end of an error amplifier EA and the other end grounded, and a resistor R 2 with one end connected with the output end of the error amplifier EA and the other end input voltage INTV CC;
The voltage INTV CC is a power supply voltage or a fixed voltage.
The invention relates to a Buck converter control circuit, which is characterized in that as a preferable mode, an AVP control circuit comprises a resistor R 1 with one end connected with the output end of an error amplifier EA and the other end grounded, and a direct current source I b with one end connected with the output end of the error amplifier EA; the direct current source I b is connected to the voltage INTV CC.
The invention relates to a Buck converter control circuit, which is characterized in that as a preferable mode, an AVP control circuit comprises a direct current source I b, one end of which is connected with the output end of an error amplifier EA, the other end of which is grounded, and a resistor R 2, one end of which is connected with the output end of the error amplifier EA, and the other end of which is input with voltage INTV CC; the voltage INTV CC is a power supply voltage or a fixed voltage.
The invention provides a self-adaptive voltage positioning realization method of a Buck converter control circuit, when a load current I LOAD is in upward step, an output voltage V OUT generates undershoot, a feedback voltage V FB is reduced to further increase a voltage V ITH, and a comparator CMP1 is triggered faster to reduce turn-off time; the self-adaptive on-time generating circuit based on the PLL control is used for maintaining the switching period constant so as to generate larger on-time, so that the off-time is reduced, the on-time is increased, the inductance current I L is rapidly increased, and the transient response speed is accelerated;
When the load current I LOAD goes down, the output voltage V OUT goes down, the feedback voltage V FB goes up to decrease the voltage V ITH, and the comparator CMP1 triggers slower to increase the off time; the self-adaptive on-time generating circuit based on the PLL control is used for keeping the switching period constant, so that smaller on-time is generated, the off-time is increased, the on-time is reduced, the inductance current I L is rapidly reduced, and the transient response speed is accelerated.
According to the self-adaptive voltage positioning implementation method of the Buck converter control circuit, as a preferred mode, a frequency phase difference between a clock signal f clk and a switching tube control signal D is detected by a charge pump PFD/CP of a phase frequency detector, then a signal V LPF is generated through filtering by a low-pass filter LPF, a charge-discharge current I ctrl is generated by a transconductance amplifier OTA according to the relative size between the signal V LPF and a fixed voltage V B, a capacitor C r is periodically charged after the charge-discharge current I ctrl is overlapped with the fixed charge current I r so as to generate a ramp voltage S r, and a comparator CMP2 compares the ramp voltage S r with the fixed voltage V TH and then outputs a signal to an R end of an RS trigger so as to clear the switching tube control signal D;
The logic driving circuit generates a driving signal for driving the switching tube S 1、S2 according to the switching tube control signal D so as to regulate the output voltage V OUT;
The feedback voltage V FB is sent to the non-inverting input end of the error amplifier EA to be compared with the reference voltage V REF, and the output of the error amplifier EA is sent to the non-inverting input end of the comparator CMP1 to be compared with the inductance current I L obtained by sampling;
When the load current I LOAD is different, the magnitude of the signal V s including the inductor current I L is also different, and the magnitude of the error amplifier output V ITH corresponding to the comparator CMP1 when it is turned over is also different; therefore, different load current magnitudes I LOAD correspond to different magnitudes of the error amplifier output V ITH, and the output voltage V ITH of the error amplifier EA determines the magnitude of the inductor current I L; under the condition that external component parameters are consistent, different load current magnitudes I LOAD correspond to different error amplifier output values V ITH, and an AVP control circuit provides an additional current path for an output node ITH of an error amplifier EA, so that the corresponding V FB voltage variation when the ITH node voltage is changed is increased to perform self-adaptive voltage positioning.
In the implementation method of self-adaptive voltage positioning of the Buck converter control circuit, when the AVP control circuit comprises a resistor R 1 with one end connected with the output end of an error amplifier EA and the other end grounded and a resistor R 2 with one end connected with the output end of the error amplifier EA and the other end input voltage INTV CC as the optimal way,
The current I 1 is an additional current provided by the error amplifier EA to the ITH node to maintain the output voltage of the error amplifier EA corresponding to the magnitude of V ITH V ITH1,VITH1 and the magnitude of the load current I LOAD1;
The voltage V FB1 is the input voltage of the error amplifier EA when the load current is I LOAD1, and g m is the transconductance value of the error amplifier EA.
In the implementation method of self-adaptive voltage positioning of the Buck converter control circuit, when the AVP control circuit comprises a resistor R 1 with one end connected with the output end of an error amplifier EA and a direct current source I b with one end connected with the output end of the error amplifier EA,
When the AVP control circuit includes a direct current source I b having one end connected to the output of the error amplifier EA and the other end grounded, and a resistor R 2 having one end connected to the output of the error amplifier EA and the other end to which the voltage INTV CC is input;
The invention has the following advantages:
The invention provides a self-adaptive on-time generating circuit based on PLL control, a comparator, an error amplifier, an inductance current sampling circuit and a self-adaptive voltage positioning circuit of a logic control driving circuit, which are control circuits suitable for a Buck converter to realize quick transient response and support an AVP function, wherein the self-adaptive on-time generating circuit determines the on-time, and an inductance current sampling signal Vs is compared with an output V ITH of the error amplifier to determine the off-time, so that a switch is controlled to be conducted to adjust the output voltage. The control circuit provided by the invention can adaptively control the on-time and realize the function of self-adaptive voltage positioning, thereby greatly enhancing the transient response speed of the system, realizing the rapid transient response speed under various different conditions and reducing the requirements on off-chip elements.
Drawings
FIG. 1 is a transient response of output voltage transient contrast with or without an adaptive voltage positioning function;
fig. 2 is a schematic circuit diagram of a Buck converter control circuit and a method for implementing adaptive voltage positioning thereof;
FIG. 3 is a schematic diagram of key signal waveforms when a load step occurs in a Buck converter control circuit and an adaptive voltage positioning implementation method thereof;
FIG. 4 is a schematic diagram showing the relationship between the output current of the current mode Buck and the output voltage of the error amplifier in a Buck converter control circuit and an adaptive voltage positioning implementation method thereof;
FIG. 5 is a schematic diagram of a first AVP control circuit structure of a Buck converter control circuit and a method for implementing adaptive voltage location thereof;
FIG. 6 is a schematic diagram of a control circuit of a Buck converter and a second AVP control circuit structure of the adaptive voltage positioning implementation method thereof;
FIG. 7 is a schematic diagram of a third AVP control circuit structure of a Buck converter control circuit and a method for implementing adaptive voltage location thereof;
fig. 8 is a transient response waveform of an embodiment 1 of a Buck converter control circuit and an adaptive voltage positioning implementation method.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Example 1
A Buck converter control circuit and a self-adaptive voltage positioning implementation method thereof are provided, and the control circuit architecture of the invention is shown in figure 2. The overall control circuit comprises a Buck converter circuit, an error amplifier EA, an AVP circuit, comparators CMP1 and CMP1, an inductive current sampling circuit, an adaptive on-time generating circuit based on PLL control, a logic driving circuit and two power switching transistors S 1 and S 2.
Error amplifier EA amplifies the difference between feedback voltage V FB and reference voltage V REF, producing output voltage V ITH.
The AVP circuit adjusts the size of V ITH to achieve an adaptive voltage positioning function.
The inductor current sampling circuit samples the inductor current through a proportion R i to generate a current sampling signal V S.
The comparator CMP1 compares the magnitude of the current sample voltage V S with the error amplifier output voltage V ITH, and its output is connected to the S terminal of the RS flip-flop to set the duty cycle signal D.
The self-adaptive on-time generation circuit based on the PLL control comprises a phase frequency detector charge pump PFD/CP, a low-pass filter LPF, a transconductance amplifier OTA, a charging circuit and a comparator.
The phase frequency detector charge pump PFD/CP detects the frequency phase difference between the clock signal f clk and the duty cycle signal D, and the output thereof is filtered by the low pass filter LPF to generate a signal V LPF, which is connected to the positive input of the OTA. The OTA generates a charge-discharge current I ctrl according to the relative magnitude between V LPF and the fixed voltage V B, which is superimposed with the fixed charge current I r to periodically charge the capacitor C r, thereby generating a ramp voltage S r, which is connected to the positive input of the comparator CMP2 and compared with the fixed voltage V TH. The CMP2 output is connected to the R terminal of the RS flip-flop to zero out the duty cycle signal D.
The logic driving circuit generates driving signals for driving the power transistors S 1 and S 2 according to the duty ratio signal D so as to realize the adjustment of the output voltage.
The self-adaptive on-time generating circuit based on PLL control determines the on-time length, the feedback loop changes the voltage of V LPF by detecting the frequency phase difference between the switching tube control signal D and the clock signal, and generates different current by OTA, thereby generating different on-time to ensure that the switching frequency is consistent with the clock frequency.
When each switching period starts, the self-adaptive on-time generating circuit generates a certain amount of on-time, then enters an off period, the inductance current is reduced, and when the comparator is triggered, the off time is ended, and the next period is entered.
So when the load is stepped up, V FB decreases and thus V ITH increases due to undershoot generated by output voltage V OUT, and the comparator triggers faster so that the off time decreases. The PLL control-based adaptive on-time generation circuit generates a larger on-time in order to maintain the switching period constant, so that the off-time decreases, the on-time increases, and the inductor current rapidly increases, thereby accelerating the transient response speed, as shown in fig. 3.
Similarly, when the load steps down, V FB increases, which in turn causes V ITH to decrease, due to the overshoot of output voltage V OUT, the comparator triggers more slowly, which increases the off time. The self-adaptive on-time generating circuit based on the PLL control is used for keeping the switching period constant, so that smaller on-time is generated, the off-time is increased, the on-time is reduced, the inductance current is rapidly reduced, and the transient response speed is accelerated.
The feedback voltage is supplied to the input of the error amplifier for comparison with a reference voltage, and the output of the error amplifier is supplied to the input of the comparator for comparison with the sampled inductor current information. When the load current is different, the magnitude of the signal V s including the magnitude of the inductor current is also different, and the magnitude of the corresponding error amplifier output V ITH is also different when the comparator is turned over. Different load current magnitudes correspond to different error amplifier output V ITH magnitudes. The output voltage of the error amplifier determines the magnitude of the inductor current. Under the condition that the parameters of the external components are consistent, different load current values have corresponding error amplifier output V ITH values, as shown in figure 4.
According to the characteristics, the invention provides a circuit for realizing self-adaptive voltage positioning, the AVP control circuit is connected to the output node of the operational amplifier, and an additional current path is provided for the output node of the operational amplifier through the circuit, so that the corresponding V FB voltage variation is increased when the ITH node voltage is changed, and the self-adaptive voltage positioning function is realized.
Fig. 5 is an implementation manner of the AVP control circuit, in which two resistors are added to the output end of the op-amp to realize the adaptive voltage positioning function, and the structure is simple and easy to realize. INTV CC is a power supply voltage or any fixed voltage, and can be input by an external pin or generated by an internal circuit of a chip. Due to the presence of the resistors R1 and R2, the magnitude of V ITH tends to be biased toward a specific value V A, as shown in formula (1).
For a Buck converter with current mode control, different error amplifier outputs V ITH are corresponding to different load currents, for example, when the load current is I OUT1, the corresponding error amplifier output is V ITH1. When the load current is of magnitude I OUT1, the error amplifier needs to supply additional current I 1 to the ITH node due to the additional resistors R1 and R2 added to maintain the corresponding magnitude of V ITH at V ITH1.
The additional current I1 can be expressed as:
The input voltage V FB1 of the corresponding error amplifier at this time is:
g m*(REF-VFB1)＝I1 (4)
Therefore, when the load current is different in magnitude, the output V ITH of the error amplifier is different, so that the corresponding different V FB magnitude is provided, namely the different V OUT magnitude is provided, and the function of self-adaptive voltage positioning is realized.
Fig. 6 and 7 illustrate another implementation of the AVP control circuit, in which the dc current source I b may be implemented by mirror biasing of the current mirror, requiring a fixed dc current. The above derivation process can be used to derive the currents corresponding to fig. 6 and 7:
Therefore, when the load current is different in size, the output V ITH of the error amplifier is different, so that the corresponding different V FB sizes are provided, namely the different V OUT sizes are provided, the function of self-adaptive voltage positioning is realized, and the speed of transient response is further enhanced.
Fig. 8 shows a simulated transient waveform after the invention is adopted, load current is hopped from 0A to 5A in a bidirectional manner, undershoot and overshoot of output voltage are almost 0, and response speed is improved.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (10)
1. The utility model provides a Buck converter control circuit which characterized in that: the self-adaptive on-time generation circuit comprises a Buck converter circuit, an error amplifier EA, an AVP control circuit, an inductive current sampling circuit, a comparator CMP1, an RS trigger, a logic driving circuit, a self-adaptive on-time generation circuit and a logic driving circuit, wherein the feedback voltage V FB of the Buck converter circuit is compared with a reference voltage V REF, the error amplifier EA is used for outputting a voltage V ITH, the AVP control circuit is connected with the output end of the error amplifier EA, the AVP control circuit is used for adjusting the voltage V ITH, the inductive current sampling circuit is connected with one end of R DCR of the Buck converter circuit, samples inductive current I L in a specified proportion and generates a current sampling voltage V S, the comparator CMP1 is used for comparing the current sampling voltage V S as a negative phase input with a voltage V ITH which is a positive phase input, the S end of the RS trigger is connected with the output end of the comparator CMP1, the self-adaptive on-time generation circuit is connected with the Q end and the R end of the RS trigger, the logic driving circuit is connected with the switching tube S 1、S2 of the Buck converter circuit, the Buck converter circuit generates an output voltage V OUT and a load current I LOAD, and the RS trigger outputs a switching tube control signal D to the self-adaptive on-time generation circuit and the logic driving circuit based on the PLL control circuit;
The self-adaptive on-time generation circuit based on the PLL control detects the frequency phase difference between the switching tube control signal D and the clock signal f clk so as to generate different on-times; the AVP control circuit provides an additional current path to the output node ITH of the error amplifier EA such that the corresponding amount of V FB voltage change increases as the ITH node voltage changes for adaptive voltage positioning.
2. The Buck converter control circuit of claim 1, wherein: the self-adaptive on-time generation circuit based on the PLL control comprises a phase frequency detector charge pump PFD/CP for detecting the frequency phase difference between a switching tube control signal D and a clock signal f clk, a low-pass filter LPF connected with the output end of the phase frequency detector charge pump PFD/CP, a transconductance amplifier OTA with a positive input end connected with the low-pass filter LPF and an inverse input end connected with a fixed voltage V B, a fixed charging current I r input from the outside, a pair capacitor C r connected with the output end of the transconductance amplifier OTA and the fixed charging current I r, and a comparator CMP2 with the positive input end connected with the capacitor C r;
One input end of a charge pump PFD/CP of the phase frequency detector is connected with a Q end of an RS trigger, a switching tube control signal D is a duty ratio signal, the other end of a capacitor C r is grounded, a capacitor C r outputs a ramp voltage signal S r, an inverting input of a comparator CMP2 is a fixed voltage V TH, an output end of the comparator CMP2 is connected with an R end of the RS trigger, and the Q end of the RS trigger outputs the duty ratio signal D;
The NMOS transistor switch is connected to two ends of the capacitor C r, the NMOS transistor switch inputs an inverted signal D of a switching transistor control signal D, and the NMOS transistor switch clears the voltage of the capacitor C r in each period so that the ramp voltage signal Sr rises from zero in each period;
The sampling coefficient of the inductive current sampling circuit is R i, the sampling voltage is V S, and the inductive current sampling circuit is connected with the inverting output end of the comparator CMP 1.
3. The Buck converter control circuit of claim 1, wherein: the Buck converter circuit comprises an inductor L and a resistor R DCR which are connected with each other, a resistor R ESR, a resistor R L and a resistor R F1 which are connected with the other end of the resistor R DCR in parallel, a capacitor C OUT connected with the other end of the resistor R ESR, a resistor R F2 connected with the other end of the resistor R F1 and a switch tube S 1、S2 connected with the other end of the inductor L;
The source electrode input voltage V in and the drain electrode of the switch tube S 1 are connected with the inductance L, the grid electrode of the switch tube S 2 is connected with the logic driving circuit, the source electrode of the switch tube S 2 is grounded, the drain electrode of the switch tube S is connected with the inductance L, the grid electrode of the switch tube S 2 is connected with the logic driving circuit, the other ends of the capacitor C OUT, the resistor R L and the resistor R F2 are grounded, a feedback voltage V FB is output between the resistor R F1 and the resistor R F2, the feedback voltage V FB is connected with the inverting input end of the error amplifier EA, and the resistor R L outputs the voltage V OUT and the load current I LOAD;
The switching tube S 1 is a PMOS tube, and the switching tube S 2 is an NMOS tube.
4. The Buck converter control circuit of claim 1, wherein: the AVP control circuit comprises a resistor R 1 with one end connected with the output end of the error amplifier EA and the other end grounded, and a resistor R 2 with one end connected with the output end of the error amplifier EA and the other end input voltage INTV CC;
The voltage INTV CC is a power supply voltage or a fixed voltage.
5. The Buck converter control circuit of claim 1, wherein: the AVP control circuit comprises a resistor R 1 with one end connected with the output end of the error amplifier EA and the other end grounded, and a direct current source I b with one end connected with the output end of the error amplifier EA; the direct current source I b is connected to the voltage INTV CC.
6. The Buck converter control circuit of claim 1, wherein: the AVP control circuit comprises a direct current source I b with one end connected with the output end of the error amplifier EA and the other end grounded, and a resistor R 2 with one end connected with the output end of the error amplifier EA and the other end input voltage INTV CC; the voltage INTV CC is a power supply voltage or a fixed voltage.
7. The method for implementing adaptive voltage positioning of a Buck converter control circuit according to any one of claims 1-6, wherein: when the load current I LOAD is stepped upwards, the output voltage V OUT is undershooted, the feedback voltage V FB is reduced to further increase the voltage V ITH, and the comparator CMP1 is triggered faster to reduce the turn-off time; the self-adaptive on-time generating circuit based on the PLL control is used for maintaining the switching period to be constant so as to generate larger on-time, so that the off-time is reduced, the on-time is increased, the inductance current I L is rapidly increased, and the transient response speed is accelerated;
When the load current I LOAD goes down, the output voltage V OUT goes down, the feedback voltage V FB goes up to decrease the voltage V ITH, and the comparator CMP1 triggers slower to increase the off time; the self-adaptive on-time generating circuit based on the PLL control is used for keeping the switching period constant, so that smaller on-time is generated, the off-time is increased, the on-time is reduced, the inductance current I L is rapidly reduced, and the transient response speed is accelerated.
8. The method for implementing adaptive voltage positioning of a Buck converter control circuit according to claim 7, wherein: the charge pump PFD/CP of the phase frequency discriminator detects the frequency phase difference between the clock signal f clk and the switching tube control signal D, then filters the frequency phase difference through a low-pass filter LPF to generate a signal V LPF, the transconductance amplifier OTA generates charge-discharge current I ctrl according to the relative magnitude between the signal V LPF and the fixed voltage V B, the charge-discharge current I ctrl is overlapped with the fixed charge current I r and then periodically charges the capacitor C r to generate a ramp voltage S r, and the comparator CMP2 compares the ramp voltage S r with the fixed voltage V TH and then outputs a signal to the R end of the RS trigger to clear the switching tube control signal D;
The logic driving circuit generates a driving signal for driving the switching tube S 1、S2 according to the switching tube control signal D so as to regulate the output voltage V OUT;
The feedback voltage V FB is sent to the non-inverting input end of the error amplifier EA to be compared with the reference voltage V REF, and the output of the error amplifier EA is sent to the non-inverting input end of the comparator CMP1 to be compared with the inductance current I L obtained by sampling;
When the load current I LOAD is different, the magnitude of the signal V s including the inductor current I L is also different, and the magnitude of the error amplifier output V ITH corresponding to the comparator CMP1 when it is turned over is also different; therefore, different load current magnitudes I LOAD correspond to different magnitudes of the error amplifier output V ITH, and the output voltage V ITH of the error amplifier EA determines the magnitude of the inductor current I L; under the condition that external component parameters are consistent, different load current magnitudes I LOAD correspond to different error amplifier output values V ITH, and an AVP control circuit provides an additional current path for an output node ITH of an error amplifier EA, so that the corresponding V FB voltage variation when the ITH node voltage is changed is increased to perform self-adaptive voltage positioning.
9. The method for implementing adaptive voltage positioning of a Buck converter control circuit according to claim 7, wherein: when the AVP control circuit includes a resistor R 1 having one end connected to the output of the error amplifier EA and the other end grounded and a resistor R 2 having one end connected to the output of the error amplifier EA and the other end input voltage INTV CC,
The current I 1 is an additional current provided by the error amplifier EA to the ITH node to maintain the output voltage of the error amplifier EA corresponding to the magnitude of V ITH V ITH1,VITH1 and the magnitude of the load current I LOAD1;
The voltage V FB1 is the input voltage of the error amplifier EA when the load current is I LOAD1, and g m is the transconductance value of the error amplifier EA.
10. The method for implementing adaptive voltage positioning of a Buck converter control circuit according to claim 9, wherein: when the AVP control circuit includes resistor R 1 connected at one end to the output of error amplifier EA and dc current source I b connected at one end to the output of error amplifier EA,
When the AVP control circuit includes a direct current source I b having one end connected to the output of the error amplifier EA and the other end grounded, and a resistor R 2 having one end connected to the output of the error amplifier EA and the other end to which the voltage INTV CC is input;
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