KR20090063135A - Constant on-time regulator with increased maximum duty cycle - Google Patents

Abstract

A switching regulator and a control method for the same are provided, which can produce switching output voltage having the reduced output ripple by using the feedback control loop. The switching regulator(100) controls the high-side switch(M1) and low-side switch(M2) by using the feedback control loop. The switching regulator runs the switch output node in order to produce the switching output voltage. The switch output node is combined with the LC filter circuit. The voltage divider produces the feedback voltage in the feedback voltage node. The on-time control circuit(128) produces the first signal for controlling the high-side switch.

Description

Buck switching regulators and methods {CONSTANT ON-TIME REGULATOR WITH INCREASED MAXIMUM DUTY CYCLE}

This application is filed September 11, 2006, entitled “RIPPLE GENERATION IN BUCK REGULATOR USING FIXED ON-TIME CONTROL TO ENABLE THE USE OF OUTPUT CAPACITOR HAVING ANY ESR” and having the invention and at least one co-inventor In some continuing applications of No. 11 / 530,548, application number 11 / 530,548 is incorporated herein by reference in its entirety.

This application is related to U.S. Patent Application No. 11 / 955,150 to Ioan Stoichita, Matthew Weng and Charles Vinn, entitled “CONSTANT ON-TIME REGULATOR WITH INTERNAL RIPPLE GENERATION AND IMPROVED OUTPUT VOLTAGE ACCURACY” It is hereby incorporated by reference in its entirety.

The present invention relates to a switching regulator or a DC-DC converter, and more particularly, to a control scheme combined with a fixed on-time buck regulator using multi-mode on and off time control.

The DC voltage regulator or switching regulator operates to convert energy from one DC voltage level to another DC voltage level. This type of switching regulator is also known as a DC / DC converter. Switching regulators, commonly referred to as switched-mode power supplies, provide power supply functionality through low-loss components such as capacitors, inductors, and transformers, and power switches that are turned on and off to transfer energy from the input to the output of individual packets. In order to maintain a fixed output voltage within the desired load range of this circuit, a feedback control circuit is used to regulate the energy transfer.

The switching regulator can be configured to step up the input voltage, step down the input voltage, or both. Specifically, a buck switching regulator, also referred to as a "buck converter", steps down the input voltage and a boost switching regulator, also referred to as a "boost converter," steps up the input voltage. Buck-boost switching regulators or buck-boost converters provide both step-up and step-down functions.

The operation of the switching regulator is well known and is generalized as follows. The power switch is turned on to apply energy to the inductor of the output filter circuit and generate a current through the inductor. When the power switch is turned off, the voltage across the inductor is reversed and charge is transferred to the output capacitor and load of the output filter circuit. A relatively fixed output voltage is maintained by the output capacitor. Often a second switch is used for synchronous control operation.

The switching regulator can be configured using an integrated (internal) power switch or an external power switch. If the power switch is external to the switching regulator integrated circuit (IC), the switching regulator IC is often referred to as a "switching regulator controller" or converter controller, where the switching regulator controller is coupled to an output filter circuit that generates a relatively fixed output voltage. Indicates that a control signal for driving an external power switch is provided. The switching regulator controller is also referred to as buck controller, boost controller or buck-boost controller, depending on the voltage conversion function of the controller.

Buck switching regulators or "buck regulators" using fixed on-time control provide excellent efficiency for light loads in PFM (pulse width modulation) mode, easy synchronization with external signals, and relatively large off-time. Some important advantages such as ease of control and very small fixed on-time for regulating the high input voltage with low output voltage are preferred in this field.

Fixed on-time (or fixed on-time) regulators are a type of voltage regulator that employs ripple-mode control, and hysteretic regulators are another type of switching regulator that employs ripple-mode control. In general, a ripple-mode regulator adjusts its output voltage based on the ripple component of the output signal. Due to the switching operation at the power switch, all switch-mode regulators generate an output ripple current through the switched output inductor. This current ripple represents this as the output voltage ripple, especially due to the equivalent series resistance (ESR) of the output capacitor placed in parallel with the load.

The hysteresis regulator uses a comparator to compare the output voltage to be adjusted, including the ripple, to the hysteresis control band. Above the hysteresis upper limit, the hysteresis controller switches its associated output inductor low, and below the hysteresis lower limit, the magnetic history controller switches the output inductor high. On the other hand, a fixed on-time regulator operates similar to a hysteresis controller, turning the output inductor high for a fixed time when the output ripple falls below a single reference point. At the end of the fixed on-time, even if the output ripple is still below a single reference point, the output inductor is switched low for a minimum off-time before switching back high for a fixed on-time.

For voltage regulators using ripple-mode control, output ripple is useful for output voltage regulation, but is undesirable in view of output signal noise and load voltage limitations. Indeed, the need to minimize output ripple has led to the design and manufacture of capacitors with very low ESR. By lowering the output capacitor ESR, the output ripple signal can be significantly lowered. Low ripple offers the advantages of noise minimization and reduced load voltage variation, but makes ripple-mode adjustment more difficult. The low ripple size reduces the comparator voltage difference and makes it difficult to make accurate and fast comparisons.

This allows manufacturers of fixed on-time voltage regulators to impose a minimum ESR on the output capacitor to ensure the minimum amount of ripple voltage in the output voltage so that efficient ripple-mode control can be realized. Therefore, output capacitors with large ESR must be used with all fixed on-time voltage regulators. In some cases, if the output capacitor itself does not have sufficient ESR, manufacturers propose to include a resistor in series with the output capacitor to introduce sufficient series resistance to generate the required minimum amount of ripple voltage.

One solution to the requirements of high ESR output capacitors is to add current feedback to the control loop. In other cases, a virtual ripple generator is used to generate an internal virtual ripple that is proportional to the inductor current. This solution allows the use of low ESR in ripple-mode voltage regulators, but these solutions add complexity and cost to the voltage regulator.

The requirement for a minimum amount of ripple voltage in the output signal limits the application of a fixed on-time voltage regulator to where the ripple of the output voltage can be tolerated. Also, zero ESR capacitors, such as ceramic capacitors, which are typically cheaper than tantalum capacitors with large ESRs, cannot be used because a minimum amount of ESR is required for proper control loop operation.

According to one embodiment of the invention, a buck switching regulator is formed on an integrated circuit to receive an input voltage, and the buck switching regulator uses a high-side switch and a low side using a feedback control loop. The low-side switch is controlled to drive a switch output node that produces a switching output voltage. The switch output node is coupled to an LC filter circuit outside the integrated circuit to produce a regulated output voltage having a substantially constant magnitude on the output node. The regulated output voltage is fed back to the buck switching regulator and supplied to a voltage divider that generates a feedback voltage on the feedback voltage node. The buck switching regulator includes an on-time control circuit that generates a first signal for controlling the high side switch under a minimum on-time and variable off-time feedback control loop, The first signal then turns off the high side switch upon expiration of a first on-time duration or upon expiration of maximum on-time. The first on-time period is at least minimum on-time and can be extended to a maximum on-time when the feedback voltage is kept below the reference voltage. The maximum on-time may be a first maximum on-time and a second extended maximum on-time greater than the first maximum on-time. The second extended maximum on-time applies when the minimum off-time is used for the high side switch during the previous switching cycle.

According to another aspect of the present invention, there is provided a method in a buck switching regulator for receiving an input voltage and driving a switch output node for generating a switching output voltage by controlling a high side switch and a low side switch using a feedback control loop. The switch output node is coupled to the LC filter circuit to produce a regulated output voltage having a substantially constant magnitude on the output node, which is fed back to the buck switching regulator to produce a feedback voltage on the feedback voltage node. Supplied to a voltage divider, the method providing a first on-time period for high side switching, the first on-time period being at least a minimum on-time and maximum when the feedback voltage is kept below the reference voltage. Extend to on-time, the maximum on-time being a first maximum on-time or the first maximum on-time May be a larger second extended maximum on-time-and applying a second extended maximum on-time and minimum on when the minimum off-time was used on the high side switch during the previous switching cycle. Generating a first signal for turning off the high side switch under a time and variable off-time feedback control loop. The first signal turns off the high side switch upon expiration of the first on-time period or upon expiration of the first or second maximum on-time.

The invention will be better understood with reference to the following detailed description and the accompanying drawings.

In accordance with the principles of the present invention, a buck switching regulator using a fixed on-time (or fixed on-time) and minimum off-time control loop uses a switching output voltage to internally generate the necessary ripple and cause the ripple voltage. It includes a ripple input circuit that inputs the signal into the feedback control loop of the voltage regulator. The amount of ripple to be generated is controlled by a feedforward capacitor that can be integrated into the buck regulator or externally coupled to the buck regulator. In this manner, the buck regulator is configured to operate with an output capacitor having any equivalent series resistance (ESR) value. In particular, when the output capacitor coupled to the buck regulator has a large ESR, a feedforward capacitor is used to program the ripple input circuit to produce very little or no ripple from the switching output voltage. However, if the output capacitor coupled to the buck regulator has zero or very few ESRs, the feedforward capacitor is used to program the ripple input circuit to generate the required ripple from the switching output voltage.

Buck switching regulators with ripple input circuitry offer many advantages over conventional solutions. First, the buck switching regulator of the present invention enables the use of an output capacitor with any ESR value. Thus, zero or low ESR value capacitors, such as ceramic capacitors, can be used to obtain output voltages with very low output ripple. On the other hand, the ripple input circuit internally uses the switching output voltage to generate the necessary ripple so that the generated ripple voltage does not have any effect on the output voltage.

According to one aspect of the invention, the ripple input circuit includes a first capacitor and a first resistor connected in series between the switching output voltage and the feedback voltage, and also includes a feedforward capacitor connected between the output voltage and the feedback voltage. do. In one embodiment, the first capacitor and the first resistor are integrated with the resistor dividers of the feedback voltage divider onto the same integrated circuit of the buck switching regulator, and the feedforward capacitor is formed outside of the switching regulator integrated circuit. In another embodiment, the feedforward capacitor is also integrated on the switching regulator integrated circuit. In the case of integrated on-chip, the feedforward capacitor is formed of a capacitor with a programmable capacitance so that the desired capacitance can be selected to adjust the desired amount of ripple to be generated.

According to another aspect of the invention, a buck switching regulator using a fixed on-time and variable off-time control loop comprises a ripple input circuit with improved accuracy, which is feedback control of a voltage regulator away from the feedback voltage node. Input the ripple voltage signal to a point in the loop. In this way, errors in the output voltage are reduced and the accuracy of the output voltage is greatly increased. In one embodiment, the ripple input circuit includes a gain stage for receiving a feedback voltage and the ripple voltage signal is input at the output node of the gain stage. By using the gain stage to amplify the feedback voltage and inputting the ripple voltage signal at the bypassing point of the gain stage, the voltage error inserted into the regulated output voltage can be significantly reduced.

In one embodiment, the ripple input circuit includes a gain stage implemented as an operational transconductance amplifier (OTA) that receives a feedback voltage and a first reference voltage. The ripple input circuit further includes a first capacitor and a first resistor connected in series between the switching output voltage and the output terminal of the OTA. Finally, the ripple input circuit includes a feedforward capacitor connected between the output voltage and the output terminal of the OTA. Ripple input circuits with improved accuracy will be described in more detail below.

1 is a schematic diagram of a fixed on-time, minimum off-time buck switching regulator including a ripple input circuit in accordance with an embodiment of the present invention. Referring to FIG. 1, the buck switching regulator system 10 includes a buck switching regulator 100 (“buck regulator 100”) coupled to an output LC filter circuit. The buck regulator 100 receives an input voltage V _IN and provides a switching output voltage V _SW to an output LC filter circuit formed by an inductor L1 and an output capacitor C _OUT . The output LC filter circuit generates a DC output voltage V _OUT at an output voltage node 114 having a substantially fixed magnitude. In a practical implementation, as shown in FIG. 1, the output voltage V _OUT is coupled to drive the load 116. The output capacitor C _OUT connects a certain amount of ESR with it, which is represented by a dotted line resistor ESR connected in series with the output capacitor. When an output capacitor with zero ESR is used, the resistor ESR has a zero resistance and is therefore a short circuit.

The buck regulator 100 implements a fixed on-time, minimum off-time feedback control loop. In this specification, fixed on-time is also referred to as "fixed on-time". In the following description, we will first describe the fixed on-time feedback control loop of the buck regulator and describe the ripple input circuitry that inputs the desired amount of ripple into the feedback control loop.

Referring to FIG. 1, the buck regulator 100 receives an input voltage V _IN on a terminal 102. A pair of power switches M1 and M2 are connected in series between the input voltage V _IN (terminal 102) and the ground voltage of the PGND terminal 106. In this configuration, the buck regulator 100 includes separate ground connections, PGND and SGND for the power switch and the rest of the circuit for noise isolation purposes. The use of separate ground connections for noise isolation is well known in the art and is not critical to the practice of the present invention. In this embodiment, the power switch M1 is a PMOS transistor and the power switch M2 is an NMOS transistor and is controlled by a drive signal generated by the driver 134. The switching output voltage V _SW is generated at the common node 122 between the power switches M1 and M2. The switching output voltage V _SW is coupled to an inductor-capacitor (LC) filter network comprising an inductor L1 and an output capacitor C _OUT through the SW terminal 104 to filter the switching output voltage V _SW . And generate a DC output voltage V _OUT at an output voltage node 114 having a substantially fixed magnitude. In a practical implementation, the DC output voltage V _OUT is used to drive the load 116.

The DC output voltage V _OUT is again coupled to the buck regulator 100 to form a feedback control loop for adjusting the switching output voltage V _SW . Specifically, output voltage V _OUT is coupled to a voltage divider formed by resistors R1 and R2 through FB terminal 108. The feedback voltage V _FB , which is a stepped down version of the output voltage V _OUT , is coupled to the first input terminal (negative input terminal) of the error comparator 126. Reference voltage V _REF (node 138) is coupled to a second input terminal (positive input terminal) of error comparator 126. The reference voltage V _REF is generated by the voltage reference circuit 136 powered by the input voltage V _IN . The voltage reference circuit 136 is well known and many circuit configurations are possible for receiving an input voltage V _IN and generating a reference voltage V _REF having a desired voltage magnitude.

Error comparator 126 is a feedback voltage (V _FB) and a reference voltage (V _REF) evaluating a difference between the feedback voltage (V _FB) and a reference voltage (V _REF), the output voltage signal (V _{COMP_OUT} indicating the difference between the ). To form a fixed on-time control loop, the output voltage signal V _{COMP_OUT} is coupled to the start input terminal of the on-timer 128 and the logic circuit 132. On-timer 128 provides a predetermined on-time duration when the start signal is asserted and provides an end output signal indicating the end of the predetermined on-time duration. When the feedback voltage V _FB falls below the reference voltage V _REF , the output voltage signal V _{COMP_OUT} is declared and the on-time duration programmed in the on-timer 128 is started. When the on-time duration is initiated, the on-timer 128 also provides a control signal on the bus 129 to the logic circuit 132 to instruct the logic circuit 132 to turn on the high-side switch M1. do. Therefore, the current through the inductor L1 can be built up. The high-side switch M1 is only turned on for a fixed duration. When the on-time duration expires, on-timer 128 instructs logic circuit 132 to turn off high-side switch M1 and turn on low-side transistor M2.

To implement minimum off-time control, an end output signal from on-timer 128 is coupled to the start input terminal of off-timer 130. Thus, when the on-time duration expires, an off-time duration programmed in off-timer 130 is initiated. The off-timer 130 provides an end output signal to the logic circuit 132 to indicate the end of the off-time duration, wherein if the feedback voltage V _FB is less than the reference voltage V _REF , the power transistor ( M1) may be turned on again. In this way, the minimum off-time is implemented in the feedback control loop.

Through operation of the error comparator 126, the on-timer 128 and the off-timer 130, the logic circuit 132, generate a control signal such that the driver 134 causes the power switches M1 and M2 to switch. It is turned on and off alternately to generate the output voltage V _SW . In this embodiment, a feedback control loop is established such that the on-time of the buck switching regulator 100 is adaptable to different input voltages and different output voltages to keep the operating frequency constant.

FIG. 2 is a flow diagram illustrating the fixed on-time and minimum off-time feedback control loop operation implemented in the buck switching regulator system of FIG. 1. Referring to FIG. 2, at the start of the feedback control loop, the feedback voltage V _FB is compared against the reference voltage V _REF (step 204). If the feedback voltage V _FB is less than the reference voltage V _REF , the control loop turns on the high-side switch M1 for a fixed on-time (and the low-side switch M2 turns off). (Step 206). After the fixed on-time, the high-side switch M1 is turned off for the minimum off-time (and the low-side switch M2 is turned on) (step 208). The control loop then returns to comparison step 204. If the feedback voltage V _FB is greater than or equal to the reference voltage V _REF , no action is taken and the high-side switch M1 remains turned off and the low-side switch M2 remains turned on. . However, if the feedback voltage V _FB is still smaller than the reference voltage V _REF , the high-side switch M1 is turned on again for a fixed on-time (step 206). The control loop operates continuously to maintain the feedback voltage V _{FB at} or above the logic voltage V _REF .

As shown by the flowchart in FIG. 2, the buck switching regulator system 10 of FIG. 1 has a minimum off-time (off-time) when the feedback voltage V _FB is equal to or greater than the reference voltage V _REF . min-off from nominal off-time to control off-time. In continuous current mode, the buck regulator's operating frequency is stable and the duty cycle is given by

Where ConstTon is fixed on-time and Contr.Toff is off-time. Fixed on-time is defined as

The frequency of the switching output voltage is constant as a function of V _IN . The frequency of the fixed switching output voltage is desirable in the same application.

Referring to FIG. 1, the buck switching regulator 100 includes a ripple input circuit 120 operating with a feedback capacitor C _FF to generate a given amount of ripple from the switching output voltage and buck the ripple voltage signal. Input into the feedback control loop of the switching regulator system 10. Including the ripple input circuit and feedforward capacitor C _FF , the buck regulator 100 of the present invention may be coupled to an output capacitor C _OUT having any ESR value. That is, a zero-ESR capacitor such as a ceramic capacitor can be used as the output capacitor C _OUT to minimize the ripple voltage at the output voltage V _OUT . On the other hand, the ripple input circuit and feedforward capacitor of the present invention provide the necessary ripple for the feedback control loop. On the other hand, when using a capacitor with a large ESR, the ripple input circuit of the present invention can be deactivated by the feedforward capacitor since no ripple occurs.

The ripple input circuit 120 includes a first capacitor C _INJ and a resistor R _INJ connected in series between the switching output voltage V _SW (node 122) and the feedback voltage V _FB (node 124). It includes. In this embodiment, the first capacitor (C _INJ) is provided with a the other terminal connected to one terminal and the resistor (R _INJ) connected to the switching output voltage node (SW), the resistance (R _INJ) is a capacitor (C _INJ ) and a feedback voltage V _FB (node 124). In another embodiment, the order of capacitor C _INJ and resistor R _INJ may be reversed. Ripple input circuit 120 works with the voltage dividers of resistors R1 and R2 to generate a feedback voltage V _FB having a desired voltage level and a desired amount of ripple. According to the present invention, the ripple input circuit 120 is coupled to the switching output voltage node 122 so that a ripple voltage signal is generated from the switching output voltage V _SW . In other words, the ripple voltage signal is at the switching frequency of the switching output voltage which is divided-down of the switching output voltage V _SW . If a ripple signal is present at the feedback voltage (V _FB ) node 124, the amount is determined by the capacitance value of the feedforward capacitor. The feedforward capacitor C _FF is connected between the output voltage V _OUT (node 114) of the buck regulator 100 and the feedforward FFWD terminal 110. The feedforward FFWD terminal 110 is directly connected to the feedback voltage (V _FB ) node 124. Thus, the feedforward capacitor C _FF is connected between the output voltage V _OUT and the feedback voltage V _FB .

The ripple voltage signal is divided by the capacitor C _INJ and the feedforward capacitor C _FF . When the switching output voltage (V _SW) is applied to the capacitor (C _INJ), the capacitor (C _INJ) operates as a differentiator (differentiator). When the switching output voltage V _SW switches fast enough, the capacitor C _INJ operates as a short circuit. In this manner, the switching output voltage V _SW is divided to generate a ripple voltage signal. In one embodiment, the ripple voltage has a peak-peak voltage of approximately 20 mV.

Feedforward capacitor C _FF is coupled in parallel with resistors R1 and R2 and operates as a capacitive divider with capacitor C _INJ . Thus, the peak-peak voltage of the ripple voltage signal is made as a function of the capacitance value of the feedforward capacitor C _FF . Thus, the capacitance value of the feedforward capacitor C _FF is used to program the ripple input circuit to cause the buck regulator 100 to operate with an output capacitor C _OUT having any ESR value.

More specifically, the feedforward capacitor C _FF is AC coupled between the output voltage V _OUT and the feedback voltage V _FB . If the capacitance of capacitor C _FF is very large, capacitor C _FF is a short circuit for the AC signal that may appear at output voltage V _OUT node 114. As such, the ripple input circuit is shorted by a large feedforward capacitor C _FF and no ripple signal generated by the ripple input circuit is input to the feedback voltage V _FB node. Instead, the output voltage V _OUT with the ripple voltage component is coupled to the voltage divider of the feedback control loop through the FB terminal 108. Thus, the feedback voltage V _FB is generated from the output voltage signal V _OUT with the required ripple.

On the other hand, if the capacitance of the capacitor C _FF is very small or zero, the capacitor C _FF is open circuit for AC signals that may appear on the output voltage V _OUT node 114. In this case, the ripple signal generated by the ripple input circuits of the capacitors C _INJ and R _INJ is passed to the feedback voltage V _FB node 124 and a maximum amount of ripple is provided to the feedback control loop.

Thus, in practical implementations, when an output capacitor C _OUT with a sufficiently large ESR is used, the ripple input circuit 120 does not need to generate any ripple voltage signal for the feedback control loop. If no ripple voltage is required from the ripple input circuit, a feed forward capacitor C _FF having a large capacitance value is used, where the large feed forward capacitor C _FF has the effect of the capacitor C _INJ of the ripple input circuit. Essentially shorting and the ripple signal generated by the ripple input circuit is canceled by the feedforward capacitor C _FF .

On the other hand, when an output capacitor C _OUT having a small or zero ESR is used, the ripple input circuit 120 is adapted to provide the ripple voltage signal required for the feedback control loop. Thus, a feed forward capacitor C _FF having a small capacitance value is used so that the ripple signal generated by the ripple input circuit 120 from the switching output voltage V _SW can be transmitted to the feedback voltage node 124. do.

Thus, the feedforward capacitor C _FF operates to adjust the amount of ripple voltage to be provided by the ripple input circuit 120. In one embodiment, the feedforward capacitor (C _FF ) SMS has capacitance values ranging from 220 pF to 2.2 nF. Thus, the buck regulator 100 can simply select the corresponding capacitance value for the feedforward capacitor and operate with the output capacitor to value any ESR value. In addition to being used as a capacitive divider with a ripple input circuit, the feedforward capacitor also functions to provide zero to the feedback control loop to improve the stability of the transient response.

In addition, the ripple voltage signal generated by the ripple input circuit is an AC version of the switching output voltage V _SW coupled to drive the inductor L1, so the ripple voltage signal is directly proportional to the input voltage V _in . In terms of control loop stability, it is better to have a ripple, but in terms of accuracy (load regulation, output voltage ripple), it should be minimized to have minimal effect when the input voltage changes.

In this embodiment, the feedforward capacitor C _FF is formed outside the integrated circuit of the buck regulator 100 so that the different capacitance values of the feedforward capacitor are used to match the ESR characteristics of the output capacitor C _OUT . Therefore, the amount of the input ripple voltage can be fine tuned by the feedforward capacitance C _FF . However, in other embodiments, both the ripple input circuit and the feedforward capacitor C _FF can be integrated into the buck regulator integrated circuit to reduce the number of external components of the buck switching regulator system 10. When integrated, the feedforward capacitor C _FF may have a suitable capacitance value for a given range of ESR values of the output capacitor.

The buck regulator including the ripple input circuit and feedforward capacitor of the present invention realizes many advantages over conventional solutions. For example, one conventional solution amplifies the small amount of ripple voltage remaining to generate a ripple voltage from the output voltage V _OUT . When the ripple signal is very small, it is very difficult to duplicate the ripple and differentiate the ripple signal from the noise signal. In contrast, the ripple input circuit of the present invention generates a ripple signal from the switching output voltage. Thus, a simple circuit can be used to divide the switching output voltage and the ripple signal can be generated without noise.

Improved Output Voltage Accuracy

In the buck regulator 100 of FIG. 1, the DC output voltage V _OUT is a voltage having a substantially fixed magnitude and substantially free of voltage ripple. The ripple voltage signal from the ripple input circuit 120 is input to the feedback voltage node V _FB node 124. The control loop formed by the ripple input circuit has low gain and therefore accuracy is limited. In operation, the average DC voltage (middle point) of the ripple voltage signal should be equal to the comparator reference voltage V _REF . However, when the ripple voltage is input to the feedback voltage V _FB , the average DC voltage of the ripple signal is offset from the reference voltage V _REF due to various factors such as the delay time of turning on the high-side switch. Accordingly, the output voltage V _OUT has a DC offset voltage component that affects the accuracy of the buck regulator.

3 is a voltage waveform showing the feedback voltage V _FB of the constant on-time voltage regulator of FIG. 1. Referring to FIG. 3, the waveform 190 is a feedback voltage V _FB input with ripple. The waveform diagram of FIG. 3 assumes that the "on" resistance of the power switch is zero. At time zero, the upper switch M1 is on for a constant on-time t _ON . The peak-to-peak ripple ΔV ₁ is as follows.

After a certain on-time, the upper switch turns off and the feedback voltage V _FB decreases. When the feedback voltage V _FB drops to the reference voltage V _REF (line 194), the upper switch M1 will turn on again after the propagation delay t _delay . The voltage amount ΔV ₂ at which the feedback voltage V _FB falls below the reference voltage V _REF is as follows.

Because of the delay time when the upper switch is turned on, the average feedback voltage AVG_V _FB (line 192) is offset from the reference voltage V _REF (line 194). The difference between the average feedback voltage AVG_V _FB and the reference voltage V _REF is the error voltage V _{ERR2, which} is given by ½ΔV ₁ -ΔV ₂ . The error in the output voltage V _OUT is calculated by multiplying the voltage error V _ERR2 by the feedback _divider . Thus, the residual DC voltage error that appears at the output voltage V _OUT is (V _OUT / V _REF ) times the error that appears at the feedback terminal in the form of voltage error V _ERR2 . Thus, the output voltage V _OUT incorporates magnified voltage error and becomes inaccurate. For example, if the error voltage V _ERR2 is 10 mV, the output voltage V _OUT is 1.8 V, the reference voltage V _REF is 0.9 V, and the DC residual voltage error seen at the output voltage is 10 mV (1.8 / 0.9) = 20 mV. The offset voltage is 20 mV at the output voltage V _OUT .

In addition, the fact that the time values t _ON and t _delay are independent parameters leads to inaccuracies in the DC output voltage V _OUT . Further, the voltages ΔV ₁ and ΔV ₂ change depending on the input voltage V _IN and the output voltage V _OUT , thereby degrading line regulation. Finally, in a practical implementation, the "on" resistance is not zero. Thus, the output voltage V _OUT will vary with the load. These factors contribute to the inaccuracy of the undesirable regulated output voltage V _OUT .

According to another aspect of the invention, a buck switching regulator using constant on-time and variable off-time control loops incorporates an improved accuracy ripple input circuit, where the ripple input circuit is feedback control separate from the feedback voltage node. Input the ripple voltage signal to a point in the loop. 4 is a schematic diagram of a constant on-time voltage regulator incorporating a ripple input control scheme with improved output voltage accuracy in accordance with one embodiment of the present invention. To simplify the discussion, the same components are given the same reference numerals in FIGS. 1 and 4.

Referring to FIG. 4, the buck switching regulator system 400 includes a buck switching regulator 400 (“buck regulator 400”) coupled to the output LC filter circuit. The buck regulator 400 receives an input voltage V _IN and supplies a switching output voltage V _SW (terminal 404) to an output LC filter circuit formed of an inductor L1 and an output capacitor C _OUT . The output LC filter circuit produces a DC output voltage V _OUT at an output voltage node 414 having a substantially fixed magnitude. In a practical implementation, the output voltage V _OUT is coupled to the drive load 416 as shown in FIG. 4. The output capacitor C _OUT is related to a specific amount of ESR, represented by a dotted line resistor ESR connected in series with the output capacitor. Using an output capacitor with zero ESR, the resistor ESR has a zero resistance and is therefore a short circuit.

The buck regulator 400 implements a constant on-time, variable off-time feedback control loop. The constant on-time feedback control loop of the buck regulator 400 operates in the same manner as the buck regulator 100 of FIG. 1 and will not be further described. Buck regulator 400 includes a ripple input circuit 420 that provides improved output voltage accuracy. The configuration and operation of the ripple input circuit 420 for inputting the desired amount of ripple into the feedback control loop and for enhancing output voltage accuracy will be described in detail later.

The buck switching regulator 400 includes a ripple input circuit with a feedforward capacitor C _FF to generate a given amount of ripple from the switching output voltage and input a ripple voltage signal into the feedback control loop of the buck switching regulator system 40. 420. More specifically, in the ripple input circuit 420, a ripple voltage signal is input at a point in the feedback control loop separately from the feedback voltage V _FB . The effect of voltage error due to the ripple voltage signal on the output voltage V _OUT is significantly reduced, which will be described in more detail below.

The ripple input circuit 420 includes an amplifier 450 inserted between the feedback voltage node 424 of the buck regulator 400 and the error comparator 426. Amplifier 450 is coupled to receive feedback voltage V _FB on the non-inverting input terminal and reference voltage V _REF on the inverting input terminal. The amplifier 450 generates an output voltage V _X at the output terminal 452 of the amplifier that represents the difference between the feedback voltage V _FB and the reference voltage V _REF . More specifically, output voltage V _OUT on node 414 is fed back to a voltage divider formed of resistors R1 and R2 through feedback terminal (FB) 408. The feedback voltage V _FB with the desired voltage level is produced at the output node 424 of the voltage divider consisting of resistors R1 and R2. The feedback voltage V _{FB, which} is the division voltage below the output voltage V _OUT , is compared with the reference voltage V _REF at the amplifier 450 to produce the output voltage V _X.

The output voltage V _X is then coupled to the inverting input terminal of the error comparator 426 and compared to the second reference voltage V _REF2 coupled to the non-inverting input terminal of the error comparator 426. Reference generator 436 generates reference voltages V _REF and V _REF2 . The second reference voltage V _REF2 is a DC voltage selected to bias the error comparator 426 and amplifier 450 to a suitable common mode level. The error comparator 426 finds the difference between the output voltage V _X and the second reference voltage V _REF2 , and generates an output voltage signal V _{COMP_OUT} indicating the difference between the voltage V _X and V _REF2 . Output voltage V _{COMP_OUT} is coupled to control circuit 432 to complete the constant on-time, variable off-time control loop of buck regulator 400. The control circuit 432 includes not only control logic circuits, but also timers for executing constant on-time and variable off-time control loops.

In this embodiment, the amplifier 450 is an amplifier with a large output impedance, such as a transconductance (Gm) amplifier. In addition, the amplifier 450 must be an amplifier having a high DC gain and an AC gain of one. In one embodiment, amplifier 450 is a low-Gm operational transconductance amplifier (OTA) with high output impedance. If the amplifier 450 has a high output impedance, the amplifier enables feedforward transmission of the ripple voltage signal input from the amplifier output terminal to the error comparator. If the amplifier 450 is implemented as an OTA, the buck switching regulator system 40 can preserve the good transient response and stability of the feedback control loop achieved in the buck switching regulator system 10 without additional amplifiers. Low-Gm OTA adds gain only at very low frequencies and has a gain of 1 at higher frequencies without degrading phase preservation.

The ripple input circuit 420 further includes a resistor R _INJ and a first capacitor C _INJ connected in series between the switching output voltage V _SW (node 422) and the output terminal 452 of the amplifier 450. do. The feedforward FFWD terminal 410 of the buck regulator 400 is also connected to the output terminal 452 of the amplifier 450. The output terminal 452 of the amplifier 450 becomes the ripple input node of the feedback control loop, and the ripple input node 452 is separated from the feedback voltage node 424. The amplifier 450 has a high output impedance that causes a ripple voltage signal to be input to the output terminal 452. When the feed forward capacitor C _{FF is} connected between the output voltage V _OUT (node 414) and the feed forward FFWD terminal 410 of the buck regulator 100, the feed forward capacitor C _FF is connected to the output voltage V _OUT ) (node 414) and ripple input node 452. If there is a ripple signal generated at the ripple input node 452, the amount is determined by the capacitance value of the feedforward capacitor C _FF .

The ripple input circuit 420 is coupled to the switching output voltage node 422 so that a ripple voltage signal is generated from the switching output voltage V _SW . In other words, the ripple voltage signal is a divided signal of the switching output voltage V _SW and is present at the switching frequency of the switching output voltage. By including a ripple input circuit and a feedforward capacitor C _FF , the buck regulator 400 of the present invention can be coupled to an output capacitor C _OUT having any ESR value. That is, a 0-ESR capacitor C _OUT , such as a ceramic capacitor, can be used as the output capacitor C _OUT to minimize the ripple voltage at the output voltage V _OUT . On the other hand, the ripple input circuit and feedforward capacitor of the present invention provide the necessary ripple for the feedback control loop. On the other hand, when a capacitor having a large ESR is used, the ripple input circuit of the present invention can be deactivated by the feedforward capacitor C _FF since no ripple generation is required.

The ripple voltage signal generated by the ripple input circuit 420 is determined by the resistance of the resistor R _INJ , the capacitance of the capacitor C _INJ , and the capacitance of the feedforward capacitor C _FF . Resistor R _INJ and capacitor C _INJ function as low pass filters, producing a ripple voltage at node 452 that is capacitively divided between capacitor C _INJ and capacitor C _FF . More specifically, the magnitude of the ripple voltage signal is given by (on-time) * (V _IN -V _OUT ) / R _INJ / (C _INJ + C _FF ). In this way, the switching output voltage V _SW is divided to produce a ripple voltage signal. In one embodiment, the ripple voltage has a peak-to-peak magnitude of approximately 20 mV.

The feedforward capacitor C _FF functions as a capacitive divider with a capacitor C _INJ . Thus, the peak-to-peak voltage of the ripple voltage signal is configured as a function of the capacitance value of the feedforward capacitor C _FF . Thus, the capacitance value of the feedforward capacitor C _FF is used to program the ripple input circuit so that the buck regulator 400 operates with the output capacitor C _OUT having any ESR value. More specifically, the feedforward capacitor C _FF is AC coupled between the output voltage V _OUT and the voltage V _X. If the capacitance of capacitor C _FF is very large, capacitor C _FF is a short circuit for an AC signal that may appear at output voltage V _OUT node 414. As such, the ripple input circuit is shorted by a large feedforward capacitor C _FF , and no ripple signal generated by the ripple input circuit is input to the ripple input node 452. Instead, the output voltage V _OUT is coupled to the voltage divider of the feedback control loop through the FB terminal 408 using a ripple voltage component. Thus, the pigback voltage V _FB is generated from the output voltage signal V _OUT with the required ripple.

On the other hand, if the capacitance of capacitor C _FF is very small or zero, capacitor C _FF is an open circuit for the AC signal that may appear on output voltage V _OUT node 114. In this case, the ripple signal generated by the ripple input circuits of the capacitors C _INJ and R _INJ is passed to the ripple input node 452 so that the maximum amount of ripple is provided to the feedback control loop.

Thus, in practical implementations, when an output capacitor C _OUT with a sufficiently large ESR is used, no ripple input circuit 420 is generated that generates any ripple voltage signal for the feedback control loop. If it does not require the ripple voltage signal from the ripple input circuit, there is a feed-forward capacitor (C _FF) having a large capacitance value using a large feed-forward capacitor (C _FF) is essentially a capacitor (C _INJ) effect of ripple input circuit The ripple signal generated by the ripple input circuit is shorted out and is invalidated by the feedforward capacitor C _FF .

On the other hand, when an output capacitor C _OUT having a small or zero ESR is used, the ripple input circuit 420 relies on providing the necessary ripple voltage signal for the feedback control loop. Thus, a feedforward capacitor C _FF having a small capacitance value is used to allow the ripple signal generated by the ripple input circuit 420 from the switching output voltage V _SW to pass through the ripple input node 452. . In this manner, the feedforward capacitor CFF operates to adjust the amount of ripple voltage to be provided by the ripple input circuit 420. In one embodiment, the feedforward capacitor CFF has a capacitance value in the range of 220 pF to 2.2 nF.

Thus, the buck regulator 400 can operate with an output capacitor having any ESR value by simply selecting the corresponding capacitance value for the feed forward capacitor. The ripple input circuit 420 of the buck regulator 400 realizes many of the same advantages as the ripple input circuit 420 buck regulator 100 described above and will not be described further herein.

As configured, the ripple input circuit 420 allows the buck regulator 400 to modify the feedback control loop. In operation, when the voltage V _X falls below the reference voltage V _REF2 , the high-side switch M1 is turned on for a fixed on-time t _ON . After a fixed on-time t _ON , the high-side switch M1 is turned off and the low-side switch M2 is turned on for at least the minimum off-time. When the voltage V _X falls below the reference voltage V _REF2 , the high-side switch M1 is turned on again. The ripple input circuit 420 inputs a ripple voltage signal to the output voltage V _X of the amplifier 450. That is, the ripple voltage signal is input after the gain stage of the amplifier 450.

As in the case of buck regulator 100, the voltage waveform of voltage V _X at the input of error comparator 426 will be asymmetrical with respect to V _REF2 , and the input voltage V _IN , output voltage V _OUT . And will change with the load current. However, an incorrect comparator input was moved to the ripple input node 452 instead of the feedback voltage node 424. The final voltage error at the feedback voltage node 424 is equal to the voltage error at the ripple input node divided by the gain of the amplifier 450. By inserting the gain stage of the amplifier 450, the DC error at the output voltage V _OUT is greatly reduced. More specifically, the offset error at the feedback voltage node is now 1 / A times the offset error of the average DC voltage of voltage V _X , where A is the DC gain of amplifier 450. The output voltage V _OUT experiences a DC error that is significantly reduced by the DC gain of the amplifier 450, and the output voltage can be adjusted with high accuracy. In one embodiment, the DC gain A of the amplifier 450 is greater than 600. Therefore, if the error voltage V _ERR2 is 10 mV, the DC resident voltage error appearing at the output voltage V _OUT becomes only 16 kV, which significantly reduces the error and significantly improves the accuracy.

Alternative embodiments

In some applications, the buck switching regulator system 40 can be adapted to operate in discrete conduction mode (DCM). In DCM, the low side switch M2 is not allowed to conduct current in the opposite direction. When the current flows in reverse, the low side switch M2 turns off and the output capacitor supplies the load current until the voltage V _X drops below the reference voltage V _REF2 , at which point the high side switch M1 is turned on again.

However, under very light load conditions, the feedback voltage V _FB may be greater than the reference voltage V _REF for a long period of time. During this period, amplifier 450 _pulls voltage V _X to a voltage level much higher than voltage V _REF2 . Then, when a load step is generated, V _X must decrease by a large amount of voltage before the feedback control loop turns high and the side switch turns on again. According to an alternative embodiment of the present invention, a clamp circuit is added to the ripple input circuit to limit the voltage swing of V _X , increasing the transient response of the buck regulator operating in DCM under varying load conditions.

5 is a schematic diagram of a fixed on-time voltage regulator including a ripple input control scheme with improved output voltage precision according to another embodiment of the present invention. Similar elements are shown by like reference numerals in FIGS. 4 and 5 to simplify the description. Referring to FIG. 5, the buck regulator 500 in the buck switching regulator system 50 is configured in the same manner as the buck regulator 400 of FIG. 4 except for the addition of the clamp circuit 560. Thus, the buck regulator 500 operates in the same manner as the buck regulator 400 except for the clamping operation and the detailed operation will not be described further. Clamp circuit 560 is coupled to ripple input node 552 and operates to limit voltage V _X at node 552 to an amount ΔV _X higher than reference voltage V _REF2 . Thus, the voltage V _X will not increase above V _REF2 + ΔV _X even under light load conditions. When a load step occurs, the voltage V _X should only decrease by the amount of voltage ΔV _X before the feedback control loop operates to turn on the high side switch. In one embodiment, the voltage amount ΔV _X is about 15 eV.

4 and 5, the feed forward capacitor C _FF is formed externally to the integrated circuits of the buck regulators 400 and 500 so that different capacitance values of the feed forward capacitor result in an ESR characteristic of the output capacitor C _OUT . It can be used to integrate with. Thus, the amount of input ripple voltage can be fine tuned by the feedforward capacitor C _FF . However, in other embodiments, the ripple input circuit and feedforward capacitor C _FF may be integrated in the buck regulator integrated circuit to reduce the number of external components in the buck switching regulator systems 40 and 50. When integrated, the feedforward capacitor C _FF may have a capacitance value suitable for a given range of ESR values of the output capacitor.

4 and 5, the ripple input circuit including the amplifiers 400, 500 and the voltage divider of resistors R1 / R2 are integrated on a unified integrated circuit of the buck regulators 400, 500. It is shown as. Clamp circuit 560 is also shown as being integrated on a unified integrated circuit of buck regulator 500. In this embodiment, one or more components of the ripple input circuit can be off chip formed from the integrated circuit of the buck regulator. The amount of integration of circuit elements on a single integrated circuit is a matter of design choice. The implementation of the ripple input circuit of the present invention is not limited to any particular degree of integration. In one embodiment, voltage dividers R1 / R2 and OTA are off chip formed from the integrated circuit of the buck regulator. In practice, any voltage divider R1 / R2, feedforward capacitor C _FF , operational transconductance amplifier, input capacitor C _INJ , resistor R _INJ and clamp circuit may be formed on chip or off chip from the buck regulator. The degree of precise integration is not critical to the practice of the present invention.

6 is a transistor level circuit diagram of an operational transconductance amplifier and clamp that can be incorporated into the fixed on-time voltage regulator of FIGS. 4 (without clamp circuit) and FIG. 5 according to one embodiment of the invention. Referring to FIG. 6, transistors M1, M2, M3, and M4 form an operational transconductance amplifier (OTA) 600 that receives a feedback voltage V _FB and a reference voltage V _REF and generates an output voltage V _X. OTA 600 has a high output impedance at output node 602 such that a ripple voltage signal can be input onto output voltage V _X.

In FIG. 6, OTA 600 is shown integrated with clamp circuit 620. Clamp circuit 620 is optional and not used in the implementation of the OTA of FIG. 4. The clamp circuit 620 is integrated when clamping of the output voltage V _X is required, as shown with reference to the embodiment of FIG. 5. The clamp circuit 620 includes an amplifier 622 that compares the output voltage V _X with the clamp voltage V _Clamp . The output signal from amplifier 622 drives the base terminal of NPN bipolar transistor Q1. Transistor Q1 is connected across output voltage V _X and ground voltage to maintain output voltage V _X at clamp voltage V _Clamp level. In one embodiment, the clamp voltage V _Clamp is set at V _REF2 + ΔV _X. FIG. 7 is a transistor level circuit diagram of a clamp circuit that may be used to implement the clamp circuit 620 of FIG. 6.

Multer mode on and off time control

In the buck regulator described above, fixed on-time control and variable off-time control schemes are applied to control the switching of the high side and low side swings. More specifically, the fixed on-time presented by equation (2) is a function of the input voltage V _IN . The duty cycle changes as the off-time is adjusted to an increasing amount from the minimum off-time while the buck regulator's operating frequency is stable. Under this operating range, even if the feedback voltage is lower than the reference voltage V _REF at a fixed on-time end, the high side switch is turned off and the low side switch has a minimum off-time before the high side switch can be turned on again. Is turned on. The requirement of the minimum off time is to guarantee a sufficient set time for the control circuit, in particular for the error comparator. In some cases, it is desirable for the high side switch to remain on until the feedback voltage reaches the reference voltage.

Also, ideally, although the buck regulator can reach up to 100% duty cycle, the minimum on-time requirement limits the buck regulator's duty cycle. The delay time to turn on and off the squelch also limits the duty cycle. In addition, if current sensing is required on the low side switch, such as current limiting or discontinuous conduction mode, sufficient time must be provided to perform the current sensing function. The maximum duty cycle achievable is then limited as follows.

On-the other hand it is possible, on increasing the maximum duty cycle by increasing the time t _ON - increasing the time t _ON may have undesirable results. First, increased on-time can result in higher inductor current ripple and may not always be practical. Secondly, on-time cannot be allowed to expand for too long. Although the on-time can be extended until the feedback voltage V _FB rises above the reference voltage V _REF , this condition can have undesirable consequences when short circuit conditions exist. Under short conditions, the feedback voltage cannot increase above the reference voltage and the high side switch is not turned off, resulting in extremely high inductor current. Finally, if the on-time is extended too much, poor transient response can result. Consider the situation where the load current is stepped from less current to more current. Because the current step causes the feedback voltage V _FB to drop below the reference voltage V _REF , the regulator control loop attempts to increase as much on-time t _ON as possible. If the on-time t _ON is increased too long, the inductor current will go higher than the load current and when the high side switch is last turned off and the low side switch is turned on, the energy stored in the inductor will cause the output voltage to overshoot its target. will overshoot).

According to the present invention, the buck switching regulator implements a multi-mode on and off time control scheme that implements a fixed on-time, variable off-time control loop. The multi-mode on and off time control scheme is implemented in the buck switching regulators of FIGS. 1, 4 and 5 to allow the buck switching regulator to operate at high duty cycles. 8 is a logic diagram of an on and off time control circuit implementing a multi-mode on and off time control scheme in a buck switching regulator in accordance with an embodiment of the present invention. In one embodiment, the on-time control circuit 800 is performed in the logic circuit 132 of the buck regulator 100 or in the control circuits 432 and 532 of the buck regulators 400 and 500 to enable multi-mode on and off in accordance with the present invention. Implement the time control scheme. It is important to understand that FIG. 8 is merely intended to illustrate the logical relationship between the different operating signals and the timers of the on-time control circuit and is not intended to merely illustrate the literal implementation of the on-time control circuit. Those skilled in the art will appreciate that on-time control circuitry may be implemented in a number of different ways using various circuit elements.

Referring to FIG. 8, the on-time control circuit 800 includes a first logic circuit 810 for generating a Top_Switch_On signal for turning on a high-side switch and a Top_Switch_Off signal for turning off a high-side switch. It includes a second logic circuit 820 to generate a. The multi-mode on and off time control scheme operates as follows. In the first logic circuit 810, the Top_Switch_On signal is asserted when the feedback voltage V _FB is less than the reference voltage V _REF and the minimum off-time has been reached. When the high-side switch is turned on, the Top_Switch_Off signal is asserted when the Normal_Off signal is asserted or when the Force_Off signal is asserted. If at least the minimum on-time t _on-min is reached and the feedback voltage V _FB is greater than or equal to the reference voltage V _REF , the Normal_Off signal is asserted. Thus, the high-side switch is turned on for at least the minimum on-time t _on-min and remains on until the feedback voltage V _FB is above the reference voltage V _REF . However, the on-time control circuit 800 adds two maximum on-time limits for the high-side switch. When the maximum on-time t _{on_max1} or the maximum on-time t _{on_max2} is reached, the Force_Off signal is asserted. When the Force_Off signal is asserted, the Top_Switch_Off signal is asserted and the high-side switch is turned off regardless of the feedback voltage (V _FB ) value. That is, when the Force_Off signal is asserted, the high-side switch is turned off even if the feedback voltage V _FB is less than the reference voltage.

Two maximum on-time limits provide a first maximum on-time t _{on_max1} and a second extended maximum on-time t _{on_max2} . That is, the second maximum on-time (t _{on_max2)} a first maximum on-time is greater than the time (t _{on_max1).} In operation, the first maximum on-time t _{on_max1} is applied, but under certain specific circumstances, the on-time is allowed to extend to the second maximum on-time t _{on_max2} . As described in more detail below, if the off-time in the previous switching cycle was not the minimum off-time, the first maximum on-time t _{on_max1} is selected but the off-time in the previous switching cycle is the minimum off-time. If so, the second maximum on-time t _{on_max2} is selected.

The multi-mode on and off time control scheme operates as follows. From the low duty cycle to the intermediate duty cycle, the on-time control circuit performs a fixed on-time and controls the off-time of the high-side switch to obtain a regulator. Next, in the high duty cycle, the off-time is fixed at the minimum off-time and the on-time control circuit controls the on-time to achieve regulation. In the limit, a maximum duty cycle of t _{on, max} / (t _{on, max} + t _{off, min} ) is realized, which maximum allowable cycle allows t _{on, max} to be selectively extended to large values under certain conditions. If it reaches 100%. Maximum on-time extension is implemented using two maximum on-times, where the second maximum on-time has a large value.

9 is a schematic diagram of a maximum on-time control circuit according to an embodiment of the present invention. Referring to FIG. 9, the maximum on-time control circuit 900 generates a Force-Off signal upon expiration of the first maximum on-time t _{on_max1} or the second maximum on-time t _{on_max2} . In the maximum on-time circuit 900, the first maximum on-time t _{on_max1} is set by the first timer circuit formed by the capacitor, the current source 960 and the NMOS transistor M11. In operation, when the high-side switch is turned off (when the Top_Switch_Off signal is asserted), transistor M11 is turned on to discharge capacitor C _X. Thus, the voltage V _TMAX at node 962 is at or near ground voltage. Comparator 940 compares capacitor voltage V _TMAX of capacitor C _X (node 962) with DC voltage V _DC . If the voltage V _TMAX is less than the _DC voltage V _DC , the comparator 940 generates a Force_Off signal with a logical low level.

Next, when the Top_Switch_Off signal is deasserted to turn on the high-side switch, transistor M11 is turned off and current source 960 is allowed to charge capacitor C _X. When the voltage V _TMAX at the top pole plate (node 962) of capacitor C _X reaches voltage V _DC , comparator 940 switches the state and generates a Force_Off signal with a logical high level. do. The logical high level of the Force_Off signal indicates that the Force_Off signal is asserted and the Top_Switch_Off signal is asserted accordingly. In this way, the capacitance of capacitor C _X or the time that capacitor Cx is charged to the VDC voltage establishes a first maximum on-time t _{on_max1} .

According to one embodiment of the present invention, the maximum on-time control circuit 900 provides a second extended maximum on-time t _{on_max2} under certain conditions. Under this condition, the maximum on-time is allowed to extend beyond the first maximum on-time t _{on_max1} when the minimum off-time is used in the previous switching cycle. To this end, the maximum on-time control circuit 900 includes a second timer circuit that operates to add a capacitor C _{Y in} parallel with the capacitor C _X when the minimum off-time was used in a previous switching cycle. do. The total capacitance provided by capacitor C _Y and capacitor C _X extends the time taken to charge voltage V _TMAX to DC voltage V _DC and thus the maximum on-time t _{on, max2} To extend. In the previous switching cycles, if the off-time is greater than the minimum off-time, the maximum on-time will not be extended and the maximum on-time added by the capacitor C _X will be maintained.

The configuration and operation of the second timer circuit will be described with reference to the timing diagrams of FIGS. 9 and 10. The second timer circuit includes a one-shot circuit 970 that receives the signal t _{off, min_reached} , which is asserted when the minimum off time is reached. The one shot circuit 970 generates t _{off, min_reached} pulses (waveform 1004). The t _{off, min_reached} pulse is logically ANDed with the Top_Switch_On signal indicating the turn-on of the high-side switch (AND gate 972). Thus, when the high-side switch is turned on simultaneously with the t _{off, min_reached} pulse, this indicates that the minimum off time was used in the previous switching cycle. Thus, the output of AND gate 972 is asserted. If the high-side switch is not turned on at the end of the minimum off-time, the output of AND gate 972 is not asserted.

The AND gate 972 drives the set input terminal of the set-reset flip-flop 974. The reset input terminal is driven by the Top_Switch_Off signal. The output signal Q of the set-reset flip flop 974 is an Increase_t _{on, max} signal connected to drive the gate terminal of the NMOS transistor M12. The drain terminal of the NMOS transistor M12 is connected to the node 962 while the source terminal is connected to the capacitor C _Y. When the Increase_t _{on, max} signal is asserted, transistor M12 is turned on to connect capacitor C _Y in parallel to capacitor C _X. If the Increase_t _{on, max} signal is not asserted, transistor M12 is turned off.

The Increase_t _{on, max} signal is asserted when AND gate 972 asserts its output signal to set output signal Q of flip flop 974 to logical high. When the Top_Switch_Off signal is asserted, the output signal Q of the flip flop 974 is reset to logic low. When neither the set input terminal nor the reset input terminal is asserted, the output signal Q of the flip flop 974 remains in the previous logic state.

The operation of the second timer circuit is as follows. When the maximum off-time is reached (time A), the t _{off, min_reached} signal is asserted and the one-shot circuit 970 generates a t _{off, min_reached} pulse (waveform 1004). The Top_Switch_On signal is then asserted to turn on the high-side switch (waveform 1002) at the same time, and the AND gate 972 asserts its output. Flip flop 974 is set accordingly, and the Increase_t _{on, max} signal (waveform 1006) is asserted. Transistor M12 is turned on and capacitor C _Y is connected in parallel with capacitor C _X to increase the maximum on-time. Due to the t _{off, min_reached} pulse, AND gate 972 _{asserts the} set input terminal only for the _duration of the t _{off, min_reached} pulse. However, the Increase_t _{on, max} signal remains asserted until the Top_Switch_Off signal is asserted (time B) to reset the Increase_t _{on, max} signal.

On the other hand, in the next switching cycle, when the minimum off-time is reached but the Top_Switch_On signal is not asserted (time C), AND gate 972 asserts its output signal. The Increase_t _{on, max} signal remains reset. That is, when the minimum off-time is reached but the high-side switch is not turned on, the maximum on-time control circuit 900 determines that the previous switching cycle does not include the minimum off-time. In such a case, extension of the maximum on type is unnecessary.

The maximum on-time control circuit 900, when implemented in a buck regulator, provides several benefits that improve the operation of the buck regulator. First, the maximum on-time control circuit 900 has two maximum on-times, one for maximum on-time t _{on_max1} and the other for extended maximum on-time t _{on_max2} . Extended maximum on-time is only provided under conditions when higher duty cycles are required. That is, the extended maximum on-time is provided when the previous switching cycle uses the minimum off-time. In low to medium duty cycles, the buck regulator is not affected by the two maximum on-times because the control loop controls off-times greater than the minimum off-time t _{off, min} . . In the high duty cycle, the buck regulator starts by controlling the on-time t _on using the minimum off-time t _{off, min} . In this regard, the on-time t _on is typically _extended until the feedback voltage V _FB reaches the reference voltage V _REF before the maximum on-time t on _max1 is reached. However, as the duty cycle continues to increase, the required on-time is greater than the first maximum on-time t _{on_max1} . In order that a higher duty cycle can be achieved, a second maximum on-time t on _max2 is used under certain conditions. Transient overshoots are avoided because the maximum on-time t _{on_max} is extended only when the previous switching cycle uses the minimum off-time. During transient conditions, the maximum on-time does not extend because the off-time is typically greater than the minimum off-time during the transient condition.

11 is a schematic diagram of a maximum on-time control circuit according to another embodiment of the present invention. Referring to FIG. 11, the maximum on-time control circuit 1100 is configured in the same manner as the maximum on-time control circuit 900 but has additional circuitry to prevent short circuit conditions. In particular, the maximum on-time control circuit 1100 is configured such that the maximum on-time extension is impossible when there is a short circuit condition. When there is a short circuit condition, the output current reaches the current limit. In the maximum on-time control circuit 1100, the Not_In_Current_Limit signal is connected to the AND gate 1172 and logically ANDed with t _{off, min_reached} pulses and Top_Switch_On pulses. Thus, in addition to the two previous conditions (minimum off-time reached and high-side switch turn on), AND gate 1172 sets the output signal to set flip-flop 1174 only when the output current is not current limited. Asserted, there is no short circuit at the output of the buck switching regulator. In this way, the maximum on-time does not extend when there is a shorting condition detected at the switching regulator.

The foregoing detailed description is provided to describe particular embodiments of the invention and is not intended to be limiting. Many variations and modifications are possible within the scope of the invention. The invention is defined by the appended claims.

1 is a schematic diagram of a fixed (fixed) on-time voltage regulator including a ripple input control scheme in accordance with an embodiment of the present invention.

FIG. 2 illustrates a fixed on-time and minimum off-time control loop used by the voltage regulator of FIG. 1. FIG.

3 shows a voltage waveform representing the feedback voltage V _FB of the fixed on-time voltage regulator of FIG. 1.

4 is a schematic diagram of a fixed on-time voltage regulator including a ripple input control scheme with improved output voltage accuracy in accordance with one embodiment of the present invention.

5 is a schematic diagram of a fixed on-time voltage regulator including a ripple input control scheme with improved output voltage accuracy in accordance with another embodiment of the present invention.

FIG. 6 is a transistor level circuit diagram of an operational transconductance amplifier and clamp that may be included in the fixed on-time voltage regulator of FIGS. 4 (excluding the clamp circuit) and FIG. 5 in accordance with an embodiment of the present invention.

7 is a transistor level circuit diagram of a clamp circuit that may be included within the fixed on-time voltage regulator of FIG. 5 in accordance with an embodiment of the present invention.

8 is a logic diagram of an on and off time control circuit for implementing a multi-mode on and off time control scheme in a buck switching regulator in accordance with an embodiment of the present invention.

9 is a schematic diagram of a maximum on-time control circuit in accordance with an embodiment of the present invention.

FIG. 10 is a timing diagram illustrating operation of the maximum on-time control circuit of FIG. 9. FIG.

11 is a schematic diagram of a maximum on-time control circuit according to another embodiment of the present invention.

Claims (12)

A buck switching regulator formed on an integrated circuit and receiving an input voltage, The buck switching regulator drives a switch output node to generate a switching output voltage by controlling a high-side switch and a low-side switch using a feedback control loop, the switch output node being Coupled to an LC filter circuit external to the integrated circuit to produce a regulated output voltage having a substantially constant magnitude on an output node, the regulated output voltage is fed back to the buck switching regulator to provide a feedback voltage node. A voltage divider that generates a feedback voltage on the phase, The buck switching regulator includes an on-time control circuit that generates a first signal for controlling the high side switch under a minimum on-time and variable off-time feedback control loop. and, The first signal turns off the high side switch upon expiration of a first on-time duration or upon expiration of a maximum on-time, the first on-time period being at least minimum Is on-time and extends to the maximum on-time when the feedback voltage remains below a reference voltage, the maximum on-time being a first maximum on-time and the first A second extended maximum on-time greater than the maximum on-time, The second extended maximum on-time is applied when a minimum off-time is used for the high side switch during the previous switching cycle. Buck switching regulator. The method of claim 1, The first maximum on-time is set by a first capacitor and the second maximum on-time is set by adding a second capacitor in parallel with the first capacitor. Buck switching regulator. The method of claim 1, The first maximum on-time is set by a first capacitance value and the second maximum on-time is set by adding a second capacitance value to the first capacitance value. Buck switching regulator. The method of claim 1, The second extended maximum on-time is applied when a minimum off-time is used on the high side during the previous switching cycle and when the output current of the switching regulator is not current limited. Buck switching regulator. The method of claim 1, The on-time control circuit comprises a maximum on-time control circuit for generating a second signal upon expiration of the first maximum on-time or the second maximum on-time, The maximum on-time control circuit is A first timer circuit comprising a first capacitor connected in parallel with a first transistor between a first node and a ground node, and a current source coupled to charge the first capacitor, wherein the first transistor is coupled to the first signal. Controlled by A comparator that compares a first voltage at the first node with a second DC reference voltage to produce an output voltage that is a second signal that is asserted when the first voltage is above the second DC reference voltage; , When the high side switch is turned off, the first signal is asserted to turn on the first transistor to discharge the first capacitor, and when the high side switch is turned on, the first signal turns the first transistor on. Deasserted to turn off so that the first capacitor can be charged by the current source, thereby increasing the first voltage, The first maximum on-time includes a period during which the first voltage reaches the second DC reference voltage. Buck switching regulator. The method of claim 5, wherein The maximum on-time control circuit further comprising a second timer circuit comprising a second transistor connected in series with a second capacitor between the first node and the ground node, The second transistor is controlled by a third signal, the third signal is asserted to turn on the second transistor when a minimum off-time is used in the high side switch during a previous switching cycle, The second transistor is turned on to connect the second capacitor in parallel with the first capacitor, The second maximum on-time includes a period during which the first voltage reaches the second DC reference voltage by charging the first and second capacitors. Buck switching regulator. The method of claim 6, The second timer circuit is A one-shot circuit for generating a minimum off-time pulse indicating that the minimum off-time is reached; A first logic gate that receives the minimum off-time pulse and a fourth signal and generates an output signal that is asserted when the fourth signal is asserted during the minimum off-time pulse; A set-reset flip having a set input terminal for receiving the output signal of the first logic gate, a reset input terminal for receiving the first signal, and an output terminal for generating the third signal Containing the flop Buck switching regulator. The method of claim 7, wherein The first logic gate further receives a fifth signal indicating that the output current of the switching regulator is not current limited, wherein the first logic gate is asserted during the minimum off-time pulse and the fourth signal Asserting the output signal when 5 signals are asserted Buck switching regulator. A method in a buck switching regulator that receives an input voltage and drives a switch output node to generate a switching output voltage by controlling a high side switch and a low side switch using a feedback control loop, the switch output node being an LC filter circuit. Coupled to generate a regulated output voltage having a substantially constant magnitude on an output node, the regulated output voltage fed back to the buck switching regulator and supplied to a voltage divider that generates a feedback voltage on a feedback voltage node. As Providing the high side switch with a first on-time period that is at least minimum on-time and extends to a maximum on-time when the feedback voltage is maintained below a reference voltage; Providing, as the maximum on-time, a first maximum on-time or a second extended maximum on-time greater than the first maximum on-time; Applying the first maximum on-time when a minimum off-time has not been used for the high side switch during a previous switching cycle; Applying the second extended maximum on-time when a minimum off-time was used for the high side switch during the previous switching cycle; Generating a first signal for turning off the high side switch under a minimum on-time and variable off-time feedback control loop, wherein the first signal is upon expiration of the first on-time period or the first Or turning off the high side switch upon expiration of a second maximum on-time. Way. The method of claim 9, Providing the first maximum on-time comprises providing the first maximum on-time by charging a first capacitor, Providing the second extended maximum on-time may include providing the second extended maximum on-time by charging the first capacitor and a second capacitor connected in parallel with the first capacitor. Containing Way. The method of claim 9, Providing the first maximum on-time comprises providing the first maximum on-time by charging a first capacitance value, Providing the second extended maximum on-time may include providing the second extended maximum on-time by charging a second capacitance value that is a sum of the first capacitance value and a third capacitance value. Containing Way. The method of claim 9, Providing a second extended maximum on-time greater than the first maximum on-time is such that when a minimum off-time is used for the high side switch during a previous switching cycle and the output current of the switching regulator is current limited. Providing the second extended maximum on-time when not Way.

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