CN118039701A - High-heat-conductivity gallium oxide transistor and preparation method thereof - Google Patents
High-heat-conductivity gallium oxide transistor and preparation method thereof Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 132
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 132
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 239000010408 film Substances 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000012298 atmosphere Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- -1 silicon ions Chemical class 0.000 claims description 4
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000001017 electron-beam sputter deposition Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000009616 inductively coupled plasma Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000002207 thermal evaporation Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 70
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000003949 trap density measurement Methods 0.000 abstract description 3
- 239000002346 layers by function Substances 0.000 abstract description 2
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 24
- 238000010586 diagram Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
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Abstract
A high heat conduction gallium oxide transistor and a preparation method thereof belong to the technical field of semiconductor device preparation. The preparation method comprises (1) bonding a gallium oxide film layer on a high heat conduction substrate by hydrogen ion implantation and stripping technology; (2) Epitaxially growing a high-quality functional layer on the gallium oxide film layer; (3) ohmic contact electrode preparation; (4) depositing a gate dielectric layer; (5) gate electrode preparation; and (6) etching the dielectric hole. Aiming at the problems of high trap density, low breakdown voltage, serious current collapse and the like of the existing gallium oxide heterogeneous integrated transistor, the invention develops the gallium oxide transistor with high heat conduction capability and high crystal quality epitaxial layer based on gallium oxide heterogeneous bonding and epitaxial growth technology, and has the advantages of few traps of a gallium oxide channel layer, high device breakdown voltage, good heat dissipation performance, low device junction temperature, high current density and power density, good high-temperature stability and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a high-heat-conductivity gallium oxide transistor and a preparation method thereof.
Background
The ultra-wide band gap semiconductor gallium oxide has excellent material characteristics of large band gap, high breakdown field strength, large single crystal size and the like, and is a preferable material for preparing high-voltage, high-frequency and high-power electronic devices. However, the thermal conductivity of gallium oxide is extremely low, and a transistor prepared by using a gallium oxide substrate has serious self-heating effect, so that the junction temperature of the device can be increased sharply along with the increase of the power density, and the performance of the device is degraded or even fails.
At present, the heat dissipation problem of the gallium oxide transistor is solved by adopting heterogeneous integration of a high-heat-conductivity substrate and a gallium oxide film, but a large number of defects exist on the surface and in the interior of the gallium oxide film obtained by means of hydrogen ion implantation, mechanical stripping and the like, and the transistor prepared by directly adopting the gallium oxide layer has serious trap effect, so that the improvement of the breakdown voltage, the output power and other performances of the gallium oxide transistor is severely restricted. Therefore, the invention develops the high-heat-conductivity gallium oxide transistor and the preparation method thereof based on gallium oxide heterojunction bonding and high-quality epitaxial growth technology, and the technology can improve the crystal quality of a gallium oxide epitaxial layer and the heat dissipation capacity of the gallium oxide transistor, thereby realizing the high-heat-conductivity gallium oxide transistor with strong heat dissipation capacity, strong power bearing capacity, high frequency performance and good high-temperature stability.
Disclosure of Invention
The technical problems to be solved are as follows: aiming at the problems of high trap density, low breakdown voltage, serious current collapse and the like of the existing gallium oxide heterogeneous integrated transistor, the invention provides a high-heat-conductivity gallium oxide transistor and a preparation method thereof, and the developed device has the characteristics of strong heat radiation capability, high breakdown voltage, strong power bearing capability, high frequency performance and good high-temperature stability through the heterogeneous bonding of a high-heat-conductivity substrate and gallium oxide and the high-quality epitaxial growth technology of gallium oxide, and can be applied to the development and production of gallium oxide power electronic devices and radio frequency devices.
The technical scheme is as follows: a high thermal conductivity gallium oxide transistor comprising:
A high thermal conductivity substrate;
The gallium oxide film layer is positioned on the upper surface of the high-heat-conductivity substrate;
an unintentionally doped gallium oxide layer positioned on the surface of the gallium oxide film layer;
the doped gallium oxide layer is positioned on the surface of the unintentionally doped gallium oxide layer, and two sides of the doped gallium oxide layer are provided with two heavily doped regions which are symmetrically distributed;
gallium oxide ohmic contact metal arranged on the surface of the heavily doped region;
The gate dielectric layer is positioned on the surfaces of the doped gallium oxide layer and the gallium oxide ohmic contact metal, and a dielectric hole area is formed in the gate dielectric layer;
And the gate metal is positioned on the surface of the gate dielectric layer.
Preferably, the high heat conduction substrate is diamond, silicon carbide, aluminum nitride or boron nitride, and the thickness is 100-1000 mu m.
Preferably, the gallium oxide film layer is a Fe doped or unintentionally doped gallium oxide film, and the thickness is 10-500 nm.
Preferably, the thickness of the unintentionally doped gallium oxide layer is between 0nm and 5 mu m, and the doping concentration is less than 1E17cm -3.
Preferably, the thickness of the doped gallium oxide layer is 2 nm-1 μm, the doping atoms are silicon or germanium, and the doping concentration is 1E16 cm -3～1E20 cm-3; the heavily doped region is a doped region formed on the originally doped gallium oxide layer by silicon ion implantation with a silicon ion implantation dose of 1E13cm -2～1E16cm-2.
Preferably, the gallium oxide ohmic contact metal is at least one of Ti, al, au, pt, ni, mo, cu, ag, pd, W and Fe, and the thickness is 10 nm-1 μm; the gate dielectric layer is at least one of Al 2O3、TiO2、HfO2、AlN、Si3N4 and SiO 2, and the thickness is 5 nm-100 nm; the gate metal is at least one of Ti, au, pt, al, W, ni, cu and Fe, and the thickness is 20-800 nm.
Based on the preparation method of the gallium oxide transistor with high heat conduction, the preparation method comprises the following steps:
step one, bonding a gallium oxide film layer on a high-heat-conductivity substrate through conventional hydrogen ion implantation and stripping technologies;
Sequentially growing an unintentionally doped gallium oxide layer and a doped gallium oxide layer on the gallium oxide film layer;
Step three, defining a source and drain region by using photoresist through conventional photoetching and developing processes, performing silicon ion implantation by using the photoresist as a mask to form a heavily doped region, and performing high-temperature annealing on a sample after removing the photoresist through an organic solution (acetone) to activate silicon ions;
Defining a source-drain region by using a photoresist mask, depositing gallium oxide ohmic contact metal on the heavily doped region, stripping by using an organic solution (acetone) to form an ohmic electrode, and annealing to form ohmic contact to obtain a sample;
depositing a gate dielectric layer on the upper surface of the sample;
Step six, defining a gate region by using photoresist through conventional photoetching and developing processes, then depositing gate metal, and stripping by using an organic solution (acetone) to form a gate electrode;
and step seven, defining a dielectric hole area by using photoresist through conventional photoetching and developing processes, etching off a dielectric in a dielectric hole, and removing the photoresist through an organic solution (acetone) to finally obtain the high-heat-conductivity gallium oxide transistor.
Preferably, the growth mode of the unintentionally doped gallium oxide layer and the doped gallium oxide layer in the second step is Molecular Beam Epitaxy (MBE), metal organic chemical vapor phase epitaxy (MOCVD), hydride Vapor Phase Epitaxy (HVPE), atomized vapor phase epitaxy (mist-CVD) or laser pulse deposition (PLD).
Preferably, the energy of the silicon ion implantation in the third step is between 10keV and 100keV, the annealing atmosphere is one of nitrogen, argon or oxygen, the annealing temperature is between 700 ℃ and 1000 ℃, and the annealing time is between 10s and 1 h.
Preferably, the annealing atmosphere in the fourth step is nitrogen, the annealing temperature is between 400 ℃ and 800 ℃, and the annealing time is between 10s and 30 min; the deposition mode in the fifth step is atomic layer deposition, plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, thermal evaporation, electron beam evaporation or sputtering; in the seventh step, inductively Coupled Plasma (ICP), reactive Ion Etching (RIE) or wet etching is used to etch the medium in the dielectric hole.
The beneficial effects are that: in the prior art, gallium oxide is directly bonded to a SiC or diamond substrate, and a large number of traps exist in and on the gallium oxide, so that the device is serious in current collapse and low in breakdown voltage, and the current density and the power density of the device are affected.
Compared with the prior art, the invention has the advantages that: (1) few traps of a gallium oxide channel layer; (2) high device breakdown voltage; (3) the heat dissipation performance of the device is good; (4) low junction temperature of the device; (5) high current density and power density; (6) high temperature stability.
Drawings
Fig. 1 is a schematic structural diagram of a high thermal conductivity gallium oxide transistor according to the invention;
FIG. 2 is a schematic diagram of the structure of step (1) of embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of the structure of the process of step (2) in example 1 of the present invention;
FIG. 4 is a schematic diagram of the structure of the process of step (3) of example 1 of the present invention;
FIG. 5 is a schematic diagram of the structure of the process of step (4) of example 1 of the present invention;
FIG. 6 is a schematic diagram of the structure of the process of step (6) in example 1 of the present invention.
The numerical references in the drawings are as follows: 1. a high thermal conductivity substrate; 2. a gallium oxide thin film layer; 3. an unintentionally doped gallium oxide layer; 4. a doped gallium oxide layer; 5. a photoresist; 6. a heavily doped region; 7. gallium oxide ohmic contact metal; 8. a gate dielectric layer; 9. a gate metal.
Detailed Description
The invention is further described below with reference to the drawings and specific embodiments.
In the examples of this specification, unless otherwise specified, the starting materials were all from common commercial products.
Bonding a gallium oxide film layer on a high-heat-conductivity substrate through a hydrogen ion implantation and stripping technology; epitaxially growing a high-quality functional layer on the gallium oxide film layer; ohmic contact electrode preparation; depositing a gate dielectric layer; preparing a gate electrode; and etching the dielectric hole. Aiming at the problems of high trap density, low breakdown voltage, serious current collapse and the like of the existing gallium oxide heterogeneous integrated transistor, the invention develops the gallium oxide transistor with high heat conduction capacity and high crystal quality epitaxial layer based on gallium oxide heterogeneous bonding and epitaxial growth technology, and has the advantages of few traps of a gallium oxide channel layer, high device breakdown voltage, good device heat dissipation performance, low device junction temperature, high current density and power density, good high-temperature stability and the like. The method comprises the following steps:
As shown in fig. 1, fig. 1 is a schematic structural diagram of a high thermal conductivity gallium oxide transistor according to an embodiment of the present invention, where the high thermal conductivity gallium oxide transistor includes: a high thermal conductivity substrate 1; the gallium oxide film layer 2 is positioned on the upper surface of the high-heat-conductivity substrate 1; an unintentionally doped gallium oxide layer 3 located on the surface of the gallium oxide thin film layer 2; the doped gallium oxide layer 4 is positioned on the surface of the unintentionally doped gallium oxide layer 3, and two sides of the doped gallium oxide layer 4 are provided with two heavily doped regions 6 which are symmetrically distributed; gallium oxide ohmic contact metal 7 arranged on the surface of the heavily doped region 6; the gate dielectric layer 8 is positioned on the surfaces of the doped gallium oxide layer 4 and the gallium oxide ohmic contact metal 7, and a dielectric hole area is arranged on the gate dielectric layer 8; and the gate metal 9 is positioned on the surface of the gate dielectric layer 8.
As one preferred embodiment of the present invention, the high thermal conductivity substrate 1 is diamond, silicon carbide, aluminum nitride or boron nitride, and has a thickness of 100-1000 μm.
As one preferred embodiment of the present invention, the gallium oxide thin film layer 2 is a Fe doped or unintentionally doped gallium oxide thin film, and has a thickness of 10-500 nm.
As one of the preferred embodiments of the present invention, the thickness of the unintentionally doped gallium oxide layer 3 is between 0nm and 5 μm, and the doping concentration is less than 1E17cm -3.
As one of the preferred embodiments of the present invention, the thickness of the doped gallium oxide layer 4 is 2 nm-1 μm, the doping atoms are silicon or germanium, and the doping concentration is 1E16cm -3～1E20cm-3; the heavily doped region 6 is a doped region formed on the originally doped gallium oxide layer 4 by silicon ion implantation with a silicon ion implantation dose of 1E13cm -2～1E16cm-2.
As one preferred embodiment of the invention, the gallium oxide ohmic contact metal 7 is at least one of Ti, al, au, pt, ni, mo, cu, ag, pd, W and Fe, and has a thickness of 10nm to 1 μm.
As one preferred embodiment of the present invention, the gate dielectric layer 8 is at least one of Al 2O3、TiO2、HfO2、AlN、Si3N4 and SiO 2, and has a thickness of 5-100 nm.
As one preferred embodiment of the present invention, the gate metal 9 is at least one of Ti, au, pt, al, W, ni, cu and Fe, and has a thickness of 20 to 800nm.
Based on the preparation method of the gallium oxide transistor with high heat conduction, the preparation method comprises the following steps:
Step one, bonding a gallium oxide film layer 2 on a high heat conduction substrate 1 through conventional hydrogen ion implantation and stripping technology;
sequentially growing an unintentionally doped gallium oxide layer 3 and a doped gallium oxide layer 4 on the gallium oxide film layer 2;
Step three, defining a source and drain region by using a photoresist 5 through a conventional photoetching and developing process, performing silicon ion implantation by taking the photoresist 5 as a mask to form a heavily doped region 6, and performing high-temperature annealing on a sample to activate silicon ions after removing the photoresist 5 by using an organic solution (acetone);
Defining a source-drain region by using a photoresist mask, depositing gallium oxide ohmic contact metal 7 on the heavily doped region 6, stripping by using an organic solution (acetone) to form an ohmic electrode, and annealing to form ohmic contact to obtain a sample;
Depositing a gate dielectric layer 8 on the upper surface of the sample;
Step six, defining a gate region by using photoresist through conventional photoetching and developing processes, then depositing gate metal 9, and stripping by using an organic solution (acetone) to form a gate electrode;
and step seven, defining a dielectric hole area by using photoresist through conventional photoetching and developing processes, etching off a dielectric in a dielectric hole, and removing the photoresist through an organic solution (acetone) to finally obtain the high-heat-conductivity gallium oxide transistor.
As one of the preferred embodiments of the present invention, the growth mode of the unintentionally doped gallium oxide layer 3 and the doped gallium oxide layer 4 in the second step is Molecular Beam Epitaxy (MBE), metal organic chemical vapor epitaxy (MOCVD), hydride Vapor Phase Epitaxy (HVPE), atomized vapor phase epitaxy (mist-CVD) or laser pulse deposition (PLD).
As one preferred embodiment of the invention, the energy of the silicon ion implantation in the third step is between 10keV and 100keV, the annealing atmosphere is one of nitrogen, argon or oxygen, the annealing temperature is between 700 ℃ and 1000 ℃, and the annealing time is between 10s and 1 h.
As one preferable embodiment of the invention, the annealing atmosphere in the fourth step is nitrogen, the annealing temperature is between 400 ℃ and 800 ℃, and the annealing time is between 10s and 30 min; the deposition mode in the fifth step is atomic layer deposition, plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, thermal evaporation, electron beam evaporation or sputtering; in the seventh step, inductively Coupled Plasma (ICP), reactive Ion Etching (RIE) or wet etching is used to etch the medium in the dielectric hole.
The invention is further described below in connection with specific examples.
Example 1
The preparation method of the gallium oxide transistor with high heat conductivity in the embodiment is based on the above method, and specifically comprises the following steps:
(1) Bonding a 50nm thick Fe doped gallium oxide film layer 2 on a high thermal conductivity diamond substrate 1 by conventional hydrogen ion implantation and stripping technology, wherein the Fe doping concentration of the embodiment is 1E19 cm -3 (optionally, the Fe doping concentration ranges from 1E16 cm -3 to 1E20 cm -3) as shown in FIG. 2;
(2) A 200nm thick unintentionally doped gallium oxide layer 3 and a 200nm thick silicon doped gallium oxide layer 4 (i.e. a channel) are sequentially grown on the gallium oxide thin film layer 2, a sample structure diagram is shown in fig. 3, wherein the doping concentration of the unintentionally doped gallium oxide layer 3 is less than 1E16cm -3, and the doping concentration of the silicon doped gallium oxide layer 4 is 4E17cm -3;
(3) Defining a source-drain region (a region without photoresist coverage in fig. 4 is a source-drain region) by using a conventional photoetching and developing process, performing silicon ion implantation by using the photoresist 5 as a mask, forming a heavily doped region 6 with the implantation energy of 60keV and the dosage of 1E14cm -2, removing the photoresist 5 by using an organic solution such as acetone and the like for a sample structure shown in fig. 4, and annealing for 10min in a nitrogen atmosphere at 950 ℃ to activate silicon ions;
(4) Defining a source-drain region by using a photoresist mask, then depositing Ti/Au ohmic contact metal 7 with the thickness of 20/200nm, stripping by using organic solution such as acetone to form an ohmic electrode (namely a source/drain electrode), and annealing for 3min in nitrogen atmosphere at 470 ℃ to form ohmic contact, wherein a sample structure diagram is shown in FIG. 5;
(5) Depositing a layer of Al 2O3 gate dielectric layer 8 with the thickness of 20nm on the surface of a sample by adopting an atomic layer deposition technology;
(6) Defining a gate region by using photoresist through conventional photoetching and developing processes, then depositing Ni/Au gate metal 9 with the thickness of 20/300nm, stripping by using organic solution such as acetone and the like to form a gate electrode, wherein a sample structure diagram is shown in FIG. 6;
(7) The dielectric hole area is defined by photoresist through conventional photoetching and developing processes (the area which is not covered by the Al 2O3 gate dielectric layer 8 in fig. 1 is the dielectric hole area, before Al 2O3 is etched, the photoresist is protected outside the dielectric hole, and the dielectric hole area is defined by the photoresist, so that the dielectric hole area is defined by the photoresist), the Al 2O3 dielectric in the dielectric hole is etched, the photoresist is removed through organic solution such as acetone, and the structure diagram of the device is shown in fig. 1.
It should be understood that the particular embodiments described herein are illustrative only and are not limiting upon the invention. The manufacturing method can adopt a plurality of manufacturing schemes, and all equivalent changes and decorations according to the claims of the invention belong to the coverage of the invention.
Claims (10)
1. A high thermal conductivity gallium oxide transistor, comprising:
A high thermal conductivity substrate (1);
the gallium oxide film layer (2) is positioned on the upper surface of the high-heat-conductivity substrate (1);
an unintentionally doped gallium oxide layer (3) positioned on the surface of the gallium oxide film layer (2);
The doped gallium oxide layer (4) is positioned on the surface of the unintentionally doped gallium oxide layer (3), and two heavily doped regions (6) which are symmetrically distributed are arranged on two sides of the doped gallium oxide layer (4);
gallium oxide ohmic contact metal (7) arranged on the surface of the heavily doped region (6);
The gate dielectric layer (8) is positioned on the surfaces of the doped gallium oxide layer (4) and the gallium oxide ohmic contact metal (7), and a dielectric hole area is arranged on the gate dielectric layer (8);
and the gate metal (9) is positioned on the surface of the gate dielectric layer (8).
2. A high thermal conductivity gallium oxide transistor according to claim 1, wherein the high thermal conductivity substrate (1) is diamond, silicon carbide, aluminum nitride or boron nitride, and has a thickness of 100-1000 μm.
3. A high thermal conductivity gallium oxide transistor according to claim 1, wherein the gallium oxide thin film layer (2) is a Fe doped or unintentionally doped gallium oxide thin film having a thickness of 10-500 nm.
4. A high thermal conductivity gallium oxide transistor according to claim 1, wherein the thickness of the unintentionally doped gallium oxide layer (3) is between 0nm and 5 μm, the doping concentration being less than 1E17cm -3.
5. The high thermal conductivity gallium oxide transistor according to claim 1, wherein the thickness of the doped gallium oxide layer (4) is 2 nm-1 μm, the doping atoms are silicon or germanium, and the doping concentration is 1e16 cm -3～1E20 cm-3; the heavily doped region (6) is a doped region formed on the originally doped gallium oxide layer (4) through silicon ion implantation, wherein the silicon ion implantation dosage of the doped region is 1E13cm -2～1E16cm-2.
6. The high thermal conductivity gallium oxide transistor according to claim 1, wherein the gallium oxide ohmic contact metal (7) is at least one of Ti, al, au, pt, ni, mo, cu, ag, pd, W and Fe, and has a thickness of 10nm to 1 μm; the gate dielectric layer (8) is at least one of Al 2O3、TiO2、HfO2、AlN、Si3N4 and SiO 2, and the thickness is 5 nm-100 nm; the gate metal (9) is at least one of Ti, au, pt, al, W, ni, cu and Fe, and the thickness is 20-800 nm.
7. The preparation method of the high-heat-conductivity gallium oxide transistor based on the method of claim 1 is characterized by comprising the following steps:
step one, bonding a gallium oxide film layer (2) on a high heat conduction substrate (1) through conventional hydrogen ion implantation and stripping technology;
Sequentially growing an unintentionally doped gallium oxide layer (3) and a doped gallium oxide layer (4) on the gallium oxide film layer (2);
defining a source and drain region by using a photoresist (5) through a conventional photoetching and developing process, performing silicon ion implantation by taking the photoresist (5) as a mask to form a heavily doped region (6), removing the photoresist (5) through an organic solution, and performing high-temperature annealing on a sample to activate silicon ions;
defining a source-drain region by using a photoresist mask, then depositing gallium oxide ohmic contact metal (7) on the heavily doped region (6), stripping by using an organic solution to form an ohmic electrode, and annealing to form ohmic contact to obtain a sample;
depositing a gate dielectric layer (8) on the upper surface of the sample;
Step six, defining a gate region by using photoresist through conventional photoetching and developing processes, then depositing gate metal (9), and stripping by using an organic solution to form a gate electrode;
and step seven, defining a dielectric hole area by using photoresist through conventional photoetching and developing processes, etching off the dielectric in the dielectric hole, and removing the photoresist through an organic solution to finally obtain the gallium oxide transistor with high heat conductivity.
8. The method according to claim 7, wherein the growth of the unintentionally doped gallium oxide layer (3) and the doped gallium oxide layer (4) in the second step is molecular beam epitaxy, metal organic chemical vapor phase epitaxy, hydride vapor phase epitaxy, atomized vapor phase epitaxy or laser pulse deposition.
9. The method of manufacturing a high thermal conductivity gallium oxide transistor according to claim 7, wherein the energy of the silicon ion implantation in the third step is between 10keV and 100keV, the annealing atmosphere is one of nitrogen, argon or oxygen, the annealing temperature is between 700 ℃ and 1000 ℃, and the annealing time is between 10s and 1 h.
10. The method of manufacturing a high thermal conductivity gallium oxide transistor according to claim 7, wherein the annealing atmosphere in the fourth step is nitrogen, the annealing temperature is 400 ℃ to 800 ℃, and the annealing time is 10s to 30 min; the deposition mode in the fifth step is atomic layer deposition, plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, thermal evaporation, electron beam evaporation or sputtering; and in the seventh step, inductively coupled plasma, reactive ion etching or wet etching is adopted to etch the medium in the medium hole.
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| CN202410326001.9A Pending CN118039701A (en) | 2024-03-21 | 2024-03-21 | High-heat-conductivity gallium oxide transistor and preparation method thereof |
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