CN114497192B - RESFET device and preparation method thereof - Google Patents

RESFET device and preparation method thereof Download PDF

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Publication number
CN114497192B
CN114497192B CN202111638719.4A CN202111638719A CN114497192B CN 114497192 B CN114497192 B CN 114497192B CN 202111638719 A CN202111638719 A CN 202111638719A CN 114497192 B CN114497192 B CN 114497192B
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nanowire
substrate
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oxide layer
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CN114497192A (en
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黄双武
高麟飞
林峰
吴钧烨
黎晓华
刘新科
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Shenzhen University
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

Compared with the prior art, the RESFET device has the advantages of lower static power consumption, lower time delay, reduced device volume and improved integration level. The upper surface, the lower surface and the side surfaces of the nanowire form channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated gate-all-around and the comprehensive performance of the multi-layer nanowire are further improved. The nanowire with narrow width is adopted, so that the method has the characteristic of low power consumption. Compared with the traditional vertical FinFET device, the heat dissipation can be effectively realized, the normal operation can be realized for a longer time, and the output current density is higher. The preparation method of the RESFET device improves the device performance, improves the device integration level, reduces the energy consumption, and simultaneously adopts the technical means without any threshold, thereby being suitable for large-scale popularization and application.

Description

RESFET device and preparation method thereof
Technical Field
The invention belongs to the field of device manufacturing in semiconductor technology, and particularly relates to a RESFET device and a preparation method thereof.
Background
The GaN-based material has a series of material performance advantages of large forbidden bandwidth, high breakdown field intensity, high polarization coefficient, high electron mobility, high electron saturation drift speed and the like, is a preferred material for preparing a new generation of high-performance power electronic devices, and has important application prospect. GaN-based materials are attractive for both optoelectronic and microelectronic devices. The GaN-based material has the characteristics of bandwidth inhibition, high breakdown voltage, high electron saturation drift speed, good thermal stability and the like, and can form an ideal heterojunction with the AlGaN alloy material, the large conduction band offset on the heterojunction interface and the piezoelectric polarization and spontaneous polarization intensity of the GaN-based material can generate high-density two-dimensional electron gas, and the electron gas density is about one order of magnitude higher than that of the AlGaAs/GaAs heterojunction, so that the GaN-based material is suitable for manufacturing high-temperature, high-frequency and high-power electronic devices.
In recent years, wide bandgap gallium nitride (GaN) has become a well-known semiconductor in the application fields of power and radio frequency devices due to its superior material properties. The FinFET vertical nanowire complementary metal semiconductor Field effect transistor (Fin Field-Effect Transistor, finFET for short) with the three-dimensional structure has excellent gate controllability, and is highly valued and widely applied. The existing FinFET has the outstanding characteristics that: (1) The on and off of the control circuits at the two sides of the grid electrode are realized. (2) In the FinFET structure, the gate is designed into a fork-shaped 3D structure similar to a fin, so that leakage current can be greatly improved and reduced, and the gate length of the transistor can be greatly shortened. And (3) the method has the advantages of low power consumption and small area.
The existing FinFET also has obvious defects: due to the narrow channel width, the current density is extremely high, the efficiency is low, and the function is single.
High heat is generated and the GaN channel cannot effectively dissipate heat, resulting in an increase in the temperature inside the channel, resulting in deterioration of device performance (self-heating effect). Therefore, it is necessary to rationally design a RESFET device and a matched and practical manufacturing method to overcome the defects of the prior art.
Disclosure of Invention
The invention aims to provide a RESFET device to solve the technical problems of large size, high energy consumption and insufficient integration of the existing RESFET device.
The invention also aims to provide a preparation method of the RESFET device, so as to supplement the preparation method of the RESFET device with high integration level.
To achieve the above object, an aspect of the present invention provides a resufet device, comprising:
a MOS tube part and a RES part;
wherein the MOS transistor portion includes: an n-type GaN substrate;
a first n-type GaN nanowire bonded to a surface of the n-type GaN substrate;
an aluminum oxide layer bonded to the n-type GaN substrate and divided into two portions spaced apart from each other by the first n-type GaN nanowire, the two portions of the aluminum oxide layer spaced apart from each other forming a plane with the first n-type GaN nanowire;
the first metal electrode layer is attached to the surface of the n-type GaN substrate, which is away from the plane formed by the aluminum oxide layer and the first n-type GaN nanowire;
the first oxide layer is combined on the surface of the first metal electrode layer, which is away from the surface of the n-type GaN substrate;
a second GaN nanowire bonded to the first oxide layer away from the n-type GaN substrate surface;
the second oxide layer is combined with the first oxide layer and deviates from the surface of the n-type GaN substrate, and the second oxide layer and the first oxide layer tightly wrap the second GaN nanowire to form an oxide wrapping layer;
the second metal electrode layer is combined with the surface of the second oxide layer, which is away from the first oxide layer, and the second metal electrode layer and the first metal electrode layer tightly wrap the oxide wrapping layer;
two ends of the second GaN nanowire are respectively provided with an ohmic electrode;
the RES section includes:
a substrate layer;
the metal film layer is combined on one surface of the substrate and divided into two parts which are separated from each other and respectively named as a first metal film layer and a second metal film layer;
the liner layers are respectively combined with the first metal film layer which is away from the surface of the substrate and the second metal film layer which is away from the surface of the substrate, two liner layers which are spaced from each other are respectively arranged on the first metal film layer and the second metal film layer, an outer liner is arranged close to the edge of the metal film, and an inner liner is arranged close to a spacing area formed by the first metal film and the second metal film;
a polysilicon germanium thin film layer in ohmic contact with the inner side of the liner;
and the substrate layer of the RES part is attached to the surface of the n-type GaN substrate, which is formed by the aluminum oxide layer of the MOS tube part and the first n-type GaN nanowire, and the surface of the n-type GaN substrate is deviated from the surface of the n-type GaN substrate.
Preferably, the material of the MOS tube substrate can be replaced by SiC; the RES tube substrate material may be replaced with SiO2.
Preferably, the material of the first oxide layer and the second oxide layer is Al2O3 or SiO2.
Preferably, the materials of the first metal electrode layer, the second metal electrode layer and the metal film layer are any one of Cr, ti and Al.
Preferably, the thickness of the n-type GaN substrate is 300 μm;
the thickness of the first n-type GaN nanowire is 50nm, and the width is 10-100nm:
the thickness of the alumina layer is 50nm;
the thickness of the first metal electrode layer and the second metal electrode layer is 200nm;
the thickness of the second GaN nanowire is 0.3 μm;
the thickness of the metal film layer is 75nm;
the thickness of the lining layer is 25nm;
the thickness of the polycrystalline silicon germanium film layer is 0.3 mu m.
The invention also provides a preparation method of the RESFET device, which comprises the following steps:
the MOS tube part is provided with a plurality of metal-oxide-semiconductor (MOS) tubes,
etching a nanowire protruding from the middle of the substrate;
growing aluminum oxide layers on two sides of the nanowire on the substrate until the aluminum oxide layers are consistent with the thickness of the nanowire;
plating a first metal electrode layer on a plane formed by the nanowire and the aluminum oxide layer;
growing a first oxide layer on the first metal electrode layer, epitaxially growing a Si layer on the substrate, and etching to the thickness of the oxide layer;
growing a second nanowire on the oxide layer and the epitaxially grown Si layer;
growing a second oxide layer and the first oxide layer to jointly wrap the second nanowire;
growing a second metal electrode layer and a first metal electrode layer to wrap the oxide layer;
removing the epitaxially grown Si layer;
ohmic electrodes are modified at two ends of the nanowire;
a portion of the RES-type light source,
growing a substrate on a plane formed by the nanowire and the aluminum oxide layer;
plating two metal film layers which are spaced from each other;
plating two metal film layers on the two metal film layers respectively to form a liner layer;
a polysilicon germanium film layer is disposed on the inner liner.
Preferably, the preparation method of the alumina layer and the oxide layer is any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or an Atomic Layer Deposition (ALD) method.
Preferably, the preparation method of the metal electrode layer is any one of thermal evaporation, magnetron sputtering or electron beam evaporation.
Preferably, the second nanowire is prepared by any one of Hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD).
Preferably, the silicon layer is etched by selectively etching a tetramethyl ammonium hydroxide (TMAH) aqueous solution.
Compared with the prior art, when the conventional vertical RESFET device of the RESFET device is conducted, a resistor and an MOS tube are integrated on a substrate, and compared with the conventional inverter, the static power consumption is lower, the time delay is lower, the device volume is reduced, and the integration level is improved. The upper surface, the lower surface and the side surfaces of the nanowire form channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated gate-all-around and the comprehensive performance of the multi-layer nanowire are further improved. The nanowire with narrow width is adopted, so that the method has the characteristic of low power consumption. Compared with the traditional vertical FinFET device, the heat dissipation can be effectively realized, the normal operation can be realized for a longer time, and the output current density is higher.
The preparation method of the RESFET device improves the device performance, improves the device integration level, reduces the energy consumption, and simultaneously adopts the technical means without any threshold, thereby being suitable for large-scale popularization and application.
Drawings
FIG. 1 is a schematic diagram of a RESFET device according to an embodiment of the present invention
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the embodiments of the present invention, the following terms are described below.
MOCVD method: MOCVD is a thin single crystal material in which organic compounds of group III and group II elements, hydrides of group V and group VI elements, and the like are used as crystal growth source materials, and vapor phase epitaxy is performed on a substrate by a thermal decomposition reaction method to grow various III-V main group, II-VI sub-group compound semiconductors, and their multiple solid solutions.
In one aspect of the invention, there is provided a RESFET device comprising:
a MOS tube part and a RES part;
wherein the MOS transistor portion includes: an n-type GaN substrate 6; in a preferred embodiment, the material of the n-type GaN may be replaced by SiC; in a preferred embodiment, the thickness of the n-type GaN substrate is 300 μm;
the thickness of the first metal electrode layer and the second metal electrode layer is 200nm;
the thickness of the second GaN nanowire is 0.3 μm;
a first n-type GaN nanowire 6a, the first n-type GaN nanowire 6a being bonded to a surface of the n-type GaN substrate 6; in a preferred embodiment, the first n-type GaN nanowire has a thickness of 50nm and a width of 10-100nm, and in a further preferred embodiment, the first n-type GaN nanowire has a width of 50nm.
An aluminum oxide layer 5 bonded to the n-type GaN substrate 6 and divided into two portions spaced apart from each other by the first n-type GaN nanowire 6a, the two portions of the aluminum oxide layer 5 spaced apart from each other forming a plane with the first n-type GaN nanowire 6 a; in a preferred embodiment, the thickness of the alumina layer is 50nm; the upper surface, the lower surface and the side surfaces of the nanowire form channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated gate-all-around and the comprehensive performance of the multi-layer nanowire are further improved. The nanowire with narrow width is adopted, so that the method has the characteristic of low power consumption.
A first metal electrode layer 4a, which is attached to the surface of the n-type GaN substrate 6, where the plane formed by the alumina layer 5 and the first n-type GaN nanowire 6a faces away from the surface of the n-type GaN substrate 6;
a first oxide layer 7a, wherein a surface of the first oxide layer 7a is bonded to a surface of the first metal electrode layer 4a facing away from the n-type GaN substrate 6;
a second GaN nanowire 2,8, the second GaN nanowire 2,8 being bonded to a surface of the first oxide layer facing away from the n-type GaN substrate 6; in a preferred embodiment the thickness of the second GaN nanowire is 0.3 μm;
a second oxide layer 7b, wherein the second oxide layer 7b is combined with the first oxide layer 7a and faces away from the surface of the n-type GaN substrate, and the second oxide layer 7b and the first oxide layer 7a tightly wrap the second GaN nanowire to form an oxide wrap layer 7; in a preferred embodiment, the material of the first oxide layer and the second oxide layer is Al2O3 or SiO2.
The second metal electrode layer 4b is combined with the second oxide layer 7b and faces away from the surface of the first oxide layer, and the second metal electrode layer 4b and the first metal electrode layer 4a tightly wrap the oxide wrapping layer; in a preferred embodiment, the material of the first metal electrode layer and the second metal electrode layer is any one of Cr, ti and Al. In a preferred embodiment, the thickness of the first metal electrode layer and the second metal electrode layer is 200nm;
two ends of the second GaN nanowires 2 and 8 are respectively provided with an ohmic electrode 1 and 9;
the RES section includes:
a substrate layer 13; in a preferred embodiment the substrate material may be replaced by SiO2.
A metal film layer 11, wherein the metal film layer 11 is combined on one surface of the substrate 13 and divided into two parts which are separated from each other and respectively named as a first metal film layer 11a and a second metal film layer 11b; in a preferred embodiment, the metal film layer material is any one of Cr, ti and Al. In a preferred embodiment, the thickness of the metal film layer is 75nm;
the liner layers 14 are respectively combined with the first metal film layer 11a facing away from the substrate surface and the second metal film layer 11b facing away from the substrate surface, the first metal film layer 11a and the second metal film layer 11b are respectively provided with two liner layers spaced from each other, an outer liner is close to the edge of the metal film, and an inner liner is close to a spacing area formed by the first metal film layer 11a and the second metal film layer 11b; in a preferred embodiment, the spacer layer has a thickness of 25nm;
a polysilicon germanium film layer 12, said polysilicon germanium film layer 12 being in ohmic contact with said inner liner; in a preferred embodiment, the thickness of the polysilicon germanium film layer is 0.3 μm.
The substrate layer 13 of the RES portion is attached to the surface of the n-type GaN substrate 6, where the plane formed by the alumina layer 5 of the MOS tube portion and the first n-type GaN nanowire 6a faces away from the surface of the n-type GaN substrate 6. In a preferred embodiment, the thickness of the polysilicon germanium film layer is 0.3 μm. When the RESFET device is conducted, a resistor and an MOS tube are integrated on a substrate, and compared with a traditional inverter, the RESFET device has the advantages of lower static power consumption, lower time delay, reduced device volume and improved integration level. And the upper surface, the lower surface and the side surfaces of the nanowire form channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated gate-all-around and the comprehensive performance of the multi-layer nanowire are further improved. The nanowire with narrow width is adopted, so that the method has the characteristic of low power consumption.
In another aspect, the embodiment of the invention provides a preparation method of the RESFET device, which comprises the following steps:
the MOS tube part is provided with a plurality of metal-oxide-semiconductor (MOS) tubes,
s01: etching a nanowire protruding from the middle of the substrate;
s02: growing aluminum oxide layers on two sides of the nanowire on the substrate until the aluminum oxide layers are consistent with the thickness of the nanowire;
s03: plating a first metal electrode layer on a plane formed by the nanowire and the aluminum oxide layer;
s04: growing a first oxide layer on the first metal electrode layer, epitaxially growing a Si layer on the substrate, and etching to the thickness of the oxide layer;
s05: growing a second nanowire on the oxide layer and the epitaxially grown Si layer;
s06: growing a second oxide layer and the first oxide layer to jointly wrap the second nanowire;
s07: growing a second metal electrode layer and a first metal electrode layer to wrap the oxide layer;
s08: removing the epitaxially grown Si layer;
s09: ohmic electrodes are modified at two ends of the nanowire;
a portion of the RES-type light source,
s10: growing a substrate on a plane formed by the nanowire and the aluminum oxide layer;
s11: plating two metal film layers which are spaced from each other;
s12: plating two metal film layers on the two metal film layers respectively to form a liner layer;
s13: a polysilicon germanium film layer is disposed on the inner liner. Because the existing vertical RESFET device is integrated with a resistor and a MOS tube on a substrate, compared with the traditional inverter, the vertical RESFET device has lower static power consumption and lower time delay, reduces the volume of the device and improves the integration level.
In a preferred embodiment, the preparation method of the alumina layer and the oxide layer is any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method and an Atomic Layer Deposition (ALD) method. Can be flexibly selected according to specific material changes.
In a preferred embodiment, the metal electrode layer is prepared by any one of thermal evaporation, magnetron sputtering or electron beam evaporation. In a further preferred embodiment, magnetron sputtering is selected for coating, so that the method has the advantage of being more uniform and better in controllability.
In a preferred embodiment, the second nanowire is prepared by any one of Hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD). Chemical vapor deposition is the most commonly used method.
In a preferred embodiment, the silicon layer is etched by selectively etching an aqueous solution of tetramethylammonium hydroxide (TMAH). A Forming Gas Anneal (FGA) is performed on the nanowires after the selective etching to remove dislocations. In order to achieve good selective etching between GaN/Si, the solution temperature must be around 60℃and with the aid of ultra-large ultrasonic agitation.

Claims (10)

1. A resufet device, comprising:
a MOS tube part and a RES part;
wherein the MOS transistor portion includes: an n-type GaN substrate;
a first n-type GaN nanowire bonded to a surface of the n-type GaN substrate;
an aluminum oxide layer bonded to the n-type GaN substrate and divided into two portions spaced apart from each other by the first n-type GaN nanowire, the two portions of the aluminum oxide layer spaced apart from each other forming a plane with the first n-type GaN nanowire;
the first metal electrode layer is attached to the surface of the n-type GaN substrate, which is away from the plane formed by the aluminum oxide layer and the first n-type GaN nanowire;
the first oxide layer is combined on the surface of the first metal electrode layer, which is away from the surface of the n-type GaN substrate;
a second GaN nanowire bonded to the first oxide layer away from the n-type GaN substrate surface;
the second oxide layer is combined with the first oxide layer and deviates from the surface of the n-type GaN substrate, and the second oxide layer and the first oxide layer tightly wrap the second GaN nanowire to form an oxide wrapping layer;
the second metal electrode layer is combined with the surface of the second oxide layer, which is away from the first oxide layer, and the second metal electrode layer and the first metal electrode layer tightly wrap the oxide wrapping layer;
two ends of the second GaN nanowire are respectively provided with an ohmic electrode;
the RES section includes:
a substrate layer;
the metal film layer is combined on one surface of the substrate and divided into two parts which are separated from each other and respectively named as a first metal film layer and a second metal film layer;
the liner layers are respectively combined with the first metal film layer which is away from the surface of the substrate and the second metal film layer which is away from the surface of the substrate, two liner layers which are spaced from each other are respectively arranged on the first metal film layer and the second metal film layer, an outer liner is arranged close to the edge of the metal film, and an inner liner is arranged close to a spacing area formed by the first metal film and the second metal film;
a polysilicon germanium thin film layer in ohmic contact with the inner side of the liner;
and the substrate layer of the RES part is attached to the surface of the n-type GaN substrate, which is formed by the aluminum oxide layer of the MOS tube part and the first n-type GaN nanowire, and the surface of the n-type GaN substrate is deviated from the surface of the n-type GaN substrate.
2. The resufet device of claim 1, wherein: the material of the MOS tube substrate can be replaced by SiC; the RES tube substrate material may be replaced with SiO2.
3. The resufet device of claim 1, wherein: the first oxide layer and the second oxide layer are made of Al2O3 or SiO2.
4. The resufet device of claim 1, wherein: the first metal electrode layer, the second metal electrode layer and the metal film layer are made of any one of Cr, ti and Al.
5. The resufet device of claim 1, wherein:
the thickness of the n-type GaN substrate is 300 mu m;
the thickness of the first n-type GaN nanowire is 50nm, and the width is 10-100nm:
the thickness of the alumina layer is 50nm;
the thickness of the first metal electrode layer and the second metal electrode layer is 200nm;
the thickness of the second GaN nanowire is 0.3 μm;
the thickness of the metal film layer is 75nm;
the thickness of the lining layer is 25nm;
the thickness of the polycrystalline silicon germanium film layer is 0.3 mu m.
6. A method of fabricating a resufet device as claimed in any one of claims 1 to 5, comprising the steps of:
the MOS tube part is provided with a plurality of metal-oxide-semiconductor (MOS) tubes,
etching a nanowire protruding from the middle of the substrate;
growing aluminum oxide layers on two sides of the nanowire on the substrate until the aluminum oxide layers are consistent with the thickness of the nanowire;
plating a first metal electrode layer on a plane formed by the nanowire and the aluminum oxide layer;
growing a first oxide layer on the first metal electrode layer, epitaxially growing a Si layer on the substrate, and etching to the thickness of the oxide layer;
growing a second nanowire on the oxide layer and the epitaxially grown Si layer;
growing a second oxide layer and the first oxide layer to jointly wrap the second nanowire;
growing a second metal electrode layer and a first metal electrode layer to wrap the oxide layer;
removing the epitaxially grown Si layer;
ohmic electrodes are modified at two ends of the nanowire;
a portion of the RES-type light source,
growing a substrate on a plane formed by the nanowire and the aluminum oxide layer;
plating two metal film layers which are spaced from each other;
plating two metal film layers on the two metal film layers respectively to form a liner layer;
a polysilicon germanium film layer is disposed on the inner liner.
7. The method of fabricating a resufet device of claim 6, wherein: the preparation method of the alumina layer is any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method and an Atomic Layer Deposition (ALD) method.
8. The method of fabricating a resufet device of claim 6, wherein: the preparation method of the metal electrode layer is any one of thermal evaporation, magnetron sputtering or electron beam evaporation.
9. The method of fabricating a resufet device of claim 6, wherein: the second nanowire is prepared by any one of Hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD).
10. The method of fabricating a resufet device of claim 6, wherein: the silicon layer is etched by a tetramethyl ammonium hydroxide (TMAH) aqueous solution selectively.
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