CN114497192A - RESFET device and preparation method thereof - Google Patents

RESFET device and preparation method thereof Download PDF

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CN114497192A
CN114497192A CN202111638719.4A CN202111638719A CN114497192A CN 114497192 A CN114497192 A CN 114497192A CN 202111638719 A CN202111638719 A CN 202111638719A CN 114497192 A CN114497192 A CN 114497192A
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nanowire
oxide layer
substrate
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CN114497192B (en
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黄双武
高麟飞
林峰
吴钧烨
黎晓华
刘新科
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Shenzhen University
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Abstract

Compared with the prior art, the RESFET device has lower static power consumption and time delay, reduces the volume of the device and improves the integration level. The upper surface, the lower surface and the side surfaces of the nanowires are all provided with channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated ring gate and the comprehensive performance of the multi-layer nanowires are further improved. The nanowire with a narrow width is adopted, so that the nanowire has the characteristic of low power consumption. Compared with the traditional vertical FinFET device, the vertical FinFET device can realize more effective heat dissipation, longer-time normal operation and higher output current density. The preparation method of the RESFET device improves the device performance, improves the device integration level, reduces the energy consumption, and adopts a technical means without any threshold, so the preparation method is suitable for large-scale popularization and application.

Description

RESFET device and preparation method thereof
Technical Field
The invention belongs to the field of device manufacturing in semiconductor technology, and particularly relates to an RESFET device and a preparation method thereof.
Background
The GaN-based material has a series of material performance advantages of large forbidden band width, high breakdown field strength, high polarization coefficient, high electron mobility, high electron saturation drift velocity and the like, is an optimal material for preparing a new generation of high-performance power electronic device, and has important application prospects. GaN-based materials are very attractive for both optoelectronic and microelectronic devices. The GaN-based material has the characteristics of wide forbidden band width, high breakdown voltage, high electron saturation drift velocity, good thermal stability and the like, and can form an ideal heterojunction with AlGaN alloy material, the large conduction band offset on a heterogeneous interface and the high piezoelectric polarization and spontaneous polarization strength of the GaN-based material can generate high-density two-dimensional electron gas, and the electron gas density is about one order of magnitude higher than that of the AlGaAs/GaAs heterojunction, so that the GaN-based material is suitable for manufacturing high-temperature, high-frequency and high-power electronic devices.
Wide bandgap gallium nitride (GaN) has become a well-known semiconductor in power and rf device applications due to its superior material properties in recent years. A FinFET vertical nanowire complementary metal-semiconductor Field Effect Transistor (FinFET for short) having a three-dimensional structure has excellent gate controllability, and has attracted great attention and been widely used. The existing FinFET has the outstanding characteristics that: (1) the control circuit on the two sides of the grid is turned on and off. (2) In the FinFET structure, the gate is designed into a fork-shaped 3D structure similar to a fin, so that the leakage current can be greatly improved and reduced, and the gate length of the transistor can be greatly shortened. (3) The method has the advantages of low power consumption and small area.
The existing finfets also have significant drawbacks: the narrow channel width results in extremely high current density, low efficiency and single function.
High heat is generated and the GaN channel cannot dissipate heat efficiently, causing the temperature inside the channel to rise, resulting in poor device performance (self-heating effect). Therefore, it is necessary to reasonably design a resurfet device and a related practical fabrication method to overcome the deficiencies of the prior art.
Disclosure of Invention
The invention aims to provide an RESFET device, which aims to solve the technical problems that the conventional RESFET device is large in size and high in energy consumption and has insufficient integration level.
The invention also aims to provide a preparation method of the RESFET device, so as to supplement the preparation method of the RESFET device with high integration.
In order to achieve the above object, according to an aspect of the present invention, there is provided a resurfet device including:
a MOS transistor portion and a RES portion;
wherein the MOS transistor portion includes: an n-type GaN substrate;
a first n-type GaN nanowire bonded to a surface of the n-type GaN substrate;
an aluminum oxide layer bonded to the n-type GaN substrate and divided by the first n-type GaN nanowire into two parts spaced apart from each other, the two parts spaced apart from each other of the aluminum oxide layer forming a plane with the first n-type GaN nanowire;
the first metal electrode layer is attached to the surface, away from the surface of the n-type GaN substrate, of a plane formed by the aluminum oxide layer and the first n-type GaN nanowires;
a first oxide layer, wherein one surface of the first oxide layer is combined with the surface of the first metal electrode layer, which is deviated from the surface of the n-type GaN substrate;
a second GaN nanowire bonded to the first oxide layer away from the n-type GaN substrate surface;
the second oxide layer is combined on the surface, away from the n-type GaN substrate, of the first oxide layer, and the second oxide layer and the first oxide layer tightly wrap the second GaN nanowires to form an oxidation wrapping layer;
the second metal electrode layer is combined on the surface, away from the first oxide layer, of the second oxide layer, and the second metal electrode layer and the first metal electrode layer tightly wrap the oxidation wrapping layer;
two ohmic electrodes are respectively arranged at two ends of the second GaN nanowire;
the RES part comprises:
a substrate layer;
the metal film layer is combined on one surface of the substrate, is divided into two parts which are separated from each other and are respectively named as a first metal film layer and a second metal film layer;
the gasket layers are respectively combined with the first metal film layer, which is far away from the surface of the substrate, and the second metal film layer, which is far away from the surface of the substrate, the first metal film layer and the second metal film layer are respectively provided with two gasket layers which are spaced from each other, the gasket layers are outer side gaskets close to the edges of the metal films, and the gasket layers are inner side gaskets close to the spacing areas formed by the first metal film and the second metal film;
a polycrystalline silicon germanium thin film layer in ohmic contact with the inner side of the pad;
the RES part of the substrate layer is attached to the aluminum oxide layer arranged on the MOS tube part, and the plane formed by the first n-type GaN nanowire deviates from the surface of the n-type GaN substrate.
Preferably, the material of the MOS tube substrate can be replaced by SiC; the RES tube substrate material may be replaced by SiO 2.
Preferably, the material of the first oxide layer and the second oxide layer is Al2O3 or SiO 2.
Preferably, the first metal electrode layer, the second metal electrode layer and the metal film layer are made of any one of Cr, Ti and Al.
Preferably, the thickness of the n-type GaN substrate is 300 μm;
the first n-type GaN nanowire has a thickness of 50nm and a width of 10-100 nm:
the thickness of the aluminum oxide layer is 50 nm;
the thickness of the first metal electrode layer and the second metal electrode layer is 200 nm;
the thickness of the second GaN nanowire is 0.3 mu m;
the thickness of the metal film layer is 75 nm;
the thickness of the liner layer is 25 nm;
the thickness of the polycrystalline silicon germanium thin film layer is 0.3 mu m.
In another aspect, the present invention provides a method for manufacturing an RESFET device, including the steps of:
the MOS transistor part is connected with the MOS transistor part,
etching a nanowire with a protruding middle on a substrate;
growing aluminum oxide layers on two sides of the nanowire on the substrate until the thickness of the aluminum oxide layers is consistent with that of the nanowire;
plating a first metal electrode layer on a plane formed by the nanowires and the aluminum oxide layer;
growing a first oxide layer on the first metal electrode layer, epitaxially growing a Si layer on the substrate and etching to the thickness of the oxide layer;
growing a second nanowire on the oxide layer and the epitaxially grown Si layer;
growing a second oxide layer and the first oxide layer to jointly wrap the second nanowire;
growing a second metal electrode layer and a first metal electrode layer to wrap the oxide layer;
removing the epitaxially grown Si layer;
modifying ohmic electrodes at two ends of the nanowire;
the part of the RES is that,
growing a substrate on the plane formed by the nanowires and the aluminum oxide layer;
plating two metal film layers which are separated from each other;
respectively plating two metal film layers on the two metal film layers to form a liner layer;
and arranging the polycrystalline silicon germanium thin film layer on the inner side liner.
Preferably, the aluminum oxide layer and the oxide layer are prepared by any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method and an Atomic Layer Deposition (ALD) method.
Preferably, the preparation method of the metal electrode layer is any one of thermal evaporation, magnetron sputtering or electron beam evaporation.
Preferably, the second nanowire is prepared by any one of Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), or Metal Organic Chemical Vapor Deposition (MOCVD).
Preferably, the silicon layer is etched selectively by using a tetramethylammonium hydroxide (TMAH) aqueous solution.
Compared with the prior art, when the conventional vertical RESFET device of the RESFET device is switched on, a resistor and an MOS tube are integrated on a substrate, and compared with the traditional phase inverter, the RESFET device has the advantages of lower static power consumption, lower time delay, reduced device volume and improved integration level. The upper surface, the lower surface and the side surfaces of the nanowires are all provided with channels, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated ring gate and the comprehensive performance of the multi-layer nanowires are further improved. The nanowire with a narrow width is adopted, so that the nanowire has the characteristic of low power consumption. Compared with the traditional vertical FinFET device, the vertical FinFET device can realize more effective heat dissipation, longer-time normal operation and higher output current density.
The preparation method of the RESFET device improves the device performance, improves the device integration level, reduces the energy consumption, and adopts a technical means without any threshold, so the preparation method is suitable for large-scale popularization and application.
Drawings
FIG. 1 is a schematic structural diagram of a RESFET device according to an embodiment of the present invention
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the embodiments of the present invention, the following terms are explained below.
MOCVD method: MOCVD uses organic compounds of III group and II group elements and hydrides of V group and VI group elements as crystal growth source materials, and carries out vapor phase epitaxy on a substrate in a thermal decomposition reaction mode to grow thin layer single crystal materials of various III-V main group and II-VI sub group compound semiconductors and multi-element solid solutions thereof.
In one aspect of the present invention, there is provided a resurfet device including:
a MOS transistor portion and a RES portion;
wherein the MOS transistor portion includes: an n-type GaN substrate 6; in a preferred embodiment, the material of the n-type GaN can be replaced with SiC; in a preferred embodiment, the thickness of the n-type GaN substrate is 300 μm;
the thickness of the first metal electrode layer and the second metal electrode layer is 200 nm;
the thickness of the second GaN nanowire is 0.3 mu m;
a first n-type GaN nanowire 6a, the first n-type GaN nanowire 6a being bonded to a surface of the n-type GaN substrate 6; in a preferred embodiment, the thickness of the first n-type GaN nanowire is 50nm, and the width of the first n-type GaN nanowire is 10-100nm, and in a further preferred embodiment, the width of the first n-type GaN nanowire is 50 nm.
An aluminum oxide layer 5 bonded to the n-type GaN substrate 6 and divided into two parts spaced apart from each other by the first n-type GaN nanowire 6a, the two parts spaced apart from each other of the aluminum oxide layer 5 forming a plane with the first n-type GaN nanowire 6 a; in a preferred embodiment, the thickness of the aluminum oxide layer is 50 nm; channels are formed on the upper surface, the lower surface and the side surfaces of the nanowire, so that a multi-layer channel structure can be formed, and the overall carrier mobility of the channel structure of the multi-layer nanowire laminated ring gate and the comprehensive performance of the multi-layer nanowire are further improved. The nanowire with a narrow width is adopted, so that the nanowire has the characteristic of low power consumption.
The first metal electrode layer 4a is attached to the surface, away from the surface of the n-type GaN substrate 6, of a plane formed by the aluminum oxide layer 5 and the first n-type GaN nanowires 6 a;
a first oxide layer 7a, wherein one surface of the first oxide layer 7a is combined with the surface of the first metal electrode layer 4a, which is far away from the n-type GaN substrate 6;
a second GaN nanowire 2, 8, the second GaN nanowire 2, 8 bonded to the surface of the first oxide layer facing away from the n-type GaN substrate 6; the thickness of the second GaN nanowire is 0.3 μm in a preferred embodiment;
a second oxide layer 7b, wherein the second oxide layer 7b is combined on the surface of the first oxide layer 7a facing away from the n-type GaN substrate, and the second oxide layer 7b and the first oxide layer 7a tightly wrap the second GaN nanowire to form an oxide wrapping layer 7; in a preferred embodiment, the material of the first oxide layer and the second oxide layer is Al2O3 or SiO 2.
The second metal electrode layer 4b is combined on the surface, away from the first oxidation layer, of the second oxidation layer 7b, and the second metal electrode layer 4b and the first metal electrode layer 4a tightly wrap the oxidation wrapping layer; in a preferred embodiment, the material of the first metal electrode layer and the second metal electrode layer is any one of Cr, Ti and Al. In a preferred embodiment, the thickness of the first metal electrode layer and the second metal electrode layer is 200 nm;
two ends of each of the second GaN nanowires 2 and 8 are respectively provided with an ohmic electrode 1 and 9;
the RES part comprises:
a backing layer 13; in a preferred embodiment the substrate material may be replaced with SiO 2.
The metal film layer 11 is combined on one surface of the substrate 13, and is divided into two parts which are separated from each other and named as a first metal film layer 11a and a second metal film layer 11b respectively; in a preferred embodiment, the metal film layer is made of any one of Cr, Ti and Al. In a preferred embodiment, the thickness of the metal film layer is 75 nm;
a liner layer 14, respectively bonded to the first metal film layer 11a and the second metal film layer 11b, which are away from the substrate surface, wherein the first metal film layer 11a and the second metal film layer 11b are respectively provided with two liner layers which are spaced from each other, an outer liner is arranged near the edge of the metal film layer, and an inner liner is arranged near a spacing region formed by the first metal film layer 11a and the second metal film layer 11 b; in a preferred embodiment, the thickness of the liner layer is 25 nm;
a polycrystalline silicon germanium thin film layer 12, the polycrystalline silicon germanium thin film layer 12 being in ohmic contact with the inner liner; in a preferred embodiment, the thickness of the polycrystalline silicon germanium thin film layer is 0.3 μm.
The RES part of the substrate layer 13 is attached to the surface, away from the surface of the n-type GaN substrate 6, of the MOS tube part, of a plane formed by the aluminum oxide layer 5 and the first n-type GaN nanowire 6 a. In a preferred embodiment, the thickness of the polycrystalline silicon germanium thin film layer is 0.3 μm. When the RESFET device is conducted, the resistor and the MOS tube are integrated on the substrate, and compared with a traditional phase inverter, the RESFET device is lower in static power consumption and time delay, reduces the size of the device, and improves the integration level. And because the upper surface, the lower surface and the side surface of the nanowire form the channel, a multilayer channel structure can be formed, and the overall carrier mobility of the channel structure of the multilayer nanowire laminated ring gate and the comprehensive performance of the multilayer nanowire are further improved. The nanowire with a narrow width is adopted, so that the nanowire has the characteristic of low power consumption.
In another aspect, an embodiment of the present invention provides a method for manufacturing an RESFET device, including the following steps:
the MOS transistor part is connected with the MOS transistor part,
s01: etching a nanowire with a protruding middle on a substrate;
s02: growing aluminum oxide layers on two sides of the nanowire on the substrate until the thickness of the aluminum oxide layers is consistent with that of the nanowire;
s03: plating a first metal electrode layer on a plane formed by the nanowires and the aluminum oxide layer;
s04: growing a first oxide layer on the first metal electrode layer, epitaxially growing a Si layer on the substrate and etching to the thickness of the oxide layer;
s05: growing a second nanowire on the oxide layer and the epitaxially grown Si layer;
s06: growing a second oxide layer and the first oxide layer to jointly wrap the second nanowire;
s07: growing a second metal electrode layer and a first metal electrode layer to wrap the oxide layer;
s08: removing the epitaxially grown Si layer;
s09: modifying ohmic electrodes at two ends of the nanowire;
the part of the RES is that,
s10: growing a substrate on the plane formed by the nanowires and the aluminum oxide layer;
s11: plating two metal film layers which are separated from each other;
s12: respectively plating two metal film layers on the two metal film layers to form a liner layer;
s13: and arranging the polycrystalline silicon germanium thin film layer on the inner side liner. Because the existing vertical RESFET device integrates a resistor and an MOS tube on a substrate when being conducted, compared with the traditional phase inverter, the static power consumption is lower, the time delay is lower, the device volume is reduced, and the integration level is improved.
In a preferred embodiment, the method for preparing the aluminum oxide layer and the oxide layer is any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method and an Atomic Layer Deposition (ALD) method. Can be flexibly selected according to specific material changes.
In a preferred embodiment, the preparation method of the metal electrode layer is any one of thermal evaporation, magnetron sputtering or electron beam evaporation. In a further preferred embodiment, magnetron sputtering is selected for coating, so that the coating has the advantages of more uniformity and better controllability.
In a preferred embodiment, the second nanowire is prepared by any one of Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), or Metal Organic Chemical Vapor Deposition (MOCVD). Chemical vapor deposition is the most common method.
In a preferred embodiment, the silicon layer is etched selectively by a tetramethylammonium hydroxide (TMAH) aqueous solution. The selective etching is followed by a Forming Gas Anneal (FGA) on the nanowires to remove dislocations. In order to achieve good selective etching between GaN/Si, the solution temperature must be around 60 ℃ and stirred with ultra-large ultrasound.

Claims (10)

1. A RESFET device, comprising:
a MOS transistor portion and a RES portion;
wherein the MOS transistor portion includes: an n-type GaN substrate;
a first n-type GaN nanowire bonded to a surface of the n-type GaN substrate;
an aluminum oxide layer bonded to the n-type GaN substrate and divided by the first n-type GaN nanowire into two parts spaced apart from each other, the two parts spaced apart from each other of the aluminum oxide layer forming a plane with the first n-type GaN nanowire;
the first metal electrode layer is attached to the surface, away from the surface of the n-type GaN substrate, of a plane formed by the aluminum oxide layer and the first n-type GaN nanowires;
a first oxide layer, wherein one surface of the first oxide layer is combined with the surface of the first metal electrode layer, which is deviated from the surface of the n-type GaN substrate;
a second GaN nanowire bonded to the first oxide layer away from the n-type GaN substrate surface;
the second oxide layer is combined on the surface, away from the n-type GaN substrate, of the first oxide layer, and the second oxide layer and the first oxide layer tightly wrap the second GaN nanowires to form an oxidation wrapping layer;
the second metal electrode layer is combined on the surface, away from the first oxidation layer, of the second oxidation layer, and the second metal electrode layer and the first metal electrode layer tightly wrap the oxidation wrapping layer;
two ohmic electrodes are respectively arranged at two ends of the second GaN nanowire;
the RES part comprises:
a substrate layer;
the metal film layer is combined on one surface of the substrate, is divided into two parts which are separated from each other and are respectively named as a first metal film layer and a second metal film layer;
the liner layers are respectively combined with the first metal film layer and the second metal film layer which are deviated from the surface of the substrate, the first metal film layer and the second metal film layer are respectively provided with two liner layers which are spaced from each other, the liner layers are outer liners close to the edges of the metal films, and the liner layers are inner liners close to spaced areas formed by the first metal film and the second metal film;
a polycrystalline silicon germanium thin film layer in ohmic contact with the inner side of the pad;
the RES part of the substrate layer is attached to the aluminum oxide layer arranged on the MOS tube part, and the plane formed by the first n-type GaN nanowire deviates from the surface of the n-type GaN substrate.
2. The RESFET device of claim 1, wherein: the material of the MOS tube substrate can be replaced by SiC; the RES tube substrate material may be replaced by SiO 2.
3. The RESFET device of claim 1, wherein: the material of the first oxide layer and the second oxide layer is Al2O3 or SiO 2.
4. The RESFET device of claim 1, wherein: the first metal electrode layer, the second metal electrode layer and the metal film layer are made of any one of Cr, Ti and Al.
5. The RESFET device of claim 1, wherein:
the thickness of the n-type GaN substrate is 300 mu m;
the first n-type GaN nanowire has a thickness of 50nm and a width of 10-100 nm:
the thickness of the aluminum oxide layer is 50 nm;
the thickness of the first metal electrode layer and the second metal electrode layer is 200 nm;
the thickness of the second GaN nanowire is 0.3 mu m;
the thickness of the metal film layer is 75 nm;
the thickness of the liner layer is 25 nm;
the thickness of the polycrystalline silicon germanium thin film layer is 0.3 mu m.
6. A method of fabricating a RESFET device as claimed in any of claims 1 to 5, comprising the steps of:
a part of the MOS transistor is connected with a MOS transistor,
etching a nanowire with a protruding middle on a substrate;
growing aluminum oxide layers on two sides of the nanowire on the substrate until the thickness of the aluminum oxide layers is consistent with that of the nanowire;
plating a first metal electrode layer on a plane formed by the nanowires and the aluminum oxide layer;
growing a first oxide layer on the first metal electrode layer, epitaxially growing a Si layer on the substrate and etching to the thickness of the oxide layer;
growing a second nanowire on the oxide layer and the epitaxially grown Si layer;
growing a second oxide layer and the first oxide layer to jointly wrap the second nanowire;
growing a second metal electrode layer and a first metal electrode layer to wrap the oxide layer;
removing the epitaxially grown Si layer;
modifying ohmic electrodes at two ends of the nanowire;
the part of the RES is that,
growing a substrate on the plane formed by the nanowires and the aluminum oxide layer;
plating two metal film layers which are separated from each other;
respectively plating two metal film layers on the two metal film layers to form a liner layer;
and arranging the polycrystalline silicon germanium thin film layer on the inner side liner.
7. The method of fabricating a RESFET device of claim 6, wherein: the preparation method of the aluminum oxide layer and the oxide layer is any one of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or an Atomic Layer Deposition (ALD) method.
8. The method of fabricating a RESFET device of claim 6, wherein: the preparation method of the metal electrode layer is any one of thermal evaporation, magnetron sputtering or electron beam evaporation.
9. The method of fabricating a RESFET device of claim 6, wherein: the second nanowire is prepared by any one of Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE) or metal organic compound chemical vapor deposition (MOCVD).
10. The method of fabricating a RESFET device of claim 6, wherein: the etching mode of the silicon layer is that tetramethyl ammonium hydroxide (TMAH) aqueous solution is used for selectively etching.
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