CN118039470A - Pseudo-matched high electron mobility transistor and preparation method thereof - Google Patents

Abstract

The invention provides a pseudo-matched high electron mobility transistor and a preparation method thereof. The method comprises the steps of firstly forming a first patterned photoresist layer in the gate groove to limit the gate length of the gate structure, avoiding the influence of the evaporation angle of the evaporation process on the gate length, and improving the flexibility and the accuracy of gate length limit. Then, adopt first dielectric layer to cover the substrate with the surface that the bars groove exposes, not only can isolate the air, avoid influencing the growth of grid structure because of bars groove inner wall oxidation, improved the connection effect between grid structure and the substrate, and then stabilize the device and open the voltage to avoid the electric leakage increase, can also stabilize the grid structure, the accurate limit bars is long, and avoid dropping in the bars inslot at the in-process metal piece that the photoresistance stripped, cause the device electric leakage to be bigger or short circuit. And secondly, a second patterning photoresist layer is formed on the first dielectric layer to serve as a blocking layer for metal evaporation, a double-layer photoresist structure is omitted, and adverse effects on the morphology of the grid structure and the device performance caused by the problems of unstable photoresist morphology, photoresist residue and the like due to double-photoresist mutual dissolution are effectively avoided. And finally, forming a grid structure with better appearance by adopting an evaporation process, and improving the performance of the device.

Description

Pseudo-matched high electron mobility transistor and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a pseudo-matched high electron mobility transistor and a preparation method thereof.

Background

The pseudomorphic high electron mobility transistor (Pseudomorphic High Electron Mobility Transistor, pHEMT) is an improved structure of the high electron mobility transistor, has the advantages of higher electron mobility, high-speed low-noise operation, good temperature stability, adjustable output conductance and the like, and is widely applied to the communication fields of optical fiber communication, microwave communication, satellite communication and the like, integrated circuits and the like.

At present, the most important link in the pHEMT preparation process is the preparation of a T-shaped gate structure, and the process effect directly influences the performance and yield of the device. Referring to fig. 1 to 6, the conventional process for preparing the T-shaped gate structure is based on a double-layer glue process. That is, a first photoresist layer 101 is formed on the epitaxial layer 100, and the first photoresist layer 101 is exposed and developed to expose a portion of the surface of the epitaxial layer 100. And coating a second photoresist layer 102 on the surface of the first photoresist layer 101, and exposing and developing the second photoresist layer 102 to form the patterned second photoresist layer 102 on the surface of the first photoresist layer 101. Since the second photoresist layer 102 is directly formed on the first photoresist layer 101, the contact surface between the two layers is very easy to cause the problem of double-layer photoresist mutual dissolution, and the photoresist morphology is easy to be unstable. Therefore, as shown in fig. 4, when the metal layer 103 is deposited in the gate trench T of the epitaxial layer 100, the gate length of the T-shaped gate structure is affected by the unstable photoresist morphology; and, as shown in fig. 5, during the photoresist stripping process, the photoresist profile is unstable, which also causes problems of metal debris and dropping and residue of the photoresist 104. These problems can easily cause large leakage or short circuit of the device, and seriously affect the performance and yield of the device. And, as shown in fig. 4 to 6, the prior art is to redeposit the dielectric protection layer 105 after the entire T-gate is completed. This preparation exposes epitaxial layer 100 to the atmosphere for an excessive amount of time, resulting in oxidation of the surface of epitaxial layer 100 to form oxide layer 106. The presence of the oxide layer 106 may increase the difficulty of growth of the T-shaped gate, and affect the uniformity and stability of the T-shaped gate, thereby causing the problems of unstable device turn-on voltage, increased device leakage, and the like. In addition, the gate length of the T-shaped gate structure in the prior art is also easily influenced by the evaporation angle of the evaporation process, and if the gate length is unstable, the current control capability of the transistor is directly influenced, so that the performance of the device is unstable.

Therefore, a new process for preparing a T-type gate structure is needed to solve the above technical problems.

Disclosure of Invention

The invention aims to provide a pseudo-matched high-electron mobility transistor and a preparation method thereof, which are used for solving at least one problem of how to avoid the influence of double-colloid mutual solubility on the appearance of a photoresist, how to improve the preparation process effect of a metal gate and how to improve the performance of the transistor.

In order to solve the technical problems, the invention provides a preparation method of a pseudo-matched high electron mobility transistor, which comprises the following steps:

providing a substrate, wherein a grid groove is formed on the substrate;

forming a first patterned photoresist layer on a portion of a bottom surface of the gate trench;

forming a first dielectric layer on the surfaces of the substrate and the first patterned photoresist layer;

removing the first patterned photoresist layer and exposing the partial bottom surface of the gate trench;

forming a second patterned photoresist layer on the surface of the first dielectric layer, and exposing part of the surface of the first dielectric layer and part of the bottom surface of the gate groove;

And taking the second patterned photoresist layer as a barrier, and forming a metal layer on the exposed partial surface of the first dielectric layer and the partial bottom surface of the gate groove to serve as a gate structure.

Optionally, in the method for manufacturing the pseudo-matching hemt, the process of forming the gate groove on the substrate includes:

forming a third patterned photoresist layer on the surface of the substrate, and exposing a part of the surface of the substrate;

And etching the exposed substrate by taking the third patterned photoresist layer as a barrier to form the gate groove.

Optionally, in the method for preparing the pseudo-high electron mobility transistor, an anisotropic etching process is adopted to form the gate groove on the substrate; and removing the third patterned photoresist layer after forming the gate trench.

Optionally, in the method for manufacturing the pseudo-high electron mobility transistor, a line width of the first patterned photoresist layer is equal to a gate length of the gate structure.

Optionally, in the method for manufacturing the pseudo-matching high electron mobility transistor, in a process of forming a first dielectric layer on the surfaces of the substrate and the first patterned photoresist layer, the first dielectric layer also covers the side wall of the gate groove and the exposed bottom surface.

Optionally, in the method for manufacturing the pseudo-high electron mobility transistor, the first dielectric layer and the first patterned photoresist layer on the surface of the first patterned photoresist layer are sequentially removed in the process of removing the first patterned photoresist layer.

Optionally, in the method for manufacturing the pseudo-configured hemt, the second patterned photoresist layer exposes the first dielectric layer on the sidewall and the bottom surface of the gate trench.

Optionally, in the method for manufacturing the pseudo-high electron mobility transistor, an evaporation process is used to form the metal layer.

Optionally, in the method for manufacturing a pseudo-configured hemt, after forming the metal layer, the method for manufacturing a pseudo-configured hemt further includes:

removing the second patterned photoresist layer;

And forming a second dielectric layer on the surfaces of the first dielectric layer and the metal layer.

Based on the same conception, the invention also provides a pseudo-matched high electron mobility transistor, which comprises a grid structure prepared by the preparation method of the pseudo-matched high electron mobility transistor.

In summary, the present invention provides a pseudo-matched high electron mobility transistor and a method for manufacturing the same. Compared with the prior art, the invention has the following main beneficial effects:

1. and forming a first patterned photoresist layer in the gate groove to limit the gate length of the gate structure, so that the influence of the evaporation angle of the evaporation process on the gate length is avoided, and the flexibility and the accuracy of gate length limit are improved.

2. The first dielectric layer is adopted to cover the exposed surfaces of the substrate and the gate groove in advance, so that air can be isolated, the growth of a gate structure is prevented from being influenced due to oxidation of the inner wall of the gate groove, the connection effect between the gate structure and the substrate is improved, the starting voltage of a device is stabilized, the increase of electric leakage is avoided, the gate structure can be stabilized, the gate length is accurately limited, and the problem that metal scraps fall into the gate groove in the process of stripping the photoresist to cause the bigger electric leakage or short circuit of the device is solved.

3. And a second patterned photoresist layer is formed on the first dielectric layer to serve as a blocking layer for metal evaporation, a double-layer photoresist structure is omitted, adverse effects of photoresist morphology instability, photoresist residue and other problems caused by double-photoresist mutual dissolution on the morphology of the gate structure and the device performance are effectively avoided, and the device performance is improved.

Drawings

Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

Fig. 1 is a schematic diagram of a structure for forming a first photoresist layer in the prior art.

Fig. 2 is a schematic diagram of a structure for forming a second photoresist layer in the prior art.

Fig. 3 is a schematic diagram of a prior art structure for forming a gate trench.

Fig. 4 is a schematic diagram of a prior art structure for forming a metal layer.

FIG. 5 is a schematic diagram of a prior art structure for stripping photoresist and forming metal debris and photoresist residues.

Fig. 6 is a schematic diagram of a structure for forming a dielectric protection layer in the prior art.

Figure 7 is a flow chart of a method of fabricating a pseudomorphic hemt in an embodiment of the invention.

FIG. 8 is a schematic diagram of a structure for forming a third patterned photoresist layer according to an embodiment of the invention.

Fig. 9 is a schematic diagram of a structure for forming a gate trench in an embodiment of the present invention.

FIG. 10 is a schematic diagram of a structure for forming a first patterned photoresist layer according to an embodiment of the invention.

Fig. 11 is a schematic structural diagram of forming a first dielectric layer according to an embodiment of the present invention.

FIG. 12 is a schematic diagram of a structure for removing the third patterned photoresist layer according to an embodiment of the invention.

FIG. 13 is a schematic diagram of a structure for forming a second patterned photoresist layer according to an embodiment of the invention.

Fig. 14 is a schematic view of a structure of forming a metal layer in an embodiment of the present invention.

FIG. 15 is a schematic diagram of a structure for removing the second patterned photoresist layer according to an embodiment of the invention.

Fig. 16 is a schematic structural diagram of forming a second dielectric layer according to an embodiment of the present invention.

And, in the drawings:

100-epitaxial layers; 101-a first photoresist layer; 102-a second photoresist layer; 103-a metal layer; 104-metal scraps and a photoresist; 105-a dielectric protective layer; 106-an oxide layer;

200-substrate; 201-a third patterned photoresist layer; 202-a first patterned photoresist layer; 203-a first dielectric layer; 204-a second patterned photoresist layer; 205-a metal layer; 206-a second dielectric layer;

T-gate groove; d-line width.

Detailed Description

The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.

As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", "a third" may include either explicitly or implicitly one or at least two of such features, and the terms "mounted", "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. Furthermore, as used in this disclosure, an element disposed on another element generally only refers to a connection, coupling, cooperation or transmission between two elements, and the connection, coupling, cooperation or transmission between two elements may be direct or indirect through intermediate elements, and should not be construed as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation, such as inside, outside, above, below, or on one side, of the other element unless the context clearly indicates otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

Referring to fig. 7, the present embodiment provides a method for manufacturing a pseudo-matching hemt, which includes:

Step one S10: providing a substrate, wherein a grid groove is formed on the substrate;

step two S20: forming a first patterned photoresist layer on a portion of a bottom surface of the gate trench;

Step three S30: forming a first dielectric layer on the surfaces of the substrate and the first patterned photoresist layer;

Step four, S40: removing the first patterned photoresist layer and exposing the partial bottom surface of the gate trench;

step five S50: forming a second patterned photoresist layer on the surface of the first dielectric layer, and exposing part of the surface of the first dielectric layer and part of the bottom surface of the gate groove;

Step six S60: and taking the second patterned photoresist layer as a barrier, and forming a metal layer on the exposed partial surface of the first dielectric layer and the partial bottom surface of the gate groove to serve as a gate structure.

Based on the method, the influence of double-gel mutual dissolution on the photoresist morphology can be avoided, the preparation process effect of the grid structure can be improved, and the device performance is improved.

The following specifically describes a method for manufacturing the pseudo-configured hemt according to the present embodiment with reference to fig. 7 to 16.

Specifically, the preparation method of the pseudo-matched high electron mobility transistor comprises the following steps:

Step one S10: referring to fig. 8 and 9, a substrate 200 is provided, and a gate trench T is formed on the substrate 200.

It should be noted that, the substrate 200 in this embodiment is any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, and may be a die, a wafer processed by an epitaxial growth process, a circuit layer or other semiconductor thin film on which devices are formed. Therefore, the specific material and the film structure of the substrate 200 are not particularly limited in this embodiment. Illustratively, if the method provided in this embodiment is used to form a T-metal gate in a pseudo-high electron mobility transistor, then preferably, the substrate 200 includes a gallium arsenide (GaAs) base and an epitaxial structure formed on a surface of the GaAs base. And the epitaxial structure can comprise an AlGaAs buffer layer, an InGaAs channel layer, an AlGaAs barrier layer, a low-doped GaAs layer, a high-doped GaAs cap layer and the like which are sequentially stacked.

Further, the process of forming the gate trench T on the substrate 200 includes: a photoresist layer is coated on the surface of the substrate 200, and a third patterned photoresist layer 201 is formed by exposure and development. Wherein the third patterned photoresist layer 201 exposes a portion of the surface of the substrate 200. Then, the exposed substrate 200 is etched with the third patterned photoresist layer 201 as a barrier to form the gate trench T. Preferably, the gate groove T is formed on the substrate 200 using an anisotropic etching process. Finally, the third patterned photoresist layer 201 on the surface of the substrate 200 is removed by using a photoresist stripping process.

Step two S20: referring to fig. 10, a first patterned photoresist layer 202 is formed on a portion of the bottom surface of the gate trench T.

Illustratively, the first patterned photoresist layer 202 is a positive photoresist. Thus, a positive photoresist layer is coated on the surface of the substrate 200 and the inner walls of the gate trench T, and then the positive photoresist layer is exposed and developed, and only a portion of the positive photoresist on the bottom surface of the gate trench T remains as the first patterned photoresist layer 202. The first patterned photoresist layer 202 covers a portion of the bottom surface of the gate trench T, and the line width D of the first patterned photoresist layer 202 is equal to the gate length of the gate structure formed subsequently. It is understood that the first patterned photoresist layer 202 is used to define the gate length of the gate structure. Compared with the prior art that the gate length of the gate structure is limited by forming the double-layer photoresist layer and controlling the evaporation angle of the metal evaporation process, the method provided by the embodiment effectively avoids the problem of mutual dissolution of the double-layer photoresist layer and ensures the shape stability of the gate structure. And under the accurate definition of the first patterned photoresist layer 202, the gate length of the gate structure is not changed due to the change of metal evaporation process parameters, so that the accuracy of gate length definition of the gate structure is improved, the flexibility of gate length definition of the gate structure is optimized, and the gate length can be flexibly defined only by adjusting the line width D of the first patterned photoresist layer 202.

Step three S30: referring to fig. 11, a first dielectric layer 203 is formed on the substrate 200 and the first patterned photoresist layer 202.

Through the above process steps, the surface of the substrate 200 and the inner wall of the gate trench T on the substrate 200 are exposed to an air medium, and the long-term exposure is easy to react with oxygen in the air and generate an oxide layer. It should be noted that the presence of the oxide layer may increase the difficulty of metal growth, and even the gate structure cannot be formed. And the non-uniformity of the oxide layer can also cause non-uniform growth of the gate structure, which affects the performance and stability thereof. And the stability of the oxide layer is poor, and the oxide layer is easy to change in the subsequent heat treatment and other processes, and the performance and stability of the gate structure are also affected. In addition, the formation of the oxide layer may affect the connection effect between the gate structure and the substrate 200, which may easily cause the problems of unstable device turn-on voltage, increased device leakage, and the like. Therefore, in this embodiment, after the first patterned photoresist layer 202 is formed, the first dielectric layer 203 is formed on the surface of the substrate 200, the sidewall and the exposed bottom surface of the gate trench T, and the surface of the first patterned photoresist layer 202, so that the first dielectric layer 203 is used to isolate air, thereby avoiding forming an oxide layer, improving the connection effect between the gate structure and the substrate 200, and ensuring the stability of the device turn-on voltage. Meanwhile, the first dielectric layer 203 can further limit the gate length of the gate structure, so as to avoid the influence of the evaporation angle of the evaporation process. And, the arrangement of the first dielectric layer 203 can also avoid the metal scraps from falling to the substrate 200 in the subsequent metal evaporation and metal stripping processes, so as to avoid the problems of large device leakage or short circuit and the like caused by the metal scraps.

Optionally, the material of the first dielectric layer 203 includes, but is not limited to, silicon nitride (Si ₃N₄), silicon dioxide (SiO ₂), and the like. And the process of forming the first dielectric layer 203 is not limited to a chemical vapor deposition process or a physical vapor deposition process.

Step four, S40: referring to fig. 11 and 12, the first patterned photoresist layer 202 is removed, and the partial bottom surface of the gate trench T is exposed.

Since the first dielectric layer 203 is attached to the surface of the first patterned photoresist layer 202, if the photoresist stripping process is directly used to remove the first patterned photoresist layer 202, the photoresist may not be completely stripped, resulting in photoresist residue. Therefore, before the first patterned photoresist layer 202 is removed, an etching process is used to remove the first dielectric layer 203 on the surface of the first patterned photoresist layer 202, and after a high-pressure stripping process or a chemical stripping process is used to remove the first patterned photoresist layer 202, the partial bottom surface of the gate trench T is exposed. It will be appreciated that, when a portion of the bottom surface of the gate trench T is exposed for growing a gate structure, the width of the portion of the bottom surface exposed is equal to the gate length of the gate structure.

Step five S50: referring to fig. 13, a second patterned photoresist layer 204 is formed on the surface of the first dielectric layer 203, and a portion of the surface of the first dielectric layer 203 and the portion of the bottom surface of the gate trench T are exposed.

Specifically, a positive photoresist is coated on the surface of the first dielectric layer 203 and a part of the exposed bottom surface of the gate groove T. The positive photoresist is then exposed to light and developed to form the second patterned photoresist layer 204. Wherein the second patterned photoresist layer 204 exposes not only a portion of the bottom surface of the gate trench T, but also the first dielectric layer 203 on the sidewall and bottom surface of the gate trench T. Preferably, the second patterned photoresist layer 204 has an undercut morphology. As shown in fig. 13, the second patterned photoresist layer 204 has an inverted trapezoid shape, so that in the subsequent metal evaporation process, a metal layer is not easy to be formed on the sidewall of the second patterned photoresist layer 204, which is beneficial to precisely controlling the morphology of the metal layer.

Based on this, the method provided in this embodiment includes forming the gate trench T in the substrate 200, defining the gate length by using the first patterned photoresist layer 202, and finally forming the second patterned photoresist layer 204 on the surface of the first dielectric layer 203 to serve as a barrier layer for metal evaporation. Compared with the prior art, the method provided by the embodiment does not need to form double-layer stacked photoresist layers, so that the problem of unstable photoresist morphology caused by double-layer photoresist mutual dissolution is effectively avoided, and the morphology of the grid structure is ensured to have better accuracy; meanwhile, the problem of large electric leakage or short circuit of the device caused by falling of evaporated metal scraps in the subsequent metal evaporation process can be avoided, and the performance of the device is effectively improved.

Step six S60: referring to fig. 14, with the second patterned photoresist layer 204 as a barrier, a metal layer 205 is formed on the exposed portion of the surface of the first dielectric layer 203 and the portion of the bottom surface of the gate trench T to serve as a gate structure.

Preferably, the metal layer 205 is formed on the exposed surface of the first dielectric layer 203 and the exposed bottom surface of the gate trench T by using an evaporation process. The specific process parameters for forming the metal layer 205 are not limited, and specific materials of the metal layer 205 are not limited, for example: one or more of aluminum (Al), titanium (Ti), platinum (Pt) and gold (Au). And, in the evaporation process, a metal structure is also formed on the top surface of the second patterned photoresist layer 204, but in the subsequent lift-off process, the second patterned photoresist layer 204 is removed together, and only the metal layer 205 at the position of the gate trench T remains as the gate structure.

Compared with the prior art, the method provided in this embodiment forms the first dielectric layer 203 on the inner wall of the gate groove T in advance before forming the metal layer 205, so that on one hand, the problem that the growth and the morphology of the metal layer 205 are affected due to oxidation in the gate groove T, the connection effect between the gate structure and the substrate 200 is improved, the stability of the device on-voltage is ensured, and the increase of the electric leakage is avoided, and on the other hand, the gate length of the gate structure is further limited, the collapse of the metal layer 205 is avoided, and the problem that the electric leakage of the device is large or the device is short-circuited due to the occurrence of the condition that metal scraps fall in the gate groove T is avoided.

Further, referring to fig. 14, 15 and 16 after forming the metal layer 205, the method for manufacturing the pseudo-configured hemt further includes: a lift-off process is used to remove the second patterned photoresist layer 204. Because the method provided in this embodiment previously uses the first dielectric layer 203 to surround the contact position between the metal layer 205 and the substrate 200, and the method does not use a double-layer photoresist structure, in the process of removing the second patterned photoresist layer 204 and the metal structure on the second patterned photoresist layer 204, stability of the metal layer 205 can be improved, collapse of the metal layer 205 can be avoided, and problems of photoresist residue and metal chip drop can be effectively avoided, thereby improving device performance. And forming the second dielectric layer 206 on the surface of the first dielectric layer 203 and the surface of the metal layer 205 after removing the second patterned photoresist layer 204. Preferably, the material and the preparation process of the second dielectric layer 206 may be consistent with the material and the preparation process of the first dielectric layer 203, which is not specifically limited in this embodiment. It should be noted that the subsequent preparation process of the pseudo-configured hemt is a process well known to those skilled in the art, and the embodiment is not described herein.

Based on the same inventive concept, the embodiment also provides a pseudo-matched high electron mobility transistor. The pseudo-high electron mobility transistor comprises a grid structure prepared by the preparation method of the pseudo-high electron mobility transistor.

In summary, in the pseudo-matching high electron mobility transistor and the preparation method thereof provided in the present embodiment, the first patterned photoresist layer 202 is formed in the gate groove T to define the gate length of the gate structure, so that the influence of the evaporation angle of the evaporation process on the gate length is avoided, and the flexibility and the accuracy of the gate length definition are improved. Then, the first dielectric layer 203 is used to cover the exposed surfaces of the substrate 200 and the gate groove T, which not only can isolate air, but also can avoid affecting the growth of the gate structure due to oxidation of the inner wall of the gate groove T, improve the connection effect between the gate structure and the substrate 200, ensure the stability of the device on-voltage, avoid the increase of electric leakage, and can also stabilize the gate structure, precisely limit the gate length, and avoid the metal scraps falling into the gate groove T during the stripping process of the photoresist, thereby causing the bigger electric leakage or short circuit of the device. Second, a second patterned photoresist layer 204 is formed on the first dielectric layer 203 to serve as a barrier layer for metal evaporation, and a double-layer photoresist structure is omitted, so that adverse effects on the morphology and device performance of the gate structure due to the problems of unstable photoresist morphology, photoresist residue and the like caused by double-photoresist mutual dissolution are effectively avoided. And finally, forming a grid structure with better appearance by adopting an evaporation process, and improving the performance of the device.

It should also be appreciated that while the present invention has been disclosed in the context of a preferred embodiment, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (10)

1.A method of fabricating a pseudomorphic high electron mobility transistor comprising:

providing a substrate, wherein a grid groove is formed on the substrate;

forming a first patterned photoresist layer on a portion of a bottom surface of the gate trench;

forming a first dielectric layer on the surfaces of the substrate and the first patterned photoresist layer;

removing the first patterned photoresist layer and exposing the partial bottom surface of the gate trench;

forming a second patterned photoresist layer on the surface of the first dielectric layer, and exposing part of the surface of the first dielectric layer and part of the bottom surface of the gate groove;

And taking the second patterned photoresist layer as a barrier, and forming a metal layer on the exposed partial surface of the first dielectric layer and the partial bottom surface of the gate groove to serve as a gate structure.

2. The method of fabricating a pseudomorphic high electron mobility transistor of claim 1 wherein forming the gate trench on the substrate comprises:

forming a third patterned photoresist layer on the surface of the substrate, and exposing a part of the surface of the substrate;

And etching the exposed substrate by taking the third patterned photoresist layer as a barrier to form the gate groove.

3. The method of manufacturing a pseudomorphic high electron mobility transistor of claim 2 wherein the gate trench is formed in the substrate using an anisotropic etching process; and removing the third patterned photoresist layer after forming the gate trench.

4. The method of claim 1, wherein the first patterned photoresist layer has a linewidth equal to a gate length of the gate structure.

5. The method of claim 1, wherein the first dielectric layer further covers sidewalls of the gate trench and exposed bottom surfaces during the forming of the first dielectric layer on the substrate and the first patterned photoresist layer surface.

6. The method of claim 1 or 5, wherein the first dielectric layer and the first patterned photoresist layer on the surface of the first patterned photoresist layer are sequentially removed during the process of removing the first patterned photoresist layer.

7. The method of claim 5, wherein the second patterned photoresist layer exposes the first dielectric layer on sidewalls and bottom surfaces of the gate trench.

8. The method of manufacturing a pseudomorphic high electron mobility transistor of claim 1 or 7 wherein the metal layer is formed by an evaporation process.

9. The method of manufacturing a pseudomorphic high electron mobility transistor of claim 1, characterized in that after forming the metal layer, the method of manufacturing a pseudomorphic high electron mobility transistor further comprises:

removing the second patterned photoresist layer;

And forming a second dielectric layer on the surfaces of the first dielectric layer and the metal layer.

10. A pseudomorphic high electron mobility transistor comprising a gate structure prepared by the method of preparing a pseudomorphic high electron mobility transistor according to any one of claims 1-9.