CN118012210B

CN118012210B - Reference source with adjustable temperature drift curvature

Info

Publication number: CN118012210B
Application number: CN202410411998.8A
Authority: CN
Inventors: 汪荔; 刘银才; 王汉卿; 李雪民
Original assignee: Suzhou Linghui Lixin Technology Co ltd
Current assignee: Suzhou Linghui Lixin Technology Co ltd
Priority date: 2024-04-08
Filing date: 2024-04-08
Publication date: 2024-06-11
Anticipated expiration: 2044-04-08
Also published as: CN118012210A

Abstract

The invention relates to the technical field of reference sources, and particularly discloses a reference source with adjustable temperature drift curvature, which comprises: the reference source circuit is provided with a temperature compensation structure and is provided with a pair of positive and negative input feedback points; and the temperature curvature compensation circuit is electrically connected with the pair of positive and negative input feedback points and is used for performing curvature compensation on the reference source circuit and is suitable for a voltage type or current type reference source. The reference source with adjustable temperature drift curvature provided by the invention can be used for adjusting the curvature and the temperature turning point of the existing voltage/current reference source, so as to realize the optimal curvature, further provide higher-precision output voltage and meet the requirement of high-precision voltage in practical application.

Description

Reference source with adjustable temperature drift curvature

Technical Field

The invention relates to the technical field of reference sources, in particular to a reference source with adjustable temperature drift curvature.

Background

The reference source is an important device in an integrated circuit and can provide reference voltages and reference currents for other circuits. Fig. 1A and 1B show reference sources of conventional voltage/current type that change the components of the father Vbe by adjusting the magnitudes of Ra0, rb0, respectively, to achieve first order temperature coefficient compensation of the output voltage.

However, the first-order temperature coefficient compensation of the reference source of the conventional voltage/current type cannot change the curvature and shape of the reference source along with the temperature change, so as to provide an output voltage with higher precision, and cannot meet the requirement of high-precision low-temperature drift voltage.

Most of the existing high-precision reference sources only comprise a first-order temperature drift compensation circuit, the reference sources with curvature compensation usually need to adopt a complex switch and a current mirror circuit to generate compensation current, the structure is complex, the area is large, and the high curvature still remains after compensation and has relatively large process variation.

Based on the technical background, the invention researches a reference source with adjustable temperature drift curvature, and the curvature after compensation is further reduced.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides the reference source with adjustable temperature drift curvature, which can adjust the curvature and the temperature turning point of the existing voltage/current reference source to realize the optimal curvature, further provide higher-precision output voltage and meet the requirement of high-precision voltage in practical application.

In order to achieve the above object, the present invention provides a reference source with adjustable temperature drift curvature, comprising:

the reference source circuit is provided with a temperature compensation structure and is provided with a pair of positive and negative input feedback points;

and the temperature curvature compensation circuit is electrically connected with the pair of positive and negative input feedback points and is used for performing curvature compensation on the reference source circuit and is suitable for a voltage type or current type reference source.

The technical effects of the invention include:

(1) The reference source with adjustable temperature drift curvature provided by the invention can be used for adjusting the curvature and the temperature turning point of the existing voltage/current reference source, so as to realize the optimal curvature, further provide higher-precision output voltage and meet the requirement of high-precision voltage in practical application.

(2) The reference source with adjustable temperature drift curvature has lower output temperature curvature, thereby realizing better temperature drift performance; the universal type is strong, and is suitable for various voltage or current type structure reference sources; and the structure is simple, the area is small, and the cost is low.

Additional features and advantages of the invention will be set forth in the detailed description which follows.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.

Fig. 1A is a schematic diagram of a reference source circuit of a common voltage type in the prior art.

FIG. 1B is a schematic diagram of a current reference source circuit of the prior art.

Fig. 2 is a schematic diagram of a temperature curvature compensation circuit in a reference source with adjustable temperature drift curvature according to the present invention.

Fig. 3 is a schematic diagram of a bias current generating circuit in a reference source with adjustable temperature drift curvature according to the present invention.

Fig. 4A is a schematic diagram illustrating a connection relationship between a temperature curvature compensation circuit and a voltage-type reference source in an embodiment of a reference source with adjustable temperature drift curvature according to the present invention.

Fig. 4B is a schematic diagram of a specific connection structure between a temperature curvature compensation circuit and a voltage-type reference source in a specific embodiment of a reference source with adjustable temperature drift curvature according to the present invention.

Fig. 5A is a schematic diagram illustrating a connection relationship between a temperature curvature compensation circuit and an amperometric reference source in another embodiment of a temperature drift curvature adjustable reference source according to the present invention.

Fig. 5B is a schematic diagram showing a connection structure between a temperature curvature compensation circuit and an amperometric reference source in another embodiment of the reference source with adjustable temperature drift curvature according to the present invention.

FIG. 6 is a schematic diagram of a first-order temperature compensation curve of a conventional reference source.

FIG. 7 is a comparative schematic diagram of the effect of uncompensated, first order temperature compensation and compensation of the curvature of the reference source output of the present invention.

Reference numerals illustrate:

A1-a first amplifier, A2-a second amplifier; ra1, ra 2-feedback resistor, ra 0-first voltage dividing resistor, mb1, mb 2-feedback PMOS tube, mb 3-mirror PMOS tube, rb1, rb 2-bypass resistor, rb 0-second voltage dividing resistor, rb 3-third voltage dividing resistor, Q1-first bipolar transistor, Q2-second bipolar transistor, Q3-third bipolar transistor, Q4-fourth bipolar transistor, PCC-temperature curvature compensation circuit;

a CTM-negative temperature coefficient current mirror, a CTG-adjustable negative temperature coefficient current generation structure, a ZTG-zero temperature coefficient current generation structure, biasc-a first bias generation structure, biasc-a second bias generation structure, biascm-a current source structure;

Mnp1, mnp 2-pull-down current NMOS, mnm-mirror NMOS, mptp, mptp 2-negative temperature coefficient generating PMOS, mptn1, mptn 2-negative temperature coefficient generating NMOS, iptat _trim-PTAT trimming current source, mztp1, mztp-zero temperature coefficient generating PMOS, mztn-zero temperature coefficient voltage dividing NMOS, rzt-zero temperature coefficient voltage dividing resistor, qr-feedback bipolar transistor, iptat-first PTAT current source, iptat-second PTAT current source, mbp1_1, mbp1_2, mbp2_1, mbp2_2-PMOS bias, mbn1, mbn2-NMOS bias, mmbp1_1, mmbp1_2, mmbp2_1, mmbp2_2-PMOS current mirror bias, qb1, qb 2-bipolar bias, rb-bias resistor, mscp _1, mscp _2, mscp _1, mb2_2, mbp2_2, 3932_2-PMOS, mscp-2-PMOS current mirror bias, 3931, mscp-PMOS, mscp-2-PMOS;

Vref-reference power output, icc_out-curvature compensation current, ictat _gen-negative temperature coefficient current, iztat _gen-zero temperature coefficient current, iptat _trim positive temperature coefficient trimming current, iptat-first positive temperature coefficient current, iptat 2-first positive temperature coefficient current, vdd-power, k 1-trimming coefficient, and mirror ratio of k 2-pull-down current NMOS tube to mirror NMOS tube.

Detailed Description

Preferred embodiments of the present invention will be described in more detail below. While the preferred embodiments of the present invention are described below, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein.

In the present invention, unless otherwise indicated, terms of orientation such as "upper and lower" are used to generally refer to the upper and lower portions of the device in normal use, and "inner and outer" are used with respect to the profile of the device. Furthermore, the terms "first, second, third and the like" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first, second, third" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The present invention provides a reference source with adjustable temperature drift curvature, as shown in fig. 2-5B, comprising:

and the temperature curvature compensation circuit PCC is electrically connected with the pair of positive and negative input feedback points and is used for performing curvature compensation on the reference source circuit and is suitable for a voltage type or current type reference source.

In the invention, the curvature and the temperature turning point can be adjusted by the existing voltage/current reference source, so that the optimal curvature is realized, the output voltage with higher precision is further provided, and the requirement of high-precision voltage in practical application is met.

According to the invention, the reference source circuit is a voltage-type reference source circuit or a current-type reference source circuit;

the voltage type reference source circuit comprises a first amplifier A1, a pair of feedback resistors Ra1 and Ra2, a first voltage dividing resistor Ra0, a first bipolar transistor Q1 and a second bipolar transistor Q2;

the non-inverting input end of the first amplifier A1 is electrically connected with one end of one feedback resistor Ra1, and the inverting input end of the first amplifier A1 is electrically connected with one end of the other feedback resistor Ra 2;

the other ends of the two feedback resistors Ra1 and Ra2 are electrically connected with the output end of the first amplifier A1 together;

The non-inverting input end of the first amplifier A1 is also electrically connected with the collector of the first bipolar transistor Q1, and the inverting input end is also electrically connected with the collector of the second bipolar transistor Q2 through a first voltage dividing resistor Ra 0;

The collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 are respectively and electrically connected with the respective bases, and the emitters are commonly and electrically connected;

the non-inverting input end and the inverting input end of the first amplifier A1 serve as a pair of positive and negative input feedback points, and the output end serves as a reference power supply output end.

According to the present invention, the current-mode reference source circuit includes a second amplifier A2, a pair of feedback PMOS transistors Mb1, mb2, a mirror PMOS transistor Mb3, a pair of shunt resistors Rb1, rb2, a second shunt resistor Rb0, a third shunt resistor Rb3, a third bipolar transistor Q3, and a fourth bipolar transistor Q4;

The non-inverting input end of the second amplifier A2 is electrically connected with the drain electrode of one feedback PMOS tube Mb2, and the inverting input end is electrically connected with the drain electrode of the other feedback PMOS tube Mb 1;

The grid electrodes of the two feedback PMOS tubes Mb1 and Mb2 are electrically connected with the output end of the second amplifier A2 together, and the source electrodes are electrically connected with a power supply;

the inverting input end of the second amplifier A2 is also electrically connected with the collector electrode of the third bipolar transistor Q3, and the non-inverting input end is also electrically connected with the collector electrode of the fourth bipolar transistor Q4 through a second voltage dividing resistor Rb 0;

the collectors of the third bipolar transistor Q3 and the fourth bipolar transistor Q4 are respectively and electrically connected with the respective bases, and the emitters are commonly and electrically connected;

The non-inverting input end of the second amplifier A2 is also electrically connected with one end of one bypass resistor Rb1, and the inverting input end is also electrically connected with one end of the other bypass resistor Rb 2;

The other ends of the two bypass resistors Rb1 and Rb2 are electrically connected with ground;

The source electrode of the mirror PMOS tube Mb3 is electrically connected with a power supply, the drain electrode is electrically connected with one end of a third voltage dividing resistor Rb3, and the grid electrode is electrically connected with the output end of the second amplifier A2;

the other end of the third voltage dividing resistor Rb3 is electrically connected with ground;

The non-inverting input end and the inverting input end of the second amplifier A2 serve as a pair of positive and negative input feedback points;

The drain electrode of the mirror PMOS tube Mb3 is used as a reference voltage output end.

According to the invention, the temperature curvature compensation circuit PCC comprises a negative temperature coefficient current mirror CTM, an adjustable negative temperature coefficient current generating structure CTG and a zero temperature coefficient current generating structure ZTG;

The negative temperature coefficient current mirror CTM comprises a pair of pull-down current NMOS transistors Mnp1 and Mnp2 and a mirror NMOS transistor Mnm;

The drains of the two pull-down current NMOS tubes Mnp1 and Mnp2 are respectively and electrically connected with a pair of positive and negative input feedback points, the grid electrode is electrically connected with the grid electrode of the mirror NMOS tube Mnm, and the sources are electrically connected with ground;

The sources of the mirror NMOS transistors Mnm are electrically connected with each other, and the gates are electrically connected with the drains of the mirror NMOS transistors Mnm.

Preferably, the adjustable negative temperature coefficient current generating structure CTG includes a pair of negative temperature coefficient generating PMOS transistors Mptp, mptp2, a pair of negative temperature coefficient generating NMOS transistors Mptn, mptn2, and a PTAT trimming current source iptat _trim;

The sources of the two negative temperature coefficient generating PMOS tubes Mptp and Mptp2 are electrically connected with a power supply, and the grids are electrically connected with each other;

The drain electrode of the first negative temperature coefficient generating PMOS tube Mptp is electrically connected with one end of the PTAT trimming current source iptat _trim and the drain electrode of the mirror NMOS tube Mnm at the same time, and the grid electrode of the second PMOS tube is electrically connected with the source electrode of the second PMOS tube;

the other end of the PTAT trimming current source iptat _trim is electrically connected with ground;

The sources of the two negative temperature coefficient generating NMOS transistors Mptn and Mptn2 are electrically connected with each other, and the grids are electrically connected with each other;

The drain of the first negative temperature coefficient generation NMOS tube Mptn is electrically connected with the drain of the second negative temperature coefficient generation PMOS tube Mptp;

the grid electrode of the second negative temperature coefficient generating NMOS tube Mptn is electrically connected with the source electrode of the second negative temperature coefficient generating NMOS tube;

The negative temperature coefficient current ictat _gen in the negative temperature coefficient current mirror CTM is the difference between the zero temperature coefficient current iztat _gen in the adjustable negative temperature coefficient current generating structure CTG and the PTAT trimming current source trim.

According to the present invention, the zero temperature coefficient current generating structure ZTG includes a pair of zero temperature coefficient generating PMOS transistors Mztp, mztp2, a zero temperature coefficient voltage dividing NMOS transistor Mztn, a zero temperature coefficient voltage dividing resistor Rzt, a feedback bipolar transistor Qr, a first PTAT current source iptat, and a second PTAT current source iptat;

The sources of the two zero temperature coefficient generation PMOS tubes Mztp and Mztp2 are electrically connected with a power supply, and the grids are electrically connected with each other;

the drain of the first zero temperature coefficient generation PMOS tube Mztp and one end of the second PTAT current source iptat are electrically connected to the drain of the second negative temperature coefficient generation NMOS tube Mptn at the same time;

the grid electrode of the second zero temperature coefficient generation PMOS tube Mztp is electrically connected with the drain electrode of the second zero temperature coefficient generation PMOS tube Mztp, and the drain electrode is electrically connected with the drain electrode of the zero temperature coefficient voltage division NMOS tube Mztn;

The source electrode of the zero temperature coefficient voltage dividing NMOS tube Mztn is electrically connected with one end of the zero temperature coefficient voltage dividing resistor Rzt and the base electrode of the feedback bipolar transistor Qr at the same time;

the other end of the zero temperature coefficient voltage dividing resistor Rzt and the emitter electrode of the feedback bipolar transistor Qr are all electrically connected;

one end of the first PTAT current source iptat is electrically connected with a power supply, and the other end is electrically connected with the grid electrode of the zero temperature coefficient voltage division NMOS tube Mztn and the collector electrode of the feedback bipolar transistor Qr;

The base-emitter voltage differential of the feedback bipolar transistor Qr is applied to the zero temperature coefficient voltage divider resistor Rzt to generate the negative temperature coefficient current ictat _gen, which is added to the output of the second PTAT current source iptat2 to generate the zero temperature coefficient current iztat _gen.

According to the present invention, the first PTAT current source iptat, the second PTAT current source iptat, and the PTAT trimming current source iptat _trim are all generated by a bias current generating circuit;

The bias current generating circuit includes a first bias generating structure Biasc, a second bias generating structure Biasc, and a current source structure Biascm.

Preferably, the first bias generating structure Biasc includes two pairs of PMOS bias transistors mbp1_1, mbp1_2, mbp2_1, mbp2_2 and a pair of NMOS bias transistors Mbn1, mbn2;

The source electrode of the first PMOS bias tube Mbp1_1 and Mbp2_1 in each pair of PMOS bias tubes Mbp1_1 and Mbp1_2 or Mbp2_2 is electrically connected with a power supply, and the drain electrode is correspondingly electrically connected with the source electrode of the second PMOS bias tube Mbp1_2 and Mbp2_2;

The sources of the two NMOS bias tubes Mbn1 and Mbn2 are electrically connected with each other, and the grids are electrically connected with each other;

The grid electrode of the first NMOS bias tube Mbn1 is electrically connected with the drain electrode of the first NMOS bias tube Mbp1_1 and the drain electrode of the second PMOS bias tube Mbp1_2 in the first pair of PMOS bias tubes Mbp1_1 and Mbp1_2, and the drain electrode of the second NMOS bias tube Mbn2 is electrically connected with the drain electrode of the second PMOS bias tube Mbp2_2 in the second pair of PMOS bias tubes Mbp2_1 and Mbp2_2;

The gate of the second PMOS bias tube mbp2_2 of the second pair of PMOS bias tubes mbp2_1, mbp2_2 is electrically connected to the drain thereof, the gate of the first PMOS bias tube mbp2_1 of the second pair of PMOS bias tubes mbp2_1, mbp2_2, and the gate of the second PMOS bias tube mbp1_2 of the first pair of PMOS bias tubes mbp1_1, mbp1_2 at the same time.

According to the present invention, the second bias generating structure Biasc includes a PMOS bias current mirror, a pair of bipolar bias tubes Qb1, qb2, and a bias resistor Rb;

The PMOS bias current mirror includes two pairs of PMOS current mirror bias tubes Mmbp _1, mmbp _2, mmbp2_1, mmbp2_2;

The gates of PMOS current mirror bias tubes Mmbp1_1, mmbp1 _1_2 are electrically connected to each other, and the gates of PMOS current mirror bias tubes Mmbp2_1, mmbp2_2 are electrically connected to each other;

The sources of the two PMOS current mirror bias tubes Mmbp1_1, mmbp1_2 of the first pair of PMOS current mirror bias tubes Mmbp1_1, mmbp1 _1_2 are electrically connected to a power supply, the drains are electrically connected to the sources of the two PMOS current mirror bias tubes Mmbp2_1, mmbp2_2 of the second pair of PMOS current mirror bias tubes Mmbp2 _2_1, mmbp2_2, respectively, the gates are electrically connected to the drain of the second PMOS current mirror bias tube Mmbp2_2 of the second pair of PMOS current mirror bias tubes Mmbp2_1, mmbp2_2, and the gate of the first PMOS bias tube mbp1_1 of the first pair of PMOS bias tubes mbp1_2;

the drain of the first PMOS current mirror bias tube Mmbp2_1 of the second pair of PMOS current mirror bias tubes Mmbp2_1, mmbp2_2 is electrically connected to the collector of the first bipolar bias tube Qb 1;

The bases of two bipolar bias tubes Qb1, qb2 of a pair of bipolar bias tubes Qb1, qb2 are electrically connected to each other;

The base electrode of the first bipolar bias tube Qb1 is electrically connected with the collector electrode of the first bipolar bias tube Qb1, and the emitter electrode is electrically connected with the ground;

The collector of the second bipolar bias tube Qb2 is electrically connected to the drains of the second PMOS current mirror bias tubes Mmbp2_1, mmbp2_2 of the second pair of PMOS current mirror bias tubes Mmbp2_2, mmbp2_2, and the emitter is electrically connected to one end of the bias resistor Rb;

the other end of the bias resistor Rb is electrically connected to ground.

According to the present invention, current source structure Biascm includes a first PTAT current source iptat1, a second PTAT current source iptat, and a PTAT trimming current source iptat _trim;

The first PTAT current source iptat and the second PTAT current source iptat are a pair of PMOS transistors Mscp1_1, mscp1_2 and mscp2_1, mscp2_2 connected in series;

The source of the first PMOS tube Mscp _1, mscp2_1 of each pair of PMOS tubes Mscp _1, mscp1_2, mscp2_1, mscp2_2 connected in series is electrically connected with a power supply, the drain is electrically connected with the source of the second PMOS tube Mscp1_2, mscp2_2, the gate is electrically connected with the gate of the first PMOS bias tube Mbp1_1 of the first pair of PMOS bias tubes Mbp1_1, mbp1_2, the gate of the second PMOS tube is electrically connected with the gate of the second PMOS bias tube Mbp1_2 of the first pair of PMOS bias tubes Mbp1_1, mbp1_2, and the drain is a current source output end;

The PTAT trimming current source iptat _trim includes a plurality of pairs of PMOS trimming tubes Mtrp1_1, mtrp1_2, mtrp2_1, mtrp2_ … … Mtrpn _1, mtrpn _2 and a pair of NMOS trimming tubes Mtrn1, mtrn2;

The source electrode of the first PMOS trimming tube Mtrp _1, mtrp2_1 and … … Mtrpn _1 in each pair of PMOS trimming tubes is electrically connected with a power supply, the drain electrode is electrically connected with the source electrode of the second PMOS trimming tube Mtrp _2 and Mtrp2_ … … Mtrpn _2, and the grid electrode is electrically connected with the grid electrode of the first PMOS biasing tube Mbp1_1 in the first pair of PMOS biasing tubes Mbp1_1 and Mbp1_2;

The drain electrodes of the second PMOS trimming tube Mtrp _2 and Mtrp _ … … Mtrpn _2 in each pair of PMOS trimming tubes are electrically connected with the drain electrode of the first NMOS trimming tube Mtrn;

the grid electrodes of the two NMOS trimming tubes Mtrn and Mtrn are electrically connected with each other;

The grid electrode of the first NMOS trimming tube Mtrn is electrically connected with the drain electrode of the first NMOS trimming tube, and the drain electrode of the second NMOS trimming tube Mtrn is a current pull-in end;

The gate of the second one of the at least one pair of PMOS trimming transistors Mtrp1_1, mtrp1 _1_2, mtrp2_1, mtrp2 _2_ 2 … … Mtrpn _1, mtrpn _2 is electrically connected to the gate of the second one of the first pair of PMOS biasing transistors mbp1_1, mbp1_2, and the gates of the remaining pairs of PMOS trimming transistors float.

In the invention, the curvature of the output temperature is lower, thereby realizing better temperature drift performance; the universal type is strong, and is suitable for various voltage or current type structure reference sources; and the structure is simple, the area is small, and the cost is low.

In the present invention, fig. 1A and 1B show reference sources of conventional voltage/current type, and their basic formulas of band gap (Bandgap reference) temperature drift compensation are:

；

Wherein Vbe is the voltage between the base and emitter of the bipolar transistor, has negative temperature coefficient characteristics, and contains a temperature nonlinear term (curvature);

；

the voltage difference between the base and the emitter of the two bipolar transistors has positive temperature coefficient characteristics;

And/> And overlapping according to a certain proportion to obtain the reference voltage with zero temperature coefficient, wherein the reference voltage is shown as the following formula:

；

the first-order temperature coefficient in the formula is compensated, the nonlinear curvature is remained, and the compensation curve is shown in figure 6;

FIG. 1A shows a reference source of a conventional voltage type, and FIG. 1B shows a reference source of a conventional current type, which change the components of Vbe by adjusting the magnitudes of Ra0, rb0, respectively, so as to achieve first-order temperature coefficient compensation of the output voltage;

the output formula of the voltage-type reference source is divided into:

wherein Ra1 = Ra2;

The output formula of the current reference source is:

wherein rb1=rb2.

In the invention CTAT (complementary to absolute temperature) represents the negative temperature coefficient which is complementary to the absolute temperature; PTAT (proportional to absolute temperaute), which is proportional to temperature and is a positive temperature coefficient; ZTAT (zero to absolute temperature) denotes zero temperature coefficient, which does not vary with temperature.

In the present invention, the temperature curvature compensation circuit PCC and the bias current generation circuit shown in fig. 2 and 3 are used to compensate the reference source of the conventional voltage/current type shown in fig. 1A and 1B, respectively, and the specific compensation circuit is shown in fig. 4A, 4B, 5A and 5B;

Fig. 4A and fig. 4B are diagrams illustrating compensation for a reference source of a conventional voltage type, and the compensation calculation formula is as follows:

；

fig. 5A and 5B are diagrams showing compensation for a reference source of a conventional current type, and the compensation calculation formula is as follows:

；

As shown in fig. 4B and 5B, subtracting the iztat _gen current from the slope-adjustable iptat current creates a slope-variable icc_out current flowing into/out of the reference source circuit, thereby changing the magnitude and shape of the curvature of the reference source with temperature; adjusting the magnitude of the current mirror proportion k2 to change the magnitude of the absolute value of the icc_out so as to change the curvature of the reference source; the temperature curvature compensation circuit PCC can enable the curvature of the output temperature of the reference source to be lower by adjusting the magnitude of the trimming coefficient k1 to change the slope of the icc_out to change the temperature turning point of the curvature of the reference source, as shown in FIG. 7, so that better temperature drift performance is realized.

The invention will be described in more detail by means of a specific example.

Example 1

As shown in fig. 4A and 4B, the present embodiment provides a reference source with adjustable temperature drift curvature, for compensating for a conventional voltage type reference source, including:

The temperature curvature compensation circuit PCC is electrically connected with a pair of positive and negative input feedback points and is used for performing curvature compensation on the reference source circuit and is suitable for a voltage type or current type reference source;

In this embodiment, the reference source circuit is a voltage-type reference source circuit;

The non-inverting input end and the inverting input end of the first amplifier A1 are used as a pair of positive and negative input feedback points, and the output end is used as a reference power supply output end;

In this embodiment, the temperature curvature compensation circuit PCC includes a negative temperature coefficient current mirror CTM, an adjustable negative temperature coefficient current generation structure CTG, and a zero temperature coefficient current generation structure ZTG;

the source electrodes of the mirror NMOS tubes Mnm are electrically connected with each other, and the grid electrodes are electrically connected with the drain electrodes of the mirror NMOS tubes Mnm;

the adjustable negative temperature coefficient current generation structure CTG comprises a pair of negative temperature coefficient generation PMOS (P-channel metal oxide semiconductor) tubes Mptp and Mptp2, a pair of negative temperature coefficient generation NMOS (N-channel metal oxide semiconductor) tubes Mptn and Mptn2 and a PTAT trimming current source iptat _trim;

the negative temperature coefficient current ictat _gen in the negative temperature coefficient current mirror CTM is the difference between the zero temperature coefficient current iztat _gen in the adjustable negative temperature coefficient current generating structure CTG and the PTAT trimming current source trim;

The zero temperature coefficient current generation structure ZTG includes a pair of zero temperature coefficient generation PMOS transistors Mztp, mztp2, a zero temperature coefficient voltage dividing NMOS transistor Mztn, a zero temperature coefficient voltage dividing resistor Rzt, a feedback bipolar transistor Qr, a first PTAT current source iptat, and a second PTAT current source iptat;

the base-emitter voltage difference of the feedback bipolar transistor Qr is loaded on the zero temperature coefficient voltage dividing resistor Rzt to generate a negative temperature coefficient current ictat _gen, and the negative temperature coefficient current ictat _gen is added with the output of the second PTAT current source iptat to generate a zero temperature coefficient current iztat _gen;

the first PTAT current source iptat, the second PTAT current source iptat, and the PTAT trimming current source iptat _trim are all generated by a bias current generating circuit;

The bias current generating circuit includes a first bias generating structure Biasc, a second bias generating structure Biasc, and a current source structure Biascm;

in this embodiment, the first bias generating structure Biasc includes two pairs of PMOS bias transistors mbp1_1, mbp1_2, mbp2_1, mbp2_2 and a pair of NMOS bias transistors Mbn1, mbn2;

The gate of the second PMOS bias tube mbp2_1, mbp2_2 of the second pair of PMOS bias tubes mbp2_1, mbp2_2 is electrically connected to the drain thereof, the gate of the first PMOS bias tube mbp2_1 of the second pair of PMOS bias tubes mbp2_1, mbp2_2, and the gate of the second PMOS bias tube mbp1_2 of the first pair of PMOS bias tubes mbp1_1, mbp1_2 at the same time;

The second bias generating structure Biasc includes a PMOS bias current mirror, a pair of bipolar bias tubes Qb1, qb2, and a bias resistor Rb;

the other end of the bias resistor Rb is electrically connected with ground;

the current source structure Biascm includes a first PTAT current source iptat1, a second PTAT current source iptat, and a PTAT trimming current source iptat _trim;

In this embodiment, the PTAT trimming current source iptat _trim includes four pairs of PMOS trimming tubes Mtrp1_1, mtrp1_2, mtrp2 _2_1, mtrp2_2 … … Mtrp4 _4_1, mtrp4 _4_2 and a pair of NMOS trimming tubes Mtrn1, mtrn2;

The source electrode of the first PMOS trimming tube Mtrp _1, mtrp2_1 and … … Mtrp4_1 in each pair of PMOS trimming tubes is electrically connected with a power supply, the drain electrode is electrically connected with the source electrode of the second PMOS trimming tube Mtrp _2 and Mtrp2_ … … Mtrp4_2, and the grid electrode is electrically connected with the grid electrode of the first PMOS biasing tube Mbp1_1 in the first pair of PMOS biasing tubes Mbp1_1 and Mbp1_2;

the drain electrodes of the second PMOS trimming tube Mtrp _2, mtrp2_ … … Mtrp4_2 of each pair of PMOS trimming tubes are electrically connected with the drain electrode of the first NMOS trimming tube Mtrn 1;

The gates of the second PMOSMtrp1_2 trimming tube of the first pair of PMOS trimming tubes Mtrp1_1, mtrp1_2 of the four pairs of PMOS trimming tubes Mtrp1_1, mtrp1 _1_2, mtrp2_1, mtrp2_2 … … Mtrpn _1, mtrpn _2 are electrically connected with the gates of the second PMOS biasing tube mbp1_2 of the first pair of PMOS biasing tubes mbp1_1, mbp1_2, and the gates of the second PMOS trimming tubes of the remaining pairs of PMOS trimming tubes float to obtain the optimal trimming coefficient k1.

Example 2

As shown in fig. 5A and 5B, the present embodiment provides a reference source with adjustable temperature drift curvature, for compensating for a conventional current-type reference source, including:

In this embodiment, the reference source circuit is a current-type reference source circuit;

The current-type reference source circuit comprises a second amplifier A2, a pair of feedback PMOS transistors Mb1 and Mb2, a mirror PMOS transistor Mb3, a pair of bypass resistors Rb1 and Rb2, a second voltage dividing resistor Rb0, a third voltage dividing resistor Rb3, a third bipolar transistor Q3 and a fourth bipolar transistor Q4;

The drain electrode of the mirror PMOS tube Mb3 is used as a reference voltage output end;

the temperature curvature compensation circuit PCC comprises a negative temperature coefficient current mirror CTM, an adjustable negative temperature coefficient current generation structure CTG and a zero temperature coefficient current generation structure ZTG;

In this embodiment, the first PTAT current source iptat, the second PTAT current source iptat, and the PTAT trimming current source iptat _trim are all generated by a bias current generating circuit;

The first bias generation structure Biasc includes two pairs of PMOS bias transistors mbp1_1, mbp1_2, mbp2_1, mbp2_2 and a pair of NMOS bias transistors Mbn1, mbn2;

the other end of the bias resistor Rb is electrically connected with ground;

In this embodiment, the current source structure Biascm includes a first PTAT current source iptat1, a second PTAT current source iptat, and a PTAT trimming current source iptat _trim;

The PTAT trimming current source iptat _trim includes three pairs of PMOS trimming tubes Mtrp1_1, mtrp1_2, mtrp2 _2_1, mtrp2_2, mtrp3 _3, mtrp3_2 and a pair of NMOS trimming tubes Mtrn1, mtrn2; the source electrode of the first PMOS trimming tube Mtrp _1, mtrp2 _2_1 and Mtrp3_1 in each pair of PMOS trimming tubes is electrically connected with a power supply, the drain electrode is electrically connected with the source electrode of the second PMOS trimming tube Mtrp _2, mtrp2_2 and Mtrp3_2, and the grid electrode is electrically connected with the grid electrode of the first PMOS biasing tube Mbp1_1 in the first pair of PMOS biasing tubes Mbp1_1 and Mbp1_2;

The drain electrodes of the second PMOS trimming tube Mtrp _2, mtrp2_2, mtrp3_2 in each pair of PMOS trimming tubes are electrically connected with the drain electrode of the first NMOS trimming tube Mtrn 1;

The grid electrode of the second one of the two pairs of PMOS trimming tubes Mtrp _1, mtrp _2, mtrp2_1, mtrp _2, mtrp3_1, mtrp _2 is electrically connected with the grid electrode of the second one of the first pair of PMOS bias tubes Mbp1_1, mbp1_2, and the grid electrode of the second one of the other pair of PMOS trimming tubes floats to obtain the optimal trimming coefficient k1.

The reference source with adjustable temperature drift curvature in the embodiment of the invention can adjust the curvature and the temperature turning point of the existing voltage/current reference source to realize the optimal curvature, thereby providing higher-precision output voltage and meeting the requirement of high-precision voltage in practical application.

The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.

Claims

1. A temperature drift curvature adjustable reference source comprising:

The temperature curvature compensation circuit is electrically connected with the pair of positive and negative input feedback points and is used for performing curvature compensation on the reference source circuit and is suitable for a voltage type or current type reference source;

the reference source circuit is a voltage-type reference source circuit or a current-type reference source circuit;

the voltage type reference source circuit comprises a first amplifier, a pair of feedback resistors, a first voltage dividing resistor, a first bipolar transistor and a second bipolar transistor;

The non-inverting input end of the first amplifier is electrically connected with one end of one feedback resistor, and the inverting input end of the first amplifier is electrically connected with one end of the other feedback resistor;

the other ends of the two feedback resistors are electrically connected with the output end of the first amplifier together;

the non-inverting input end of the first amplifier is also electrically connected with the collector electrode of the first bipolar transistor, and the inverting input end of the first amplifier is also electrically connected with the collector electrode of the second bipolar transistor through the first voltage dividing resistor;

the collectors of the first bipolar transistor and the second bipolar transistor are respectively and electrically connected with the respective bases, and the emitters are commonly and electrically connected with the ground;

The non-inverting input end and the inverting input end of the first amplifier are used as the pair of positive and negative input feedback points, and the output end is used as a reference power supply output end;

The current-type reference source circuit comprises a second amplifier, a pair of feedback PMOS (P-channel metal oxide semiconductor) transistors, a mirror PMOS transistor, a pair of bypass resistors, a second voltage dividing resistor, a third bipolar transistor and a fourth bipolar transistor;

The non-inverting input end of the second amplifier is electrically connected with the drain electrode of one feedback PMOS tube, and the inverting input end of the second amplifier is electrically connected with the drain electrode of the other feedback PMOS tube;

The grid electrodes of the two feedback PMOS tubes are electrically connected with the output end of the second amplifier together, and the source electrodes are electrically connected with a power supply;

the inverting input end of the second amplifier is also electrically connected with the collector electrode of the third bipolar transistor, and the non-inverting input end of the second amplifier is also electrically connected with the collector electrode of the fourth bipolar transistor through the second voltage dividing resistor;

the collectors of the third bipolar transistor and the fourth bipolar transistor are respectively and electrically connected with the respective bases, and the emitters are commonly and electrically connected with the ground;

The non-inverting input end of the second amplifier is also electrically connected with one end of one bypass resistor, and the inverting input end of the second amplifier is also electrically connected with one end of the other bypass resistor;

The other ends of the two bypass resistors are electrically connected with ground;

The source electrode of the mirror image PMOS tube is electrically connected with a power supply, the drain electrode of the mirror image PMOS tube is electrically connected with one end of the third voltage dividing resistor, and the grid electrode of the mirror image PMOS tube is electrically connected with the output end of the second amplifier;

the other end of the third voltage dividing resistor is electrically connected with ground;

the non-inverting input end and the inverting input end of the second amplifier are used as the pair of positive and negative input feedback points;

the drain electrode of the mirror image PMOS tube is used as a reference voltage output end;

The temperature curvature compensation circuit comprises a negative temperature coefficient current mirror, an adjustable negative temperature coefficient current generation structure and a zero temperature coefficient current generation structure;

The negative temperature coefficient current mirror comprises a pair of pull-down current NMOS tubes and mirror NMOS tubes;

The drains of the two pull-down current NMOS tubes are respectively and electrically connected with the pair of positive and negative input feedback points, the grid electrode is electrically connected with the grid electrode of the mirror NMOS tube, and the sources are electrically connected with the ground;

the source electrodes of the mirror NMOS tubes are electrically connected with each other, and the grid electrodes of the mirror NMOS tubes are electrically connected with the drain electrodes of the mirror NMOS tubes;

The adjustable negative temperature coefficient current generation structure comprises a pair of negative temperature coefficient generation PMOS (P-channel metal oxide semiconductor) tubes, a pair of negative temperature coefficient generation NMOS (N-channel metal oxide semiconductor) tubes and a PTAT trimming current source;

The sources of the two negative temperature coefficient generating PMOS tubes are electrically connected with a power supply, and the grids are electrically connected with each other;

The drain electrode of the first negative temperature coefficient generating PMOS tube is electrically connected with one end of the PTAT trimming current source and the drain electrode of the mirror NMOS tube at the same time, and the grid electrode of the second PMOS tube is electrically connected with the source electrode of the second PMOS tube;

The other end of the PTAT trimming current source is electrically connected with the ground;

The sources of the two negative temperature coefficient generating NMOS tubes are electrically connected with each other, and the grids are electrically connected with each other;

The drain electrode of the first negative temperature coefficient generating NMOS tube is electrically connected with the drain electrode of the second negative temperature coefficient generating PMOS tube;

The grid electrode of the second negative temperature coefficient generating NMOS tube is electrically connected with the source electrode of the second negative temperature coefficient generating NMOS tube;

The negative temperature coefficient current in the negative temperature coefficient current mirror is the difference between the zero temperature coefficient current in the adjustable negative temperature coefficient current generating structure and the PTAT trimming current source;

The zero temperature coefficient current generation structure comprises a pair of zero temperature coefficient generation PMOS (P-channel metal oxide semiconductor) tubes, a zero temperature coefficient voltage division NMOS (N-channel metal oxide semiconductor) tube, a zero temperature coefficient voltage division resistor, a feedback bipolar transistor, a first PTAT current source and a second PTAT current source;

The sources of the two zero temperature coefficient generation PMOS tubes are electrically connected with a power supply, and the grids are electrically connected with each other;

One end of the drain electrode of the first zero temperature coefficient generation PMOS tube and one end of the second PTAT current source are electrically connected with the drain electrode of the second negative temperature coefficient generation NMOS tube at the same time;

the grid electrode of the second zero temperature coefficient generation PMOS tube is electrically connected with the drain electrode of the second zero temperature coefficient generation PMOS tube, and the drain electrode is electrically connected with the drain electrode of the zero temperature coefficient voltage division NMOS tube;

The source electrode of the zero temperature coefficient voltage dividing NMOS tube is electrically connected with one end of the zero temperature coefficient voltage dividing resistor and the base electrode of the feedback bipolar transistor at the same time;

the other end of the zero temperature coefficient voltage dividing resistor and the emitter electrode of the feedback bipolar transistor are electrically connected with each other;

One end of the first PTAT current source is electrically connected with a power supply, and the other end of the first PTAT current source is electrically connected with the grid electrode of the zero temperature coefficient voltage division NMOS tube and the collector electrode of the feedback bipolar transistor;

The base-emitter voltage difference of the feedback bipolar transistor is loaded on the zero temperature coefficient voltage dividing resistor to generate negative temperature coefficient current, and the negative temperature coefficient current is added with the output of the second PTAT current source to generate zero temperature coefficient current.

2. The reference source of claim 1, wherein the first PTAT current source, the second PTAT current source, and the PTAT trimming current source are each generated by a bias current generating circuit;

The bias current generating circuit includes a first bias generating structure, a second bias generating structure, and a current source structure.

3. The reference source of claim 2, wherein the first bias generating structure comprises two pairs of PMOS bias tubes and a pair of NMOS bias tubes;

The source electrode of a first PMOS bias tube in each pair of PMOS bias tubes is electrically connected with a power supply, and the drain electrode is electrically connected with the source electrode of a second PMOS bias tube;

the sources of the two NMOS bias tubes are electrically connected with each other, and the grids are electrically connected with each other;

the grid electrode of the first NMOS bias tube is electrically connected with the drain electrode of the first NMOS bias tube and the drain electrode of the second PMOS bias tube in the first pair of PMOS bias tubes at the same time, and the drain electrode of the second NMOS bias tube is electrically connected with the drain electrode of the second PMOS bias tube in the second pair of PMOS bias tubes;

The grid electrode of the second PMOS bias tube in the second pair of PMOS bias tubes is electrically connected with the drain electrode of the second PMOS bias tube, the grid electrode of the first PMOS bias tube in the second pair of PMOS bias tubes and the grid electrode of the second PMOS bias tube in the first pair of PMOS bias tubes.

4. A reference source as claimed in claim 3, wherein the second bias generating structure comprises a PMOS bias current mirror, a pair of bipolar bias tubes and a bias resistor;

the PMOS bias current mirror comprises two pairs of PMOS current mirror bias tubes;

The grid electrodes of the two PMOS current mirror bias tubes in each pair of PMOS current mirror bias tubes are mutually and electrically connected;

the sources of the two PMOS current mirror bias tubes in the first pair of PMOS current mirror bias tubes are electrically connected with a power supply, the drains of the two PMOS current mirror bias tubes in the second pair of PMOS current mirror bias tubes are respectively electrically connected with the sources of the two PMOS current mirror bias tubes, and the grid of the two PMOS current mirror bias tubes in the second pair of PMOS current mirror bias tubes is simultaneously electrically connected with the drain of the second PMOS current mirror bias tube in the second pair of PMOS current mirror bias tubes and the grid of the first PMOS bias tube in the first pair of PMOS bias tubes;

The drain electrode of a first PMOS current mirror bias tube in the second pair of PMOS current mirror bias tubes is electrically connected with the collector electrode of the first bipolar bias tube;

The bases of two bipolar bias tubes in the pair of bipolar bias tubes are electrically connected with each other;

The base electrode of the first bipolar bias tube is electrically connected with the collector electrode of the first bipolar bias tube, and the emitter electrode of the first bipolar bias tube is electrically connected with the ground;

the collector electrode of the second bipolar bias tube is electrically connected with the drain electrode of the second PMOS current mirror bias tube in the second pair of PMOS current mirror bias tubes, and the emitter electrode is electrically connected with one end of the bias resistor;

the other end of the bias resistor is electrically connected with ground.

5. The reference source of claim 4, wherein the current source structure comprises a first PTAT current source, a second PTAT current source, and a PTAT trimming current source;

The first PTAT current source and the second PTAT current source are a pair of PMOS tubes connected in series;

The source electrode of the first PMOS tube in each pair of PMOS tubes connected in series is electrically connected with a power supply, the drain electrode is electrically connected with the source electrode of the second PMOS tube in each pair of PMOS tubes, the grid electrode is electrically connected with the grid electrode of the first PMOS bias tube in the first pair of PMOS bias tubes, the grid electrode of the second PMOS tube is electrically connected with the grid electrode of the second PMOS bias tube in the first pair of PMOS bias tubes, and the drain electrode is a current source outlet end;

the PTAT trimming current source comprises a plurality of pairs of PMOS trimming tubes and a pair of NMOS trimming tubes;

The source electrode of a first PMOS trimming tube in each pair of PMOS trimming tubes is electrically connected with a power supply, the drain electrode is electrically connected with the source electrode of a second PMOS trimming tube in the pair of PMOS trimming tubes, and the grid electrode is electrically connected with the grid electrode of a first PMOS biasing tube in the first pair of PMOS biasing tubes;

The drain electrode of the second PMOS trimming tube in each pair of PMOS trimming tubes is electrically connected with the drain electrode of the first NMOS trimming tube;

The grid electrodes of the two NMOS trimming tubes are electrically connected with each other;

The grid electrode of the first NMOS trimming tube is electrically connected with the drain electrode of the first NMOS trimming tube, and the drain electrode of the second NMOS trimming tube is a current pull-in end;

the grid electrode of the second PMOS trimming tube of at least one pair of PMOS trimming tubes is electrically connected with the grid electrode of the second PMOS biasing tube of the first pair of PMOS biasing tubes, and the grid electrode of the second PMOS trimming tube of the other pair of PMOS trimming tubes floats.