CN117997355A - Decoding method, device, medium and SSD device of LDPC decoder - Google Patents

Decoding method, device, medium and SSD device of LDPC decoder Download PDF

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CN117997355A
CN117997355A CN202410024235.8A CN202410024235A CN117997355A CN 117997355 A CN117997355 A CN 117997355A CN 202410024235 A CN202410024235 A CN 202410024235A CN 117997355 A CN117997355 A CN 117997355A
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calculation
column
row
layer
check matrix
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黄孝勇
刘晓健
薛红军
杨骥
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Beijing Dera Technology Co Ltd
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Beijing Dera Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)

Abstract

The invention relates to the technical field of data storage, and provides a decoding method, a decoding device, a medium and SSD equipment of an LDPC decoder, wherein the method comprises the following steps: the method comprises the steps of performing calculation sequencing on non-zero blocks of each row of a parity check matrix to obtain a first calculation column and a second calculation column of each row, wherein the first calculation column of each row comprises all overlapped non-zero blocks of a current row and a next row adjacent to the current row; when the hierarchical decoding algorithm is adopted to perform inter-layer column cyclic computation, sequentially performing iterative computation on a first computation column and a second computation column of a current computation layer, wherein the computation layer of the inter-layer column cyclic computation corresponds to a row of the parity check matrix; after the calculation of the first calculation column of the current calculation layer is finished, the inter-layer inter-column loop calculation of the next layer is started. The invention greatly accelerates the decoding speed of the LDPC decoder and meets the requirements of low delay and high bandwidth of storage equipment.

Description

Decoding method, device, medium and SSD device of LDPC decoder
Technical Field
The present invention relates to the technical field of LDPC decoders, and in particular, to a decoding method, apparatus, medium, and SSD device of an LDPC decoder.
Background
Low density parity check codes (LDPC) have been widely used in communication systems after 2000 because of their good overall performance in several key indicators of error correction capability, decoding throughput rate, and algorithm complexity, and are also the mainstream error correction codes of current solid State Storage (SSD) controllers.
The LDPC decoder decodes based on the check matrix. For each parity check matrix H, there is a corresponding Tanner bipartite graph (bipartitle TANNER GRAPH). The Tanner graph includes two kinds of nodes, namely a Variable Node (VN) and a Check Node (CN). As shown in fig. 1, each VN represents a column in H, and each CN represents a row of H; when an element of a certain row and a certain column in H is 1, the corresponding VN and CN in the Tanner graph are connected by a line.
In order to put the decoding algorithm originally proposed by the inventor r.gallager of the LDPC into practical use and to maintain the error correction capability as much as possible, the evolution of the decoding algorithm of the LDPC has been generally subjected to a sum product (belief propagation) algorithm, to a log BP (log BP) in the logarithmic domain, to a minimum sum (min-sum) algorithm and various variations thereof. In the process, complex multiplication operation in check node operation is firstly simplified into simpler logarithm and addition operation, so that LDPC (low density parity check) has the possibility of being realized on a chip for the first time while error correction capability is not lost; the logarithmic and additive operations are then replaced by a simpler minimum, next-smallest ordering algorithm that, while losing a little error correction performance, also makes the algorithm insensitive to the estimation of the channel parameters. Therefore, most LDPC decoders currently use various algorithms derived from min-sum. The layered decoding algorithm mentioned herein is also a min-sum derived algorithm.
The application of LDPC decoders in SSDs also faces many challenges, including limited SSD controller chip size, large computational resources occupied by decoders, limited decoding bandwidth under limited computational resources, and so on.
The LDPC of the current mainstream SSD adopts a layered decoding algorithm, and compared with the common decoding algorithm, the layered decoding algorithm can not only accelerate convergence of the decoding process, but also reduce expansion of a plurality of variables in operation, so that the number of calculation units is reduced. The hierarchical decoding algorithm has a characteristic that the operation of the next layer depends on the confidence value transmitted by the operation of the previous layer, so if the same positions of the upper layer and the lower layer have non-zero blocks, the non-zero block calculation of the next layer must be started after the non-zero block calculation of the same position of the previous layer is completed. In a general matrix structure, the number and the positions of non-zero blocks of each row of the matrix have randomness, so that interlayer parallel processing is difficult to achieve when a layering algorithm is realized, and a complete iteration operation is finished after all row calculation is completed, so that the number of clock cycles required by a single iteration operation is the number of the non-zero blocks of the whole matrix plus the number of redundancy cycles, which results in overlong decoding time and cannot meet the requirements of low delay and high bandwidth of storage equipment.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present invention provides a decoding method, apparatus, medium and SSD device of an LDPC decoder.
In one aspect of the present invention, there is provided a decoding method of an LDPC decoder, the method comprising:
the method comprises the steps of performing calculation sequencing on non-zero blocks of each row of a parity check matrix to obtain a first calculation column and a second calculation column of each row, wherein the first calculation column of each row comprises all overlapped non-zero blocks of a current row and a next row adjacent to the current row;
When the hierarchical decoding algorithm is adopted to perform inter-layer column cyclic computation, sequentially performing iterative computation on a first computation column and a second computation column of a current computation layer, wherein the computation layer of the inter-layer column cyclic computation corresponds to a row of the parity check matrix;
after the calculation of the first calculation column of the current calculation layer is finished, the inter-layer inter-column loop calculation of the next layer is started.
Further, before computationally ordering the non-zero blocks of each row of the parity check matrix, the method further comprises: constructing a parity check matrix;
the constructing the parity check matrix includes:
resetting each row in the parity check matrix to a preset fixed value;
The number of overlapping non-zero blocks of adjacent rows is less than or equal to one-half the row weight.
Further, the calculation method for performing inter-layer inter-column loop calculation by adopting a layered decoding algorithm comprises the following steps:
where i is the row number of the parity check matrix, j is the column number of the parity check matrix, t is the current iteration number, And information which is transmitted to the jth variable node by the ith check node when representing the jth iteration. /(I)And information which is transmitted to the ith check node by the jth variable node when representing the jth iteration. /(I)Representing the reliability of the j variable node at the t iteration, wherein alpha is a normalization parameter,/>Is to fetch/>Min is the minimum value of the collection element;
The method further comprises the steps of:
To the first calculation column of the current layer And/>, of the second calculation columnStored in SRAM of different bank.
In another aspect of the present invention, there is also provided a decoding apparatus of an LDPC decoder, the apparatus including:
The acquisition module is used for carrying out calculation sequencing on the non-zero blocks of each row of the parity check matrix to acquire a first calculation column and a second calculation column of each row, wherein the first calculation column of each row comprises the overlapped non-zero blocks of the current row and the next row adjacent to the current row;
The first calculation module is used for sequentially carrying out iterative calculation on a first calculation column and a second calculation column of a current calculation layer when a layered decoding algorithm is adopted for carrying out inter-layer column loop calculation, wherein the calculation layer of the inter-layer column loop calculation corresponds to a row of the parity check matrix;
And the second calculation module is used for starting inter-layer cyclic calculation of the next layer after the calculation of the first calculation column of the current calculation layer is finished.
Further, the apparatus further comprises:
the check matrix construction module is used for constructing a parity check matrix;
The check matrix construction module is specifically configured to reset each row of the parity check matrix to a preset fixed value; the number of overlapping non-zero blocks of adjacent rows is less than or equal to one-half the row weight.
Further, the calculation method for performing inter-layer inter-column loop calculation by adopting a layered decoding algorithm comprises the following steps:
where i is the row number of the parity check matrix, j is the column number of the parity check matrix, t is the current iteration number, And information which is transmitted to the jth variable node by the ith check node when representing the jth iteration. /(I)And information which is transmitted to the ith check node by the jth variable node when representing the jth iteration. /(I)Representing the reliability of the j variable node at the t iteration, wherein alpha is a normalization parameter,/>Is to fetch/>Min is the minimum value of the collection element;
the apparatus further comprises:
a memory module for storing the first calculation column of the current layer And/>, of the second calculation columnStored in SRAM of different bank.
Another aspect of the invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method.
In yet another aspect, the present invention provides an SSD device including a storage controller including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the program.
According to the decoding method, the decoding device, the medium and the SSD device of the LDPC decoder, the first calculation column and the second calculation column of each row are obtained through calculating and sequencing the non-zero blocks of each row of the parity check matrix, wherein the first calculation column of each row comprises the current row and all overlapped non-zero blocks of the next row adjacent to the current row; when the hierarchical decoding algorithm is adopted to perform inter-layer loop computation, iterative computation is performed on a first computation column of a current computation layer, and after the computation of the first computation column of the current computation layer is finished, inter-layer loop computation of a next layer is started, so that the inter-layer loop computation of the next layer does not need to wait for all non-zero blocks of the previous layer to be completely iterated, the decoding speed of the LDPC decoder is greatly accelerated, and the requirements of low delay and high bandwidth of storage equipment are met.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a diagram of a mapping relationship between a parity check matrix and a Tanner bipartite graph in the background art;
FIG. 2 is a flow chart illustrating a decoding method of an LDPC decoder according to an embodiment of the present invention;
FIG. 3 is an exemplary diagram of a parity check matrix according to an embodiment of the present invention;
FIG. 4 is a timing diagram of iterative operations of hierarchical decoding according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a decoding apparatus of an LDPC decoder according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Before describing the decoding method of the LDPC decoder according to the embodiment of the present invention, an iterative calculation principle of a hierarchical decoding algorithm is described. Let the number of rows of the parity check matrix be M and the number of columns be N.And information which is transmitted to the jth variable node by the ith check node when representing the jth iteration. /(I)And information which is transmitted to the ith check node by the jth variable node when representing the jth iteration. /(I)And the reliability of the jth variable node is represented in the t-th iteration. LLR j represents log-likelihood ratio soft information input by the decoder, and i and j also correspond to the row number and column number of the parity check matrix.
Initializing:
Starting iterative calculation, wherein T is the current iteration number, and T max represents the maximum iteration number:
For 0 is less than or equal to T < T max begin: iteration of the loop
For 0 is less than or equal to i < M begin: interlayer circulation
For 0.ltoreq.j < N begin: inter-layer inter-column circulation
Where alpha is the normalization parameter,Is to fetch/>Min is the minimum value of the element of the collection.
end
end
end
When the hardware implements the formula (1), the operation between the minimum value, the next minimum value, the product of all Q sign bits of the current row and the sign of the current Q is used for conveniencePart of the symbol bits of the current column Q of the current row can be obtained by removing the symbol bit products of all Q symbol bits of the current row; j is exactly where the minimum Q value of the current row is located,Or the next smallest Q value in the current row, j is not the position of the smallest Q value in the current row,/>The smallest Q value for the current row.
Further, for convenience of the following description, the present application will be referred to asIs Rnew,/>Is Rold,/>Qeld,/>Qnew. /(I)Called Qsign,/>And/>The relevant information is collectively referred to as FS (FS values do not vary with column number, only one set per row). The iterative calculation formula of the hierarchical decoding algorithm can be simplified as follows:
Rnew＝f(FS,Qsign) (4)
P＝Qold+Rnew (5)
Qnew＝P–Rold (6)
As can be seen from the above formula, the value of Qnew of each non-zero block of the next calculation layer adjacent to the current calculation layer depends on the P value of the corresponding column of the current calculation layer, so that the inter-layer column cyclic calculation of the next layer can be entered only by calculating the P value of the overlapping non-zero block of the current calculation layer.
Fig. 2 schematically shows a flowchart of a decoding method of an LDPC decoder according to an embodiment of the present invention. Referring to fig. 2, the decoding method of the LDPC decoder according to the embodiment of the present invention specifically includes the following steps:
s1, carrying out calculation sequencing on non-zero blocks of each row of a parity check matrix to obtain a first calculation column and a second calculation column of each row, wherein the first calculation column of each row comprises all overlapped non-zero blocks of a current row and a next row adjacent to the current row;
It should be noted that, the overlapping non-zero block is a non-zero block on the same column for both the current row and the next row adjacent to the current row. I.e. each column in the first calculated column of each row of the parity check matrix all contains columns in the next row adjacent thereto which overlap the non-zero block of the current row. The second calculation columns of two adjacent rows do not contain columns overlapping non-zero blocks.
In the parity check matrix shown in fig. 3, the 3 rd, 7 th, 14 th and 16 th columns of the first row contain overlapping non-zero blocks of the first row and the second row, and at this time, the first calculation column of the first row at least contains the 3 rd, 7 th, 14 th and 16 th columns. Accordingly, the first compute column of the second row is limited only by the non-zero blocks of the third row, independent of the first row.
S2, when a layered decoding algorithm is adopted to perform inter-layer column loop calculation, sequentially performing iterative calculation on a first calculation column and a second calculation column of a current calculation layer, wherein the calculation layer of the inter-layer column loop calculation corresponds to a row of a parity check matrix;
According to the decoding method of the LDPC decoder, when the inter-layer cycle calculation is performed, the calculation is not sequentially performed according to the column numbers, but the first calculation column of the current layer is calculated preferentially, and after all the calculation of the first calculation column is completed, the second calculation column of the current layer is calculated sequentially. The sequence of the first calculation sequence and the second calculation sequence of the current layer can be sequentially ordered according to the sequence numbers, or can be ordered in other modes, and the invention is not limited.
S3, after the calculation of the first calculation column of the current calculation layer is finished, starting inter-layer column circulation calculation of the next layer.
Because the first calculation column of the current calculation layer contains all overlapped non-zero blocks of the next layer adjacent to the first calculation column, when all calculation of the first calculation column of the current layer is finished, inter-layer loop calculation of the next layer can be started, and the next layer calculation is not needed to be started until the inter-layer loop calculation of the current layer is finished, so that the calculation time of iterative calculation can be greatly reduced.
Further, since the number (row weight) and the position of non-zero blocks in each row of the existing parity check matrix are not fixed, interlayer parallel processing is difficult to achieve when the layered decoding algorithm is implemented. Thus, in order to ensure that overlapping non-zero blocks of each adjacent two rows remain in a relatively stable range, in an embodiment of the present invention, before computationally ordering the non-zero blocks of each row of the parity check matrix, the method further comprises: and constructing a parity check matrix.
Further, the method for constructing the parity check matrix according to the embodiment of the invention comprises the following steps: resetting each row in the parity check matrix to a preset fixed value; the number of overlapping non-zero blocks of adjacent rows is less than or equal to one-half the row weight. Accordingly, the number of non-zero blocks of the first calculation column of each row of the parity check matrix is one half of the row weight of the parity check matrix. The row weight of the parity check matrix is the number of non-zero blocks of each row, and the value of the preset fixed value is determined according to the actual requirement and the column number of the parity check matrix, so that the invention is not limited.
Fig. 3 shows a specific embodiment of the parity-check matrix according to the present invention, where the parity-check matrix is a matrix of 6×16, i.e. the number of rows is 6, the number of columns is 16, the number of rows of each row is reset to 8, i.e. the number of non-zero blocks of the first calculation column is 4, the number of non-zero blocks of the second calculation column is also 4, and the number of overlapping non-zero blocks of two adjacent rows is less than or equal to 4 when constructing the parity-check matrix.
For ease of description, in fig. 3, the non-zero blocks of the first calculation column are filled with spaced vertical lines, the non-zero blocks of the second calculation column are filled with spaced diagonal lines, the overlapping non-zero blocks of the first row and the second row are the 3 rd, 7 th, 14 th, 16 th columns, and therefore the 3 rd, 7 th, 14 th, 16 th columns are taken as the first calculation columns of the first row (corresponding to the 2 nd, 4 th, 7 th, 8 th non-zero blocks), and the 1 st, 4 th, 10 th, 11 th columns of the first row are taken as the second calculation columns of the first row (corresponding to the 1 st, 3 rd, 5 th, 6 th non-zero blocks). Correspondingly, the first calculation column of the second row at least comprises columns 2, 5 and 8 (corresponding to the 9 th, 11 th and 13 th non-zero blocks).
The operation sequence for decoding calculation is shown in fig. 4 corresponding to the parity check matrix shown in fig. 3, wherein xxxx_wr represents a write enable signal and xxxx_rd represents a read enable signal. FS refers to a serial arrangement of tasks, the previous task having to be completed before the next new task can be started.
As shown in fig. 4, when the 8 th non-zero block calculation in the first layer is completed, inter-layer loop calculation of the second layer is started. The first calculation column of the second layer comprises the 9 th, 11 th and 13 th non-zero blocks, and when the 13 th non-zero block calculation of the second layer is finished, inter-layer loop calculation of the third layer is started. Thus, two layers can be guaranteed to carry out parallel iterative computation at each moment, so that the decoding speed is greatly increased,
Further, as shown in fig. 4, there are two write and one read accesses at the same time Qsign, when implemented in hardware, the SRAM is used to store Qsign, and the existing SRAM has only two independent address inputs at the same time, so that there is a conflict between 3 read and write address accesses. In the preferred embodiment of the application, as only half of each row of overlapped part is needed, the overlapped part and the non-overlapped part can be stored in SRAM of different banks, and the SRAM of 2 banks can provide 4 independent address inputs to meet the time sequence design requirement, so that each row of Bank0 part can be operated simultaneously with the uplink Bank1 without causing Qsign access conflict, thereby reducing the cycle number needed by each iteration to half of the total matrix non-zero block number plus the redundancy cycle number.
Therefore, the decoding method of the LDPC decoder according to the embodiment of the present invention further includes, when performing inter-layer column cyclic computation by using the hierarchical decoding algorithm, performing Qsign (i.e.) And/>, of the second calculation columnStored in SRAM of different bank. Therefore, the conflict of Qsign accesses can be avoided, and the implementation of the decoding method of the LDPC decoder in the embodiment of the invention is further ensured.
It should be noted that, the more pipelines are inserted in the iterative operation, the more redundancy periods are, and for more clarity of description, the timing in the embodiment of the invention is described according to the minimum pipeline insertion.
The embodiment of the invention combines a special parity check matrix construction mode and adopts a special time sequence arrangement mode, so that the number of periods required by one iteration of LDPC layered decoding is reduced to half of the total non-zero block number of the matrix plus the additional number of periods, and the number of periods required by one iteration of common LDPC layered decoding is the total non-zero block number of the matrix plus the additional number of periods, thus being capable of being understood as reducing the decoding time of the embodiment of the invention by nearly half.
For the purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated by one of ordinary skill in the art that the methodologies are not limited by the order of acts, as some acts may, in accordance with the methodologies, take place in other order or concurrently. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Fig. 5 schematically illustrates a structural diagram of a decoding apparatus of an LDPC decoder according to an embodiment of the present invention. Referring to fig. 5, a decoding apparatus of an LDPC decoder according to an embodiment of the present invention specifically includes an acquisition module 201, a first calculation module 202, and a second calculation module 203, where:
An obtaining module 201, configured to perform computation ordering on non-zero blocks of each row of the parity check matrix, and obtain a first computation column and a second computation column of each row, where the first computation column of each row includes an overlapping non-zero block of a current row and a next row adjacent to the current row;
A first calculation module 202, configured to sequentially perform iterative calculation on a first calculation column and a second calculation column of a current calculation layer when performing inter-layer column loop calculation by using a hierarchical decoding algorithm, where the calculation layer of inter-layer column loop calculation corresponds to a row of the parity check matrix;
The second calculation module 203 is configured to start inter-layer column loop calculation of the next layer after the calculation of the first calculation column of the current calculation layer is completed.
Further, the decoding device of the LDPC decoder provided by the embodiment of the invention further comprises: the check matrix construction module is used for constructing a parity check matrix;
The check matrix construction module is specifically configured to reset each row of the parity check matrix to a preset fixed value; the number of overlapping non-zero blocks of adjacent rows is less than or equal to one-half the row weight.
Further, the decoding device of the LDPC decoder according to the embodiment of the present invention further comprises:
a memory module for storing the first calculation column of the current layer And/>, of the second calculation columnStored in SRAM of different bank.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
Furthermore, embodiments of the present invention provide a computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, implements the steps of the method as described above.
In this embodiment, the modules/units integrated in the SSD device may be stored on a computer readable storage medium if implemented as software functional units and sold or used as a stand alone product. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
In addition, an embodiment of the present invention further provides an SSD device, where the device includes a storage controller, where the storage controller includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the steps of the method as described above when the processor executes the program. For example, steps S1 to S3 shown in fig. 2. Or the processor, when executing the computer program, implements the functions of each module/unit in the decoding apparatus embodiment of the LDPC decoder, for example, the acquisition module 201, the first calculation module 202, and the second calculation module 203 shown in fig. 5.
According to the decoding method, the decoding device, the medium and the SSD device of the LDPC decoder, the first calculation column and the second calculation column of each row are obtained through calculating and sequencing the non-zero blocks of each row of the parity check matrix, wherein the first calculation column of each row comprises the current row and the overlapped non-zero blocks of the next row adjacent to the current row; when the hierarchical decoding algorithm is adopted to perform inter-layer loop computation, iterative computation is performed on a first computation column of a current computation layer, and after the computation of the first computation column of the current computation layer is finished, inter-layer loop computation of a next layer is started, so that the inter-layer loop computation of the next layer does not need to wait for all non-zero blocks of the previous layer to be completely iterated, the decoding speed of the LDPC decoder is greatly accelerated, and the requirements of low delay and high bandwidth in the solid state disk are met.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments can be used in any combination.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A decoding method of an LDPC decoder, the method comprising:
the method comprises the steps of performing calculation sequencing on non-zero blocks of each row of a parity check matrix to obtain a first calculation column and a second calculation column of each row, wherein the first calculation column of each row comprises all overlapped non-zero blocks of a current row and a next row adjacent to the current row;
When the hierarchical decoding algorithm is adopted to perform inter-layer column cyclic computation, sequentially performing iterative computation on a first computation column and a second computation column of a current computation layer, wherein the computation layer of the inter-layer column cyclic computation corresponds to a row of the parity check matrix;
after the calculation of the first calculation column of the current calculation layer is finished, the inter-layer inter-column loop calculation of the next layer is started.
2. The method of claim 1, wherein prior to computationally ordering the non-zero blocks of the respective rows of the parity check matrix, the method further comprises: constructing a parity check matrix;
the constructing the parity check matrix includes:
resetting each row in the parity check matrix to a preset fixed value;
The number of overlapping non-zero blocks of adjacent rows is less than or equal to one-half the row weight.
3. The method of claim 2, wherein the number of non-zero blocks of the first computation column is one-half of a row weight of a parity check matrix.
4. The method of claim 1, wherein the calculation method for inter-layer column loop calculation using a hierarchical decoding algorithm comprises:
where i is the row number of the parity check matrix, j is the column number of the parity check matrix, t is the current iteration number, Information transmitted from the ith check node to the jth variable node in the t iteration is expressed by the information,/>Information which is transmitted to the ith check node by the jth variable node when representing the t iteration,/>Representing the reliability of the j variable node at the t iteration, wherein alpha is a normalization parameter,/>Is to fetch/>Min is the minimum value of the collection element;
The method further comprises the steps of:
To the first calculation column of the current layer And/>, of the second calculation columnStored in SRAM of different bank.
5. A decoding apparatus of an LDPC decoder, the apparatus comprising:
The acquisition module is used for carrying out calculation sequencing on the non-zero blocks of each row of the parity check matrix to acquire a first calculation column and a second calculation column of each row, wherein the first calculation column of each row comprises the overlapped non-zero blocks of the current row and the next row adjacent to the current row;
The first calculation module is used for sequentially carrying out iterative calculation on a first calculation column and a second calculation column of a current calculation layer when a layered decoding algorithm is adopted for carrying out inter-layer column loop calculation, wherein the calculation layer of the inter-layer column loop calculation corresponds to a row of the parity check matrix;
And the second calculation module is used for starting inter-layer cyclic calculation of the next layer after the calculation of the first calculation column of the current calculation layer is finished.
6. The apparatus of claim 5, wherein the apparatus further comprises:
the check matrix construction module is used for constructing a parity check matrix;
The check matrix construction module is specifically configured to reset each row of the parity check matrix to a preset fixed value; the number of overlapping non-zero blocks of adjacent rows is less than or equal to one-half the row weight.
7. The apparatus of claim 5, wherein the calculation method for performing inter-layer column loop calculation using a hierarchical decoding algorithm comprises:
where i is the row number of the parity check matrix, j is the column number of the parity check matrix, t is the current iteration number, Information transmitted from the ith check node to the jth variable node in the t iteration is expressed by the information,/>Information which is transmitted to the ith check node by the jth variable node when representing the t iteration,/>Representing the reliability of the j variable node at the t iteration, wherein alpha is a normalization parameter,/>Is to fetch/>Min is the minimum value of the collection element;
the apparatus further comprises:
a memory module for storing the first calculation column of the current layer And/>, of the second calculation columnStored in SRAM of different bank.
8. A computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method according to any one of claims 1-4.
9. An SSD device comprising a storage controller, said storage controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, said processor implementing the steps of the method according to any of claims 1-4 when said program is executed.
CN202410024235.8A 2024-01-07 2024-01-07 Decoding method, device, medium and SSD device of LDPC decoder Pending CN117997355A (en)

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