CN117995913A - Ultra-wide band-gap semiconductor diode with variable-depth JTE structure - Google Patents
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Abstract
The invention discloses an ultra-wide band-gap semiconductor diode with a variable-depth JTE structure, which comprises a substrate layer, an epitaxial layer, a dielectric layer, a cathode metal layer, a JTE region and an anode metal layer, wherein the epitaxial layer and the substrate layer are made of a first ultra-wide band-gap semiconductor material; the JTE region is a second ultra-wide band-gap semiconductor, the junction depth in the middle is unchanged, the junction depths at two sides are gradually reduced cambered surfaces until reaching the surface of the epitaxial layer, and a variable-depth JTE structure is formed. According to the invention, by utilizing the difference of etching rates of two etching materials, an inclined slope or cambered surface with a controllable angle is formed on a mask, then the shape of a groove is transferred onto an epitaxial layer through dry etching, and then a second ultra-wide semiconductor material is deposited to form a junction region, so that a variable-depth JTE structure is formed. The smooth curved surface and the cambered surfaces on two sides at the bottom surface of the structure can effectively relieve or even eliminate the electric field concentration phenomenon of the device, and the JTE structure with the variable depth increases design margin compared with the normal JTE structure, so that the requirements of complete exhaustion in withstand voltage are more easily met.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an ultra-wide band-gap semiconductor diode with a variable-depth JTE structure and a preparation method thereof.
Background
Today, energy and environmental issues are becoming more and more of a concern, society has a higher demand for efficiency of power electronics systems, and performance of power semiconductor devices. Silicon-based power devices have found widespread use in many fields to date. However, as silicon power devices develop near maturity and the material characteristics of the silicon material itself limit, their device performance has failed to meet the increasing demands of high power applications. Therefore, materials with wide forbidden bands (such as silicon carbide, gallium nitride and the like) are paid more attention to and invested in due to the advantages of high thermal conductivity, high critical field strength, high saturation drift rate and the like. At present, the wide band gap material power device is put into application in the fields of photovoltaics, chargers, new energy automobiles and the like, and occupies a considerable part of markets. With the growing use of wide band gap semiconductor materials and the urgent need for higher power devices, gallium oxide (Ga 2O3), diamond, etc. are regarded as ultra-wide band gap semiconductor materials as new focuses.
In the aspect of material characteristics, gallium oxide and diamond are used as ultra-wide band gap semiconductor materials, have similar ultra-wide forbidden bands and critical breakdown electric fields which are 10 times that of silicon, and the saturation drift speed of the ultra-wide forbidden bands and the critical breakdown electric fields is far above that of the silicon materials. The two materials with ultra-wide forbidden bands have better performance in the aspects of radiation resistance and thermal stability, and the high saturation drift speed can enable the device to work in the field of higher power. Thanks to these superior characteristics, ga 2O3 devices have shown great application potential in many fields such as power electronics, uv photodetectors, solar cells, etc., while diamond devices have broad application prospects in fields such as microwave communication, radar systems, aerospace, power systems, biological detection, quantum computation, etc., but both are currently at a distance from large-scale marketable applications.
As an ultra-wide band gap semiconductor, the difficulty in realizing the device is how to form an effective doping concentration. The crystalline phase beta-Ga 2O3 has good thermal stability, so that the crystalline phase beta-Ga 2O3 can realize good N-type doping in a mode of heat treatment after ion implantation like other materials, but stable and controllable high-quality P-type doping is difficult to realize in beta-Ga 2O3. While for diamond, P-type doping can be achieved by boron, the desire to achieve good N-type doping remains a challenge to the industry. Meanwhile, the critical breakdown electric field of the two materials is very high, so that the electric field in the dielectric layer above the device is raised to an unacceptable value during breakdown according to the gaussian theorem. Limited to these two points, devices based on these two materials have difficulty in fully exploiting the superior properties of the two materials themselves.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art and provides an ultra-wide band-gap semiconductor diode with a variable depth Junction Termination Extension (JTE) structure and a preparation method thereof, so as to improve the voltage withstand capability of the ultra-wide band-gap semiconductor device, improve the heat dissipation performance of the device and protect the reliability of a dielectric layer.
In order to solve the technical problems, the embodiment of the invention provides an ultra wide band gap semiconductor diode with a variable depth JTE structure, wherein the cell structure comprises a cathode metal layer 5, a substrate layer 4 and an epitaxial layer 3 which are sequentially stacked from bottom to top, the top layer of the epitaxial layer 3 is provided with a JTE region 2, part of the JTE region 2 and part of the epitaxial layer 3 are provided with an anode metal layer 1, the other part of the JTE region 2 and the other part of the epitaxial layer 3 are provided with a dielectric layer 6, and the side surfaces of the dielectric layer 6 and the anode metal layer 1 are in contact with each other;
the anode metal layer 1 and the epitaxial layer 3 form schottky contact, and the cathode metal layer 5 and the substrate layer 4 form ohmic contact;
The substrate layer 4 and the epitaxial layer 3 are both made of a first ultra-wide band-gap semiconductor material; the concentration of the substrate layer 4 is higher than that of the epitaxial layer 3; the JTE region 2 is made of a second ultra-wide band-gap semiconductor material, and the first ultra-wide band-gap semiconductor material is different from the second ultra-wide band-gap semiconductor material; the junction depth in the middle of the JTE region 2 is unchanged, the junction depths at the two sides are gradually reduced cambered surfaces until reaching the surface of the epitaxial layer 3, and a variable-depth JTE structure is formed; the length of the cambered surface of the side, close to the anode metal layer, of the JTE region 2 in the direction parallel to the surface of the epitaxial layer 3 is smaller than that of the variable-depth JTE structure of the cambered surface of the side, far away from the anode metal layer; the JTE region 2 is formed by a deposition process to form a heterojunction with the epitaxial layer 3 to improve electric field distribution. On the basis of the technical scheme, the invention can be improved as follows.
Further, the first ultra-wide band gap semiconductor material is one of N-type gallium oxide and P-type diamond; the second ultra-wide band gap semiconductor material is one of N-type gallium oxide and P-type diamond and is different from the first ultra-wide band gap semiconductor material.
Further, the doping element of the N-type gallium oxide comprises one or more of Si and Sn;
And/or the doping element of the JTE region 2 is B.
Further, the anode metal layer 1 comprises one or more of Ni, au, pt, al and has a thickness of 100-500 nm;
And/or the material of the cathode metal layer 5 comprises one or more of Ti, au and Cr, and the thickness is 80-300 nm.
Further, the material of the dielectric layer 6 includes one or more of Si 3N4、Al2O3、HfO2、ZrO2, and the thickness is 150-300 nm.
Further, the bottom surface of the JTE region 2 and the cambered surface form a smooth transition at the boundary.
The beneficial effects of adopting the further scheme are as follows: the structure can effectively eliminate the power line aggregation effect caused by geometric characteristics.
Furthermore, according to design requirements, the two sides of the JTE region 2 can be in an inclined surface shape through adjusting the process.
Furthermore, in the JTE region 2, a region with unchanged junction depth may not be reserved according to needs, so as to save the terminal area.
Further, the JTE region 2 is formed by a multiple deposition process.
The beneficial effects of adopting the further scheme are as follows: the concentration profile is controlled to achieve a better electric field profile.
In order to solve the technical problems, the embodiment of the invention provides a preparation method of an ultra-wide band-gap semiconductor diode with a variable-depth JTE structure, which comprises the following steps:
S1, epitaxially forming an epitaxial layer 3 on a substrate layer 4;
S2, preparing a mask layer on the surface of the epitaxial layer 3, and forming a groove shape with an arc surface on the mask layer through photoetching and etching technology;
s3, transferring the appearance of the cambered surface groove on the mask layer to the epitaxial layer 3 through dry etching;
S4, filling a second ultra-wide band gap semiconductor material on the surface of the epitaxial layer 3 and in the groove, and then flattening the surface to form a JTE region 2;
s5, preparing a dielectric layer 6 on the surfaces of the epitaxial layer 3 and the JTE region 2, and etching to form a Schottky contact window;
S6, preparing an anode metal layer 1 on the surface of the device, wherein the anode metal layer 1 is positioned on the epitaxial layer 3 and partially overlapped with the JTE region 2;
and S7, preparing a cathode metal layer 5 at the bottom of the substrate layer 4.
Further, step S2 further includes the following steps:
S21, depositing a low etching rate material 7 on the surface of the epitaxial layer 3, spin-coating photoresist on the surface of the low etching rate material 7, exposing and developing to expose an etching window;
s22, etching steps on the low etching rate material 7 by adopting a dry etching process;
s23, depositing a first high-etching-rate material 8 on the surface of the low-etching-rate material 7, and exposing an etching window on the surface of the first high-etching-rate material 8 through a photoetching technology;
s24, performing wet etching on the device to form an arc surface on the low-etching-rate material 7, and then removing the photoresist.
Further, the thickness of the low etch rate material 7 should be greater than the thickness of the first high etch rate material 8, the thickness of the first high etch rate material 8 is not greater than 0.5 μm, and the thickness of the low etch rate material 7 is not less than 1.0 μm.
The beneficial effects of adopting the further scheme are as follows: the upper layer material is rapidly etched through wet etching, so that a wet reagent can extend to a covered position below the photoresist mask, and a longer cambered surface groove with controllable angles is formed below the mask by etching the low etching material.
Further, step S24 further includes: the first high etch rate material 8 is removed.
Further, step S2 further includes the following steps:
S21, depositing a low etching rate material 7 on the surface of the epitaxial layer 3, spin-coating photoresist on the surface of the low etching rate material 7, exposing and developing to expose an ion implantation window;
S22, carrying out ion implantation on the surface of the material 7 with the low etching rate, and annealing to form a modified layer 71 with the high etching rate;
s23, etching the modified layer 71 through a wet etching process, removing photoresist, and forming a step on the low etching rate material 7;
S24, depositing a first high etching rate material 8 on the surface of the low etching rate material 7, and exposing an etching window on the surface of the first high etching rate material 8 through a photoetching technology;
s25, performing wet etching on the device to form an arc surface on the low-etching-rate material 7, and removing the photoresist and the first high-etching-rate material 8.
Further, step S2 further includes the following steps:
s21, depositing a low etching rate material 7 on the surface of the epitaxial layer 3;
s22, depositing a second high etching rate material 81 on the surface of the device, and then etching away the second high etching rate material 81 of a part of the area to form a step on the low etching rate material 7;
S23, depositing a first high etching rate material 8 on the surface of the low etching rate material 7, and exposing an etching window on the surface of the first high etching rate material 8 through a photoetching technology;
and S24, performing wet etching on the device to form an arc surface on the low-etching-rate material 7, and removing the photoresist, the first high-etching-rate material 8 and the second high-etching-rate material 81.
Further, the method for forming the multi-region variable depth JTE structure is also applied to MOSFETs, IGBTs or GTOs.
Further, the material of the low etching rate material 7 includes one or more of SiO 2、Si3N4、Al2O3, and the thickness is determined by the selection ratio of the material to the first ultra-wide band-gap semiconductor material in the dry etching and the thickness of the designed JTE region 2.
The beneficial effects of the invention are as follows:
1. At present, the technology of epitaxially growing N-type gallium oxide and P-type diamond by various methods is mature, and the formed material has the characteristics of easy impurity control, high growth rate, good uniformity and the like. Furthermore, the critical breakdown fields of the two materials are similar, which ensures that the device does not breakdown prematurely near the heterojunction. In conclusion, the P-type diamond-N-type gallium oxide heterojunction formed by deposition can effectively improve electric field distribution, protect a dielectric layer and improve the voltage-withstanding capability of a device.
2. The variable-depth JTE structure formed at the edge of the device can effectively relieve or even eliminate the problem of electric field concentration at the edge under the condition of occupying a smaller area, and further improve the breakdown voltage of the ultra-wide band-gap semiconductor device. The introduced process window of the variable-depth JTE structure can increase design margin more than that of a conventional JTE structure, and the requirement of complete exhaustion in the pressure resistance process is met more easily. Meanwhile, the smooth transition at the bottom surface of the JTE region and the cambered surfaces at the two sides can effectively relieve the phenomenon of electric field concentration, and the voltage endurance capability of the device is further improved. The structure not only can protect the reliability of the dielectric layer above the device, but also can effectively protect the Schottky contact.
3. Compared with the method for carrying out wet etching on the dielectric layer only, the method for realizing etching mask by utilizing two layers of materials with different wet etching rates can form a longer JTE structure and can better improve the characteristics of devices. The planarization treatment for the surface of the second ultra-wide band gap semiconductor material after deposition can effectively reduce adverse factors that the surface can influence the voltage endurance capacity of the terminal structure due to interface states, surface charges and the like introduced by various processes. Meanwhile, the groove of the variable-depth JTE structure is generated by one-time etching, has good consistency and surface roughness, and is easy to improve the interface characteristic by other process treatment. Meanwhile, the method provided by the invention can be used for preparing junction terminals of gallium oxide or diamond diodes, and is also suitable for various power devices based on diamond or gallium oxide materials, such as MOS, IGBT, GTO and the like.
Drawings
Fig. 1 is a schematic structural diagram of an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a first and second embodiment of the present invention;
fig. 2 is a schematic process flow diagram of a method for manufacturing an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a third and fourth embodiment of the present invention;
fig. 3 is a schematic process flow diagram of step 2 in a method for fabricating an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a third and fourth embodiment of the present invention;
Fig. 4-14 are schematic process flow structure diagrams of a method for manufacturing an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a third and fourth embodiment of the present invention;
Fig. 15 is a schematic structural diagram of an ultra wide band gap semiconductor device with a variable depth JTE junction terminal fabricated by a fabrication method of an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a third and fourth embodiment of the present invention;
fig. 16 is a schematic process flow diagram of step 2 in a method for fabricating an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a fifth embodiment of the present invention;
fig. 17 is a schematic structural diagram of a process flow of step 2 in a method for fabricating an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a fifth embodiment of the present invention;
Fig. 18 is a schematic process flow diagram of step 2 in a method for fabricating an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a sixth embodiment of the present invention;
Fig. 19 to 20 are schematic process flow structure diagrams of step 2 in a method for fabricating an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a sixth embodiment of the present invention;
fig. 21 is a schematic structural diagram of an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a seventh embodiment of the present invention.
In the drawings, the list of components represented by the various numbers is as follows:
1. Anode metal layer 2, JTE region 3, epitaxial layer 4, substrate layer 5, cathode metal layer 6, dielectric layer 7, low etching rate material 8, first high etching rate material 71, modified layer 81, second high etching rate material.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
Example 1
As shown in fig. 1, in the ultra wide band gap semiconductor diode with a variable depth JTE structure provided in the first embodiment of the present invention, the cell structure includes a cathode metal layer 5, a substrate layer 4 and an epitaxial layer 3 which are sequentially stacked from bottom to top, the top layer of the epitaxial layer 3 has a JTE region 2, a part of the JTE region 2 and a part of the epitaxial layer 3 are provided with an anode metal layer 1, another part of the JTE region 2 and another part of the epitaxial layer 3 are provided with a dielectric layer 6, and the sides of the dielectric layer 6 and the anode metal layer 1 are in contact with each other;
the anode metal layer 1 and the epitaxial layer 3 form schottky contact, and the cathode metal layer 5 and the substrate layer 4 form ohmic contact;
The substrate layer 4 and the epitaxial layer 3 are both made of a first ultra-wide band-gap semiconductor material; the concentration of the substrate layer 4 is higher than that of the epitaxial layer 3; the JTE region 2 is made of a second ultra-wide band-gap semiconductor material, and the first ultra-wide band-gap semiconductor material is different from the second ultra-wide band-gap semiconductor material; the junction depth in the middle of the JTE region 2 is unchanged, the junction depths at the two sides are gradually reduced cambered surfaces until reaching the surface of the epitaxial layer 3, and a variable-depth JTE structure is formed; the length of the cambered surface of the side, close to the anode metal layer, of the JTE region 2 in the direction parallel to the surface of the epitaxial layer 3 is smaller than that of the variable-depth JTE structure of the cambered surface of the side, far away from the anode metal layer; the JTE region 2 is formed by a deposition process to form a heterojunction with the epitaxial layer 3 to improve electric field distribution.
In the above embodiment, the first ultra wide band gap semiconductor material is N-type gallium oxide, and the second ultra wide band gap semiconductor material is P-type diamond.
Specifically, the doping element of the substrate layer 4 is Si, the effective doping carrier concentration is 10 18-1020cm-3, and the thickness is 50-100 μm;
Specifically, the doping element of the epitaxial layer 3 is Si, the effective doping carrier concentration is 10 15-1018cm-3, and the thickness is 5-30 μm;
Specifically, the doping elements of the JTE region 2 include B, and the effective doping carrier concentration is 10 15-1019cm-3;
Specifically, the cathode metal layer comprises laminated Ti and Au, wherein the thickness of Ti is 20-80nm, and the thickness of Au is 50-400nm;
Specifically, the anode metal layer comprises laminated Ni and Au, wherein the thickness of Ni is 40-80nm, and the thickness of Au is 100nm;
specifically, the dielectric layer material comprises Al 2O3 with the thickness of 150-300 nm.
Specifically, the bottom surface of the JTE region 2 and the cambered surface form a smooth transition at the boundary, so that the power line aggregation effect caused by geometric features can be effectively eliminated
Example 2
As shown in fig. 1, an ultra-wideband semiconductor diode with a variable-depth JTE structure according to a second embodiment of the present invention is provided, in which a first ultra-wideband semiconductor material and a second ultra-wideband semiconductor material are interchanged on the basis of the first embodiment.
In the above embodiment, the diamond diode formed after material exchange benefits from good heat conduction capability of diamond, and is more suitable for fields with high requirements on heat dissipation performance, such as microwaves.
Example 3
As shown in fig. 2,4-5,9-14, the preparation method of the ultra-wide band gap semiconductor diode with the variable-depth JTE structure provided by the third embodiment of the invention comprises the following steps:
S1, epitaxially forming an epitaxial layer 3 on a substrate layer 4;
First, the substrate layer 4 is cleaned with acetone-isopropyl alcohol-deionized water in sequence using a standardized cleaning process. Then, gallium oxide is epitaxially formed on the upper surface of the substrate layer 4 by any one of a hydride vapor deposition technique (HVPE), a metal-organic chemical vapor deposition technique (MOCVD), and an atomized chemical vapor deposition technique (best-CVD), to form an epitaxial layer 3, as shown in fig. 4.
S2, preparing a mask layer on the surface of the epitaxial layer 3, and forming a groove shape with an arc surface on the mask layer through photoetching and etching technology;
S3, transferring the appearance of the cambered surface groove on the mask layer to the epitaxial layer 3 through dry etching, and removing the residual mask layer;
First, the epitaxial layer 3 is etched by using the low etching rate material 7 as a mask layer and adopting the ICP etching technology to form a JTE region trench. The remaining low etch rate material 7 on the surface of the epitaxial layer 3 is then removed by wet etching. In the ICP etching technology, the gas atmosphere is BCl 3/Cl2 gas, and the ratio thereof is adjusted to obtain a selection ratio close to 1, so that the trench morphology of the low etching rate material 7 is transferred to the trench on the surface of the epitaxial layer 3 by the ICP etching technology, as shown in fig. 10. The remaining low etch rate material 7 is then removed by wet etching techniques, as shown in fig. 11.
Specifically, the ICP etching conditions in this embodiment are: the power of the upper electrode is 350-410W, the power of the lower electrode is 80-120W, the pressure of the chamber is 5-15mTorr, and the flow of the gas BCl 3：CL2 is 30-50sccm:10-20sccm, and the temperature of the reaction chamber is room temperature.
S4, filling a second ultra-wide band gap semiconductor material on the surface of the epitaxial layer 3 and in the groove, and then flattening the surface to form a JTE region 2;
Firstly, a Microwave Plasma Chemical Vapor Deposition (MPCVD) method under a borane gas environment is adopted to deposit the P-type diamond in a JTE region to form a variable depth JTE structure, the main gases of reaction are methane CH 4, hydrogen H 2 and diborane B 2H7, and during Deposition, mixed gas is introduced into a reflection cavity to control the doping concentration of the P-type diamond by controlling the flow rate of the gas, as shown in figure 12.
Thereafter, the surface is planarized by using an oxygen plasma etching technique or the like to remove diamond outside the JTE region 2, thereby forming the JTE region 2, as shown in fig. 13.
S5, preparing a dielectric layer 6 on the surfaces of the epitaxial layer 3 and the JTE region 2, and etching to form a Schottky contact window;
S6, preparing an anode metal layer 1 on the surface of the device, wherein the anode metal layer 1 is positioned on the epitaxial layer 3 and partially overlapped with the JTE region;
Firstly, an insulating medium is deposited on the epitaxial layer 3 and the JTE region 2 by adopting a metal organic chemical vapor deposition technology, and the dielectric material can be one or more of Si 3N4、Al2O3、HfO2、ZrO2, and the thickness is 150-300 nm. Spin-coating photoresist on the surface after deposition, exposing an etching window after photoetching development, and forming a window of Schottky metal by dry etching.
And then forming a metal layer by adopting an electron beam evaporation or Sputer magnetron sputtering process, wherein the metal layer covers the anode groove to form an anode metal layer 1, and the anode metal layer 1 can be made of Ni/Au or Pt/Au. Wherein, the thickness of Ni or Pt is 10-50nm, and the thickness of Au or Al is 100-400nm.
And S7, preparing a cathode metal layer 5 at the bottom of the substrate layer 4.
Firstly, placing a cleaned sample into an electron beam evaporation table, and sequentially evaporating Ti/Au on the back surface of a substrate layer 5, wherein the thickness of metal Ti is 20-50nm, and the thickness of metal Au is 100-400nm; after the electrode metal is evaporated, the electrode metal is rapidly thermally annealed in an N 2 environment at 450-600 ℃ for 60s to form ohmic contact, and a cathode metal layer 5 is obtained, as shown in FIG. 14.
Specifically, the method for preparing the JTE junction terminal by transferring the trench morphology to the epitaxial layer and depositing the P-type diamond by dry etching after forming the angle-controllable inclined slope or cambered surface by utilizing the difference of etching rates of two wet etching materials in the invention is not limited to be applied to gallium oxide diodes, and can be also used for preparing junction terminal structures of other depletion-type and enhancement-type devices based on the two materials, such as MOSFET, JFET, IGBT, GTO and other power devices, and the specific implementation is shown in fig. 15.
Example 4
As shown in fig. 2,4-5,9-14, the method for manufacturing an ultra-wide band gap semiconductor diode with a variable depth JTE structure according to the fourth embodiment of the present invention is based on the third embodiment, in which the epitaxial layer and the substrate layer are replaced with P-type diamond, the JTE region is replaced with N-type gallium oxide, and the deposition method used in step S4 is replaced with MOCVD.
In the embodiment, the MOCVD method is used for depositing the N-type gallium oxide material, so that the obtained gallium oxide material has better quality and easier control of concentration.
Optionally, as shown in fig. 3 and 5-9, in the preparation method of the ultra-wide band gap semiconductor diode with the variable depth JTE structure provided in the third and fourth embodiments of the present invention, step S2 further includes the following steps:
S21, depositing a low etching rate material 7 on the surface of the epitaxial layer 3, spin-coating photoresist on the surface of the low etching rate material 7, exposing an etching window after exposure and development;
s22, etching steps on the low etching rate material 7 by adopting a dry etching process;
first, a low etch rate material 7 is deposited on the surface of the epitaxial layer 3 using an Inductively Coupled Plasma Chemical Vapor Deposition (ICPCVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, as shown in fig. 5. Thereafter, photoresist is spin coated on the surface of the low etch rate material 7, and after exposure and development, the etch window is exposed, and the low etch rate material 7 is etched to form a step by a dry etching method such as Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP), as shown in fig. 6.
Specifically, the material of the low etching rate material 7 is SiO 2, and the ICP etching conditions are: the power of the upper electrode is 280-320W, the power of the lower electrode is 80-120W, the pressure of the chamber is 5-12mTorr, the flow of the gas SF 4 is 30-50sccm, the temperature of the reaction chamber is room temperature, and the step height is 0.1-0.5 μm.
S23, depositing a high-etching-rate material 8 on the surface of the low-etching-rate material 7, and exposing an etching window on the surface of the first high-etching-rate material 8 through a photoetching technology;
The first high etch rate material 8 is deposited on the surface of the low etch rate material 7 and since the step is then removed by wet etching, there is no excessive requirement for the step coverage of the deposition process and a less costly deposition process can be selected. Thereafter, photoresist is spin coated on the surface of the first high etching rate material 8, and an etching window is exposed after exposure and development, as shown in fig. 7.
Specifically, a layer of material with a faster wet etching rate (e.g., ti or Si 3N4 etching rate exceeds SiO 2 for hydrofluoric acid etching, and Ti, si 3N4 and SiO 2 etching rates exceed polysilicon) is deposited on top of the common dielectric (e.g., siO 2) mask material. In addition, for the same type of material, the difference of deposition process parameters also causes the difference of wet etching rates;
S24, performing wet etching on the device to form an arc surface on the low etching rate material 7, and then removing the photoresist and the high etching rate material 8;
First, the material is etched by a wet etch (e.g., HF), and since the two layers of material have different etch rates, the reagents used during etching will extend under the mask along the high etch rate material 8 while etching the underlying low etch rate material 7 to form a camber or bevel. Meanwhile, because the thicknesses of the low etching rate materials at the two sides of the etching window are not consistent, the length of the cambered surface at the side close to the anode metal, which is parallel to the surface of the device, is smaller than the cambered surface at the side far away from the anode metal, so that the cambered surface shown in fig. 8 can be formed on the low etching rate material 7. The remaining photoresist and high etch rate material 8 is then removed by wet etching, as shown in fig. 9.
Example 5
As shown in fig. 16-17, a method for manufacturing an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a fifth embodiment of the present invention is based on the third and fourth embodiments of the present invention, and the step 2 further includes the following steps:
S21, depositing a low etching rate material 7 on the surface of the epitaxial layer 3, spin-coating photoresist on the surface of the low etching rate material 7, exposing and developing to expose an ion implantation window;
S22, carrying out ion implantation on the surface of the material 7 with the low etching rate, and annealing to form a modified layer 71 with the high etching rate;
Specifically, the element used in the ion implantation may be one of N-type or P-type doping elements such as B, as, and the structure after implantation annealing is shown in fig. 17.
S23, etching the modified layer 71 through a wet etching process, removing photoresist, and forming a step on the low etching rate material 7;
S24, depositing a first high etching rate material 8 on the surface of the low etching rate material 7, and exposing an etching window on the surface of the first high etching rate material 8 through a photoetching technology;
s25, performing wet etching on the device to form an arc surface on the low etching rate material 7, and then removing the photoresist and the first high etching rate material 8;
in the above embodiment, the method of forming the step on the low etching rate material 7 by changing the etching rate by ion implantation can control the step height and the etching rate by the energy and the dose of ion implantation, and the step uniformity after etching is better.
Example 6
As shown in fig. 18-20, a method for manufacturing an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a sixth embodiment of the present invention is based on the third and fourth embodiments of the present invention, and the step 2 further includes the following steps:
s21, depositing a low etching rate material 7 on the surface of the epitaxial layer 3;
s22, depositing a second high etching rate material 81 on the surface of the device, and then etching away the second high etching rate material 81 of a part of the area to form a step on the low etching rate material 7;
specifically, the etching of the second high etching rate material 81 is dry etching having a high selectivity to the underlying low etching rate material 7, thereby forming a step profile on the surface thereof, as shown in fig. 19.
S23, depositing a first high etching rate material 8 on the surface of the low etching rate material 7, and exposing an etching window on the surface of the first high etching rate material 8 through a photoetching technology;
specifically, steps are formed on the surface after deposition, the morphology is shown in figure 20,
S24, performing wet etching on the device to form an arc surface on the low-etching-rate material 7, and then removing the photoresist, the first high-etching-rate material 8 and the second high-etching-rate material 81;
In the above embodiment, the step height is controlled by the deposition process, and the controllability and the uniformity are better than the step height is controlled by changing the etching time.
Example 7
As shown in fig. 21, an ultra wide band gap semiconductor diode with a variable depth JTE structure according to a seventh embodiment of the present invention is formed by depositing multiple times to form layered JTE regions on the basis of the first embodiment.
In the above embodiment, the layered JTE region 2 is formed by multiple depositions, so that the concentration distribution of the JTE region 2 can be better controlled, and better electric field distribution and better interface characteristics can be obtained.
The invention discloses an ultra-wide band-gap semiconductor diode with a variable-depth JTE structure, which comprises a substrate layer, an epitaxial layer, a dielectric layer, a cathode metal layer, a JTE region and an anode metal layer, wherein the epitaxial layer and the substrate layer are made of a first ultra-wide band-gap semiconductor material; the JTE region is a second ultra-wide band-gap semiconductor, the junction depth in the middle is unchanged, the junction depths at two sides are gradually reduced cambered surfaces until reaching the surface of the epitaxial layer, and a variable-depth JTE structure is formed. According to the invention, by utilizing the difference of etching rates of two etching materials, an inclined slope or cambered surface with a controllable angle is formed on a mask, then the shape of a groove is transferred onto an epitaxial layer through dry etching, and then a second ultra-wide semiconductor material is deposited to form a junction region, so that a variable-depth JTE structure is formed. The smooth curved surface and the cambered surfaces on two sides at the bottom surface of the structure can effectively relieve or even eliminate the electric field concentration phenomenon of the device, and compared with a normal JTE structure, the JTE structure with variable depth can increase design margin, and can more easily meet the requirement of complete exhaustion in withstand voltage. The reliability of various dielectric layers present over the termination region is also protected while the schottky contact is protected.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The cell structure of the ultra-wide band-gap semiconductor diode with the variable-depth JTE structure comprises a cathode metal layer (5), a substrate layer (4) and an epitaxial layer (3) which are sequentially stacked from bottom to top, wherein a JTE region (2) is arranged in the top layer of the epitaxial layer (3), anode metal layers (1) are arranged on part of the JTE region (2) and part of the epitaxial layer (3), dielectric layers (6) are arranged on the other part of the JTE region (2) and the other part of the epitaxial layer (3), and the side surfaces of the dielectric layers (6) and the anode metal layers (1) are in contact with each other;
The anode metal layer (1) and the epitaxial layer (3) form Schottky contact, and the cathode metal layer (5) and the substrate layer (4) form ohmic contact;
the semiconductor device is characterized in that the substrate layer (4) and the epitaxial layer (3) are both made of a first ultra-wide band-gap semiconductor material; the concentration of the substrate layer (4) is higher than that of the epitaxial layer (3); the JTE region (2) is made of a second ultra-wide band-gap semiconductor material, and the first ultra-wide band-gap semiconductor material is different from the second ultra-wide band-gap semiconductor material; the junction depth of the middle of the JTE region (2) is unchanged, and the junction depths of the two sides are gradually reduced cambered surfaces until reaching the surface of the epitaxial layer (3) to form a variable-depth JTE structure; the length of the cambered surface of the side, close to the anode metal layer, of the JTE region (2) in the direction parallel to the surface of the epitaxial layer (3) is smaller than that of the variable-depth JTE structure of the cambered surface of the side, far away from the anode metal layer; the JTE region (2) is formed by a deposition process, and forms a heterojunction with the epitaxial layer (3) to improve electric field distribution.
2. The ultra-wide band gap semiconductor diode with variable depth JTE structure of claim 1, wherein the first ultra-wide band gap semiconductor material is one of gallium oxide N type and diamond P type; the second ultra-wide band gap semiconductor material is one of N-type gallium oxide and P-type diamond and is different from the first ultra-wide band gap semiconductor material.
3. An ultra wide band gap semiconductor diode with variable depth JTE structure according to claim 1, characterized in that the material of the anode metal layer (1) comprises one or more of Ni, au, pt, al a with a thickness of 100-500 nm;
And/or the material of the cathode metal layer (5) comprises one or more of Ti, au and Cr, and the thickness is 80-300 nm;
And/or the material of the dielectric layer (6) comprises one or more of Si 3N4、Al2O3、HfO2、ZrO2.
4. An ultra wide band gap semiconductor diode having a variable depth JTE structure according to any one of claims 1-3, wherein the bottom surface of the JTE region (2) is smoothly transitioned to the arc surface at the boundary.
5. An ultrawide bandgap semiconductor diode having a variable depth JTE structure according to any of claims 1-3, wherein said JTE region (2) is formed by multiple depositions.
6. The method for manufacturing an ultra wide band gap semiconductor diode with a variable depth JTE structure of any one of claims 1-5, comprising the steps of:
S1, epitaxially forming an epitaxial layer (3) on a substrate layer (4);
S2, preparing a mask layer on the surface of the epitaxial layer (3), and forming a groove shape with an arc surface on the mask layer through photoetching and etching technology;
S3, transferring the appearance of the cambered surface groove on the mask layer to the epitaxial layer (3) through dry etching;
s4, filling a second ultra-wide band gap semiconductor material on the surface of the epitaxial layer (3) and in the groove, and then flattening the surface to form a JTE region (2);
S5, preparing a dielectric layer (6) on the surfaces of the epitaxial layer (3) and the JTE region (2), and etching to form a Schottky contact window;
S6, preparing an anode metal layer (1) on the surface of the device, wherein the anode metal layer (1) is positioned on the epitaxial layer (3) and is partially overlapped with the JTE region (2);
s7, preparing a cathode metal layer (5) at the bottom of the substrate layer (4).
7. The method for manufacturing an ultra wide band gap semiconductor diode with variable depth JTE structure of claim 6, wherein step S2 further comprises the steps of:
s21, depositing a low etching rate material (7) on the surface of the epitaxial layer (3), spin-coating photoresist on the surface of the low etching rate material (7), exposing and developing, and exposing an etching window;
S22, etching steps on the low-etching-rate material (7) by adopting a dry etching process;
s23, depositing a first high-etching-rate material (8) on the surface of the low-etching-rate material (7), and exposing an etching window on the surface of the first high-etching-rate material (8) through a photoetching technology;
S24, performing wet etching on the device to form an arc surface on the low etching rate material (7), and then removing the photoresist and the first high etching rate material (8).
8. The method for manufacturing an ultra wide band gap semiconductor diode with variable depth JTE structure of claim 6, wherein step S2 further comprises the steps of:
s21, depositing a low etching rate material (7) on the surface of the epitaxial layer (3), spin-coating photoresist on the surface of the low etching rate material (7), exposing and developing, and exposing an ion implantation window;
s22, carrying out ion implantation on the surface of the material (7) with the low etching rate, and annealing to form a modified layer (71) with the high etching rate;
s23, etching the modified layer (71) through a wet etching process, removing photoresist, and forming a step on the low etching rate material (7);
S24, depositing a first high-etching-rate material (8) on the surface of the low-etching-rate material (7), and exposing an etching window on the surface of the first high-etching-rate material (8) through a photoetching technology;
S25, performing wet etching on the device to form an arc surface on the low etching rate material (7), and then removing the photoresist and the first high etching rate material (8).
9. The method for manufacturing an ultra wide band gap semiconductor diode with variable depth JTE structure of claim 6, wherein step S2 further comprises the steps of:
s21, depositing a low etching rate material (7) on the surface of the epitaxial layer (3);
S22, depositing a second high etching rate material (81) on the surface of the device, and then etching away the second high etching rate material (81) of a part of areas to form steps on the low etching rate material (7);
s23, depositing a first high-etching-rate material (8) on the surface of the low-etching-rate material (7), and exposing an etching window on the surface of the first high-etching-rate material (8) through a photoetching technology;
S24, performing wet etching on the device to form an arc surface on the low-etching-rate material (7), and then removing the photoresist, the first high-etching-rate material (8) and the second high-etching-rate material (81).
10. The method of any one of claims 6-9, wherein the method of forming a multi-region variable depth JTE structure is also applied to MOSFETs, IGBTs or GTOs.
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