CN117978324A - Processing method for realizing 4G &5G rate matching and interleaving through shared hardware - Google Patents

Abstract

The embodiment of the invention provides a processing method for realizing 4G &5G rate matching and interleaving through shared hardware, wherein the shared hardware comprises a storage sharing unit and an operation sharing unit; the storage sharing unit is a plurality of SRAM block memories; the method comprises the following steps: the memory sharing unit carries out block interleaving processing on turbo codes and convolution codes in 4G LTE and polar codes and LDPC codes in 5G NR; the operation sharing unit performs code rate matching on the turbo code and the convolutional code in 4G LTE, and the polar code and the LDPC code in 5G NR. The invention realizes the rate matching and interleaving of four codes involved in 4G LTE and 5G NR communication links by using hardware through schemes such as formulation or lookup tables, maximizes the sharing granularity of four coded hardware modules, and simultaneously provides a parallelization realization scheme for an interleaving part.

Description

Processing method for realizing 4G & 5G rate matching and interleaving through shared hardware

Technical Field

The application belongs to the technical field of 4G & 5G communication chip hardware, and particularly relates to a processing method for realizing 4G & 5G rate matching and interleaving through shared hardware.

Background

In daily life, especially with the coverage of 5G base stations, it is important to research the commonality of the current algorithm and the previous algorithm and realize sharing.

From different communication standards, channel interleaving is involved in multiple standards, WiMAX(World Interoperability for Microwave Access)、WLAN(Wireless Local Area Network)、802.11n、HSPA(High-Speed Packet Access)、DVB-H(Digital Video Broadcasting Handheld)、3GPP-LTE(Long Term Evolution) and 5G NR.

From a different coding scheme, for MNBTC (Multi-Non-Binary Turbo Codes) codes, i.e. new generation Non-binary turbo codes, the document "h.belta.et al.student on Intra-symbol Interleaving for Multi-Non-Binary Turbo Codes" proposes several possible methods of Intra-symbol interleaving and summarizes the relationship between Intra-symbol interleaving and bit error rate/signal-to-noise ratio.

From different types of interleaving, for block interleaving implementations, the traditional solution is to use two alternating RAM memories, one sequentially stored and the other RAM read using a different addressing scheme. During transmission, the codeword at the receiving end is lost or erroneous due to burst noise or interference, which results in decoding failure.

One way to solve this situation is to add an interleaving module between the encoder and the transmitting end and de-interleave at the decoding end, so that rate matching and interleaving are an indispensable part of baseband signal processing, and by researching and comparing the different points in the 4G and 5G standards, it is found that the interleaving algorithm under the two standards can realize hardware sharing and memory sharing to a certain extent, that is, multiple coding sharing hardware interleavers.

Disclosure of Invention

In view of the above, a main object of the present invention is to provide a processing method for implementing 4G & 5G rate matching and interleaving by over-shared hardware.

In order to achieve the above purpose, the technical scheme of the invention is realized as follows:

The embodiment of the invention provides a processing method for realizing 4G & 5G rate matching and interleaving through shared hardware, wherein the shared hardware comprises a storage sharing unit and an operation sharing unit;

The storage sharing unit is a plurality of SRAM block memories;

The method comprises the following steps:

The memory sharing unit carries out block interleaving processing on turbo codes and convolution codes in 4G LTE and polar codes and LDPC codes in 5G NR;

the operation sharing unit performs code rate matching on the turbo code and the convolutional code in 4G LTE, and the polar code and the LDPC code in 5G NR.

In the above solution, the memory sharing unit performs block interleaving processing on the turbo code in 4G LTE, and the operation sharing unit performs code rate matching on the turbo code in 4G LTE, and specifically includes:

In the sub-block interleaving part of the turbo code, three bit streams with equal lengths are input to three sub-block interleavers, the sub-block interleavers are row-column interleaving, and the minimum line number of the sub-block interleavers is determined through the lengths of the bit streams and the line numbers of the sub-block interleavers;

If the length of the bit stream is equal to the minimum product of the number of columns and the number of rows of the sub-block interleaver, the bit stream sequentially enters the sub-block interleaver;

if the bit stream length is smaller than the minimum product of the number of columns and the number of rows of the sub-block interleaver, filling null bits into the sub-block interleaver;

Performing inter-column permutation on the bit sequences written into the subblock interleaver in the bit collecting and cyclic buffer part of the turbo code, outputting a bit stream according to a turbo code address mapping formula after the inter-column permutation is completed, and finally putting the bit stream into a cyclic buffer area according to the order of the turbo code cyclic buffer area formula;

and in the bit selecting and punching part of the turbo code, setting related parameters to complete the bit selecting and punching process of the bits entering the circular buffer area according to uplink and downlink transmission channels.

In the above scheme, the turbo code address mapping formula is

In the above scheme, the turbo code cyclic buffer formula is

In the above solution, the block interleaving processing is performed on the convolutional code in 4G LTE by the storage sharing unit, and the code rate matching is performed on the convolutional code in 4G LTE by the operation sharing unit, which specifically includes:

In the sub-block interleaving part of the convolutional code, three paths of bit streams with equal length are input to three sub-block interleavers, the sub-block interleavers are row-column interleaving, and the minimum line number of the sub-block interleavers is determined through the length of the bit streams and the line number of the sub-block interleavers;

If the length of the bit stream is equal to the minimum product of the number of columns and the number of rows of the sub-block interleaver, the bit stream sequentially enters the sub-block interleaver;

if the bit stream length is smaller than the minimum product of the number of columns and the number of rows of the sub-block interleaver, filling null bits into the sub-block interleaver;

performing inter-column replacement on the bit sequences written into the subblock interleaver in the bit collection and cyclic buffer part of the convolutional code, and after the inter-column replacement is completed, putting the output bit stream into a cyclic buffer area according to the sequence of a convolutional code cyclic buffer area formula for bit collection;

And in the bit selection part of the convolutional code block, after the convolutional code completes bit collection, completing bit selection.

In the above scheme, the bit stream is according to the convolutional code cyclic buffer formula

In the above scheme, the block interleaving and rate matching algorithm for determining the polar code in the 5G NR specifically includes: at the sub-block interleaving part of the polar code, the bit stream output by encoding enters 32 sub-blocks to be subjected to sub-block interleaving respectively, so as to obtain an output sequence yk;

In the bit selection part of the polar code, carrying out bit selection on the output sequence yk to obtain a rate matching output sequence, setting the length of the rate matching output sequence of the polar code as 864, and carrying out bit selection according to the length of the bit stream before encoding and the length of the bit stream after encoding to obtain a bit selection output sequence ek;

And in the bit interleaving part of the polar code, keeping the length of a bit interleaving sequence fk of the polar code equal to that of the bit selecting output sequence ek, and selecting isosceles right triangle interleaving in a bit interleaving mode.

In the above scheme, the determining the block interleaving and rate matching algorithm of the LDPC code in the 5G NR specifically includes: a bit selection part in the LDPC code block interleaving and rate matching algorithm, wherein each code block independently codes and outputs a bit sequence with the length of N, and the bit sequence with the length of E is processed and output according to the LDPC code bit selection algorithm;

And in the bit interleaving part of the LDPC, bit interleaving is completed in a block interleaving mode according to an LDPC code bit interleaving algorithm, the output sequence length is E, and the number of lines is the modulation order Qm.

Compared with the prior art, the invention realizes the rate matching and interleaving of four codes involved in 4G LTE and 5G NR communication links by using hardware through schemes such as formulation or lookup tables, maximizes the sharing granularity of four coded hardware modules, and simultaneously provides a parallelization realization scheme for an interleaving part.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:

FIG. 1 is a block diagram of a shared hardware in a processing method for implementing 4G & 5G rate matching and interleaving by the shared hardware according to an embodiment of the present invention;

FIG. 2 is a flow chart of a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention;

FIG. 3 is a flow chart of mode selection for providing a method for processing pole code bit selection in 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention;

FIG. 4 is a circuit diagram for generating specific addresses of turbo code interleaving address calculation formulas in a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention;

FIG. 5 is a circuit diagram for generating specific addresses of a convolutional code interleaving address calculation formula in a processing method for realizing 4G & 5G rate matching and interleaving through shared hardware according to an embodiment of the present invention;

FIG. 6 is a block diagram of a polar sub-block interleaving address calculation in a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention;

FIG. 7 is a flowchart of a preprocessing stage of a generic data flow diagram of an interleaving algorithm providing four different encodings, according to an embodiment of the present invention;

FIG. 8 is a flow chart of the execution phases of a generic dataflow graph that provides an interleaving algorithm for four different encodings, according to an embodiment of the invention;

FIG. 9 is a diagram of simulation results of waveforms of four different codes of a shared memory module according to an embodiment of the present invention;

FIG. 10 is a diagram of simulation results of an interleaved waveform of a standard shared multiplexing design scheme for four different codes according to an embodiment of the present invention;

FIG. 11 is a diagram showing an output bit stream distribution diagram of turbo code block interleaving without null bit stuffing in a turbo code rate matching and interleaving method in a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention;

FIG. 12 is a block interleaving distribution diagram of turbo code stuffing bits in a turbo code rate matching and interleaving method in a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware, according to an embodiment of the present invention;

FIG. 13 is a diagram showing a bit stream distribution diagram of a convolutional code block interleaved output without null bit stuffing in a convolutional code rate matching and interleaving method in a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention;

Fig. 14 is a block interleaving distribution diagram of convolutional codes in a convolutional code rate matching and interleaving method in a processing method for implementing 4G & 5G rate matching and interleaving by shared hardware according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The embodiment of the invention provides a processing method for realizing 4G & 5G rate matching and interleaving through shared hardware, which is applied to the shared hardware shown in figure 1, wherein the shared hardware comprises a storage sharing unit and an operation sharing unit; the storage sharing unit is a plurality of SRAM block memories;

As shown in fig. 2, the method includes:

step 101: the memory sharing unit carries out block interleaving processing on turbo codes and convolution codes in 4G LTE and polar codes and LDPC codes in 5G NR;

step 102: the operation sharing unit performs code rate matching on the turbo code and the convolutional code in 4G LTE, and the polar code and the LDPC code in 5G NR.

The memory sharing unit performs block interleaving processing on the turbo code in the 4G LTE, and the operation sharing unit performs code rate matching on the turbo code in the 4G LTE, and specifically includes:

In the sub-block interleaving part of the turbo code, three bit streams with equal lengths are input to three sub-block interleavers, the sub-block interleavers are row-column interleaving, and the minimum line number of the sub-block interleavers is determined through the lengths of the bit streams and the line numbers of the sub-block interleavers;

If the length of the bit stream is equal to the minimum product of the number of columns and the number of rows of the sub-block interleaver, the bit stream sequentially enters the sub-block interleaver;

if the bit stream length is smaller than the minimum product of the number of columns and the number of rows of the sub-block interleaver, filling null bits into the sub-block interleaver;

Performing inter-column permutation on the bit sequences written into the subblock interleaver in the bit collecting and cyclic buffer part of the turbo code, outputting a bit stream according to a turbo code address mapping formula after the inter-column permutation is completed, and finally putting the bit stream into a cyclic buffer area according to the order of the turbo code cyclic buffer area formula;

and in the bit selecting and punching part of the turbo code, setting related parameters to complete the bit selecting and punching process of the bits entering the circular buffer area according to uplink and downlink transmission channels.

The turbo code address mapping formula is

The turbo code cyclic buffer formula is

Illustratively, in the turbo code rate matching method and the interleaving method, it is assumed that the turbo encoded bit streams have equal lengths and are set to D, the block interleaver is a row-column interleaving, the turbo encoded column number is set to R, the value of R is 32, and the minimum line number of the turbo code block interleaver is determined to be C according to the parameters D and R, so that the turbo code block interleaver satisfies the formula:

D≤R×C (1)

when the equal sign of the formula (1) is established, three paths of bit streams generated by encoding directly enter three sub-block interleavers from left to right and from top to bottom in sequence;

If the equal sign of the formula (1) is not satisfied, filling ND null bits is needed in the block interleaver, and the interleaving is performed after filling, and the ND value is determined according to the formula (2):

ND＝R×C-D (2)

The code block interleaved output bit stream of the turbo code without null bit stuffing is shown in fig. 12;

The bits after padding are then 0,1,2 in order..nd-1, in the block interleaver null bits are padded first, then the coded bit stream is padded, i.e. yk= < null >, k=0, 1, 2..nd-1, ynd+k=dk (i), k=0, 1,2, …, D-1, i=0, 1,2;

The code block interleaving output bit stream of the turbo code after null bit stuffing is shown in fig. 13;

after filling, writing a bit sequence yk into an R×C matrix according to columns, and expanding and replacing the bit stream written into the matrix according to columns, wherein P (j) is the original column position of a j-th replaced column;

The permutation sequence among the interleaving columns of the turbo code blocks is shown in table 1:

TABLE 1 turbo code block interleaving inter-column permutation pattern table

For the turbo code encoded bit stream dk (2), null bit stuffing and inter-column permutation are also required, and after column permutation, the bit stream vk (2) is output according to the address mapping formula (3), the formula (3) is as follows:

After all three block interleaving coded by the turbo code are output, the address mapping bit stream vk (i), i=0, 1,2; the following circular buffer formula (4) is put in the following order:

Setting relevant parameters to complete the bit selection process according to the corresponding uplink and downlink transmission channels after the address mapping bit stream enters the circulating buffer area;

The bit selection algorithm implements a pseudo code as shown by the turbo code bit selection algorithm.

The storage sharing unit performs block interleaving processing on the convolutional codes in the 4G LTE, and the operation sharing unit performs code rate matching on the convolutional codes in the 4G LTE, and specifically includes:

In the sub-block interleaving part of the convolutional code, three paths of bit streams with equal length are input to three sub-block interleavers, the sub-block interleavers are row-column interleaving, and the minimum line number of the sub-block interleavers is determined through the length of the bit streams and the line number of the sub-block interleavers;

If the length of the bit stream is equal to the minimum product of the number of columns and the number of rows of the sub-block interleaver, the bit stream sequentially enters the sub-block interleaver;

if the bit stream length is smaller than the minimum product of the number of columns and the number of rows of the sub-block interleaver, filling null bits into the sub-block interleaver;

performing inter-column replacement on the bit sequences written into the subblock interleaver in the bit collection and cyclic buffer part of the convolutional code, and after the inter-column replacement is completed, putting the output bit stream into a cyclic buffer area according to the sequence of a convolutional code cyclic buffer area formula for bit collection;

And in the bit selection part of the convolutional code block, after the convolutional code completes bit collection, completing bit selection.

The bit stream is expressed as according to a convolution code cyclic buffer zone formula

Illustratively, in the convolutional code rate matching and interleaving method, for convolutional codes dk (0), dk (1), and dk (2), assuming that there are D input information bits per bit stream, the three paths have the same output length;

Vk (0), vk (1) and vk (2) output by the convolutional code block interleaver are obtained through the following processes;

Setting the value of the number of columns C and C of the convolutional code block interleaver to be 32, namely the columns of the block interleaver matrix are sequentially 0,1,2, … and C-1 from left to right;

Setting the row number of the matrix of the convolutional code block interleaver as R, wherein the size of R is also determined by the formula (1), and the rows of the matrix are 0,1,2, … and R-1 from top to bottom in sequence;

the code block interleaved output bit stream of the convolutional code without null bit padding is shown in fig. 14;

In the convolutional coding, if the equal sign of the formula (1) is established, each path of bit stream sequentially enters a convolutional code block interleaver from left to right according to the sequence from top to bottom;

in the convolutional coding, if the equal sign of the formula (1) is not established, adding ND null bits, and determining ND value according to the formula (2);

then writing bits y0 from column 0, row 0 in row order, where yk= < null >, k=0, 1,2, …, ND-1, ynd+k=dk (i), k=0, 1,2, …, D-1, i=0, 1,2;

The code block interleaving output bit stream of the convolutional code after null bit filling is shown in fig. 14;

After the convolutional code coded bits enter the convolutional code block interleaver matrix of the RxC, interleaving among columns is performed according to a convolutional code block interleaving column permutation mode given in the following table 2;

TABLE 2 substitution pattern table between interleaving columns of convolutional code blocks

In table 2, P (j) is the original column position of the j-th permutation column;

after interleaving the permutation among columns of the convolutional code block, reading out a convolutional code bit sequence from the exchanged R×C matrix according to the sequence of columns;

The read convolution code bit streams vk (0), vk (1) and vk (2) enter a circulating buffer zone with the length of 3 XR x C according to the sequence shown in a formula (5) for bit collection;

when the convolutional code bit sequence is output from the circular buffer, convolutional code bit selection is performed, and the bit selection process is as shown in the following algorithm 2.

In algorithm 2, the convolutional code circular buffer length K _W is shown in equation (6);

K_W＝3×R×C (6)

The block interleaving and rate matching algorithm for determining the polar code in the 5G NR specifically comprises the following steps: at the sub-block interleaving part of the polar code, the bit stream output by encoding enters 32 sub-blocks to be subjected to sub-block interleaving respectively, so as to obtain an output sequence yk;

In the bit selection part of the polar code, carrying out bit selection on the output sequence yk to obtain a rate matching output sequence, setting the length of the rate matching output sequence of the polar code as 864, and carrying out bit selection according to the length of the bit stream before encoding and the length of the bit stream after encoding to obtain a bit selection output sequence ek;

And in the bit interleaving part of the polar code, keeping the length of a bit interleaving sequence fk of the polar code equal to that of the bit selecting output sequence ek, and selecting isosceles right triangle interleaving in a bit interleaving mode.

Illustratively, in the pole code rate matching and interleaving method in the method, the bits input to the sub-block interleaver are pole code bit sequence dk, the total length of the code output bit stream is N (n=2n), and N bits respectively enter 32 sub-blocks for sub-block interleaving;

the interleaving process in the polar code rate matching and interleaving method performs address mapping according to the following algorithm 3;

The output bit stream of the polar sub-block interleaving is represented by yk, and the polar sub-block interleaving sequence substitution is shown in table 3;

TABLE 3 polar codon-block interleaving substitution pattern P (i)

In Table 3 above, P (i) is the substitution sequence of the polar codon interleaving;

A bit selection part in a polar code rate matching and interleaving method in the method performs a bit selection process on the polar code sub-block interleaving output sequence yk, and one of the three modes of repetition, selection and perforation is required to be determined;

The three mode selection processes of the pole code bit selection are shown in fig. 3;

In fig. 3, K is the bit stream length before the polar code is encoded, N is the bit stream length after the polar code is encoded, and E is the polar code rate matching output sequence length;

In a polar code downlink transmission channel in the method, setting a polar code rate matching output sequence length E to be 864;

then, selecting one mode of repeating, punching and shortening to finish bit selection according to the K value and the N value of the other two parameters;

The three bit selection mode address calculation formulas of the polar code are shown in the following algorithm 4;

A bit interleaving part in a polar code rate matching and interleaving method in the method, wherein the polar code bit selection output sequence is ek, and the bit length of ek is E (the polar code rate matching output sequence length);

In the polar code bit interleaving part, the output sequence is fk through polar code bit interleaving, the bit length E is unchanged, and the bit interleaving mode is isosceles right triangle interleaving.

The block interleaving and rate matching algorithm for determining the LDPC code in the 5G NR specifically comprises the following steps: a bit selection part in the LDPC code block interleaving and rate matching algorithm, wherein each code block independently codes and outputs a bit sequence with the length of N, and the bit sequence with the length of E is processed and output according to the LDPC code bit selection algorithm;

And in the bit interleaving part of the LDPC, bit interleaving is completed in a block interleaving mode according to an LDPC code bit interleaving algorithm, the output sequence length is E, and the number of lines is the modulation order Qm.

Illustratively, in the bit selecting part of the LDPC code rate matching and interleaving method in the method, the LDPC code rate matching is performed independently for each code block, and the bit stream (with the length of N) output by the LDPC code is subjected to bit selection to output a bit sequence with the length of E;

the LDPC code bit selection process is shown in algorithm 5;

A bit interleaving part in the LDPC code rate matching and interleaving method in the method completes LDPC code bit interleaving in a block interleaving form after LDPC code bit selection;

As shown in algorithm 6, the sequence length output through bit interleaving of the LDPC code is still E;

in the block interleaving of the bit interleaving generalization of the LDPC code, the number of lines is the modulation order Qm.

In the scheme of memory sharing and operation sharing, the memory sharing uses a certain amount of SRAM block memories to respectively realize the block interleaving of the turbo codes, the block interleaving of the convolution codes, the block interleaving of the polar codes and the bit interleaving of the LDPC codes;

Operation sharing means that mod operation is implemented by using the same hardware for the rate matching process of the turbo code, the convolutional code, and the polar code;

In the memory sharing design, the memory divides the data memory into 8 identical sub-memory systems according to the maximum data stream setting, and each sub-memory has a size of 99×32 bits, so that 32-bit parallel access can be realized at maximum.

In the memory sharing design, for the turbo coding, performing cyclic shift processing on the coded bit stream, sequentially putting the coded bit stream into each sub-memory module according to rows, namely storing 32 bits of data in each row, performing inter-row permutation according to a data row permutation rule and an address generation formula, and generating addresses through an address calculation unit according to formulas (7), (8) and (9), so as to complete corresponding address mapping;

In the operation sharing of the address calculation unit, when the bit stream enters a block interleaver for the code rate matching of the turbo coding, the index is i, after the block interleaving, three paths of bit streams are output and enter a bit collecting area, and in the three paths of total bit streams, the bit index is j;

According to the specific implementation flowchart of turbo code rate matching shown in fig. 3, the corresponding relationship between the input index and the output index of each bit can be obtained;

for the turbo code interleaver sub-block 0, the input index and output index correspondence relation (7) of each bit thereof is as follows:

for the turbo code interleaver sub-block 1, the input index and output index correspondence relation (8) of each bit thereof is as follows:

For the turbo code interleaver sub-block 2, the input index and output index correspondence relation (9) of each bit thereof is as follows:

In the above-mentioned relational expressions (7), (8) and (9), ND represents the number of filled null bits, and & represents the bit AND operation, RTC is the number of lines per sub-block, Representing a downward rounding, wherein the value of P </SUB > is determined according to the turbo inter-column permutation pattern table of Table 1;

When the turbo code block interleaving is realized, the mapping formulas of each sub-block interleaving address are respectively (7), (8) and (9), and the specific address generating circuit of the turbo code interleaving is shown in fig. 4 according to the correlation operation in the formulas;

in a specific address circuit diagram generated by the turbo code interleaving address calculation formula, namely fig. 4, the m value is

And ND of the m value is the null bit number of the turbo code interleaving stuffing.

In the memory sharing design, for the convolutional codes, the convolutional codes are put into sub memory blocks according to the sequence of each sub block in the standard, the convolutional code column displacement table is preloaded into the corresponding module, the inter-column displacement is carried out according to the sequence, and the address operation is carried out according to the optimized address calculation formula;

In the operation sharing of the address calculation unit, assuming that the initial bit sequence of each sub-block is i for code rate matching of the convolutional code, obtaining i mod 32=x through a pre-calculation process, obtaining P (n) =x according to table 2, and obtaining n values;

the mapping formula of the interleaving address of the convolution sub-block is shown as follows;

a first sub-block interleaver for the convolutional code:

a second sub-block interleaver for the convolutional code:

A third sub-block interleaver for the convolutional code:

in the above-described convolutional subblock interleaving address mapping formulas (10) (11) (12), j is a position index of a single bit in the total bit stream entering the circular buffer, ND is the number of bits filled in a single subblock, R is the number of lines per subblock, Representing a downward rounding operation;

The specific address generation circuit for the convolutional code interleaving can be obtained according to the correlation operation in the formulas (10) (11) (12) as shown in fig. 5;

In a specific address circuit diagram generated by the convolutional code interleaving address calculation formula, namely fig. 5, the m value is

And ND of the m value is the null bit number filled by the convolutional code interleaving.

In the memory sharing design, for the polar coding, the first step of rate matching is sub-block interleaving, dividing the coded bit sequence into 32 parts, and reading out the bit sequence according to an address mapping formula;

In the shared memory design of the polar code, each part is put into a sub-memory module according to columns, and 32 sub-blocks correspond to 32 columns of the sub-memory modules;

in the rate matching of the polar code, according to the polar code sub-block interleaving algorithm, the data reading process is equivalent to reading one bit at the same position of each part, so that in the implementation process, the data is output according to rows;

in the operation sharing of the address calculation unit, a specific address circuit diagram generated by a polar coding interleaving address calculation formula can be obtained according to the polar coding sub-block interleaving algorithm in the rate matching of the polar coding for the polar coding, and is shown in fig. 6.

In the memory sharing design, for the LDPC coding, the last step of LDPC code rate matching is to perform interleaving realization listed, and the bits output after bit selection are written into 8 sub-memory modules according to rows;

Due to the parallel mode of storage in the memory sharing design, 8 modules can be written in at the same time and read out in parallel;

in the operation sharing of the address calculation unit, for the code rate matching of the LDPC codes, the whole process comprises bit selection and bit interleaving;

The bit selection of the LDPC code is implemented by mod operation, and the bit interleaving of the LDPC code involves only running lists, and no specific hardware implementation circuit is given here.

In fig. 1, for the LUT module, by initializing different contents, it can be used to implement turbo code, convolutional code, and polar lookup table parameter determination;

For LDPC encoding, a mod arithmetic unit may be entered through a selector module, and the result is calculated through mod arithmetic.

To further verify the effectiveness of the algorithm in the present invention, four different coding interleaving algorithms are first explored, and interleaving implementation procedures for the four codes are listed through a general data flow diagram.

The data flow implementation is divided into a preprocessing stage and an execution stage, as shown in fig. 8 and 9 respectively;

the pre-calculation stage is used for calculating relevant parameters of the block interleaver and loading a corresponding substitution table;

The execution stage is to generate corresponding addresses according to an address mapping formula and read out the corresponding addresses after writing data.

The hardware design of the invention firstly carries out algorithm simulation on matlab, and for turbo coding and convolution coding, each bit is replaced by an address index, namely, each sub-block is assumed to input 32 bits, each bit is sequentially 0,1 and 2, and the last bit is 31;

In order to achieve the definition of the simulation result, in this section of experiment, the bit index result of the circular buffer area is given when the input bit stream length of each sub-block is 32, and in this case, the number of lines of each sub-block is 1, and 32 columns are sequentially output according to the column output, i.e. according to the inter-column replacement mode;

And writing corresponding RTL codes based on the Q_order prime, describing a hardware circuit by using Verilog, debugging, and completing waveform simulation and function verification through Modelsim. And under the SMIC 28nm technology and the operation frequency of 50MHz, the area cost and the corresponding power consumption of the hardware are finally obtained through Synopsys synthesis.

After the hardware designed by the invention is realized by using the Verilog language, debugging is performed based on quartus prime platforms, and waveform simulation is performed on modelsim. By setting corresponding control signals and enabling signals, different bits are input at the input end of the data memory, and the output of different codes is observed, so that a simulation result diagram is shown in fig. 10;

FIG. 10 is a simulation of a memory module, wherein data_in is the data input and data_out is the output signal. In the test file tb, different bit streams are input to a data input end, high and low level changes are carried out on a read enable signal and a write enable signal at the same time, when the write enable signal is high level and is a clock rising edge, writing operation is carried out on data of data_in, when the read enable signal is high level and is a clock rising edge, the written data is output through a data_out end, and bit output is carried out correctly;

Fig. 11 is a waveform simulation result of an interleaving part of the standard shared multiplexing design scheme proposed by the present invention, for interleaving of four coding interleaving parts, different bit streams are input to data input end data in test file tb, enabling signals control whether the bit streams can be read and written, control signals can generate different addresses and perform different interleaving methods, and under the action of the two, output signals of data_out data output end are observed. As can be seen from the waveform diagram, at the rising edge position of the clock, the processed bit stream correctly outputs the interleaved bit stream at the data_out end;

And through synopsys design synthesis, generating a layout, and viewing layout related parameters in table 4.

TABLE 4 layout parameters

Finally, according to the algorithm and the hardware circuit provided by the invention, simulation verification on hardware is carried out through modelsim, and the result shows that the address calculation formula can realize that bits after block interleaving are correctly output in a circular buffer area according to a standard sequence. As shown in fig. 10, in the case of increasing the parallelism in the interleaver, data of a specific length is input, and then the output terminal waveform is observed, and it is found that the corresponding sequence can be correctly output at the rising edge of the clock arrival. The design of the invention completely merges two communication standards, which is not related in the previous block interleaving algorithm, and experimental results show that the total area and the power consumption of the design are relatively small, and the design can be switched back and forth in two coding interleaving, so that the switching flexibility between systems is improved.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention.

Claims (8)

1. A processing method for realizing 4G &5G rate matching and interleaving by shared hardware is characterized in that the shared hardware comprises a storage sharing unit and an operation sharing unit,

The memory sharing unit is a plurality of SRAM block memories,

The method comprises the following steps:

The memory sharing unit carries out block interleaving processing on turbo codes and convolution codes in 4G LTE and polar codes and LDPC codes in 5G NR;

the operation sharing unit performs code rate matching on the turbo code and the convolutional code in 4G LTE, and the polar code and the LDPC code in 5G NR.

2. The processing method for implementing 4G &5G rate matching and interleaving by shared hardware according to claim 1, wherein the memory sharing unit performs block interleaving processing on turbo codes in 4G LTE, and the operation sharing unit performs code rate matching on the turbo codes in 4G LTE, specifically comprising:

In the sub-block interleaving part of the turbo code, three bit streams with equal lengths are input to three sub-block interleavers, the sub-block interleavers are row-column interleaving, and the minimum line number of the sub-block interleavers is determined through the lengths of the bit streams and the line numbers of the sub-block interleavers;

If the length of the bit stream is equal to the minimum product of the number of columns and the number of rows of the sub-block interleaver, the bit stream sequentially enters the sub-block interleaver;

if the bit stream length is smaller than the minimum product of the number of columns and the number of rows of the sub-block interleaver, filling null bits into the sub-block interleaver;

Performing inter-column permutation on the bit sequences written into the subblock interleaver in the bit collecting and cyclic buffer part of the turbo code, outputting a bit stream according to a turbo code address mapping formula after the inter-column permutation is completed, and finally putting the bit stream into a cyclic buffer area according to the order of the turbo code cyclic buffer area formula;

and in the bit selecting and punching part of the turbo code, setting related parameters to complete the bit selecting and punching process of the bits entering the circular buffer area according to uplink and downlink transmission channels.

3. The processing method for implementing 4g &5g rate matching and interleaving by shared hardware as claimed in claim 2, wherein the turbo code address mapping formula is

4. The processing method for implementing 4G &5G rate matching and interleaving by shared hardware as claimed in claim 3, wherein said turbo code cyclic buffer formula is

5. The method for implementing 4G &5G rate matching and interleaving by shared hardware according to any one of claims 1-4, wherein the memory sharing unit performs block interleaving processing on a convolutional code in 4G LTE, and the operation sharing unit performs code rate matching on the convolutional code in 4G LTE, specifically including:

In the sub-block interleaving part of the convolutional code, three paths of bit streams with equal length are input to three sub-block interleavers, the sub-block interleavers are row-column interleaving, and the minimum line number of the sub-block interleavers is determined through the length of the bit streams and the line number of the sub-block interleavers;

If the length of the bit stream is equal to the minimum product of the number of columns and the number of rows of the sub-block interleaver, the bit stream sequentially enters the sub-block interleaver;

if the bit stream length is smaller than the minimum product of the number of columns and the number of rows of the sub-block interleaver, filling null bits into the sub-block interleaver;

performing inter-column replacement on the bit sequences written into the subblock interleaver in the bit collection and cyclic buffer part of the convolutional code, and after the inter-column replacement is completed, putting the output bit stream into a cyclic buffer area according to the sequence of a convolutional code cyclic buffer area formula for bit collection;

And in the bit selection part of the convolutional code block, after the convolutional code completes bit collection, completing bit selection.

6. The processing method for implementing 4G &5G rate matching and interleaving by shared hardware as claimed in claim 5, wherein said bit stream is formulated according to a convolutional code circular buffer formula

7. The processing method for implementing 4G &5G rate matching and interleaving by shared hardware according to claim 6, wherein the determining the block interleaving and rate matching algorithm of the polar code in 5G NR specifically comprises: at the sub-block interleaving part of the polar code, the bit stream output by encoding enters 32 sub-blocks to be subjected to sub-block interleaving respectively, so as to obtain an output sequence yk;

In the bit selection part of the polar code, carrying out bit selection on the output sequence yk to obtain a rate matching output sequence, setting the length of the rate matching output sequence of the polar code as 864, and carrying out bit selection according to the length of the bit stream before encoding and the length of the bit stream after encoding to obtain a bit selection output sequence ek;

And in the bit interleaving part of the polar code, keeping the length of a bit interleaving sequence fk of the polar code equal to that of the bit selecting output sequence ek, and selecting isosceles right triangle interleaving in a bit interleaving mode.

8. The processing method for implementing 4G &5G rate matching and interleaving by shared hardware according to claim 7, wherein the determining the block interleaving and rate matching algorithm of the LDPC code in 5G NR specifically comprises: a bit selection part in the LDPC code block interleaving and rate matching algorithm, wherein each code block independently codes and outputs a bit sequence with the length of N, and the bit sequence with the length of E is processed and output according to the LDPC code bit selection algorithm;

And in the bit interleaving part of the LDPC, bit interleaving is completed in a block interleaving mode according to an LDPC code bit interleaving algorithm, the output sequence length is E, and the number of lines is the modulation order Qm.