CN102316059A - Interweaving method and device of OFDM (orthogonal frequency division multiplexing) system - Google Patents

Abstract

The invention relates to interweaving method and device of an OFDM (orthogonal frequency division multiplexing) system, which belong to the field of communication. The interweaving method of the OFDM system comprises the following steps: 1, carrying out serial-parallel conversion on a serial data stream to form a parallel data stream; 2, splitting an interweaver into a plurality of RAMs (random access memories), calculating addresses of the RAMs and inside addresses of the RAMs according to a reading address and a writing address of the interweaver, and interweaving the parallel data stream by using the RAMs. By using the method and the device, the area, the cost and the power consumption of an interweaver device can be decreased, and the requirements of a wireless communication system on low cost, small area and low power consumption are met.

Description

A kind of deinterleaving method of ofdm system and device

Technical field

The present invention relates to the communications field, relate in particular to a kind of deinterleaving method and device of ofdm system.

Background technology

The OFDM technology disturbs because of its strong multipath and the ability of anti-frequency selective fading is widely used in the multiple high-speed data access system, like WLAN, HDSL High-Speed Digital Subscriber Line, Asymmetrical Digital Subscriber Line, number audio broadcasting, DVB and HD digital TV etc.Many worlds, domestic standard are the transmission means of OFDM as physical layer.

In ofdm system, the burst error of using channel interleaving can effectively break up the channel decoder input reduces error rate of system.In ofdm system, different interleaving schemes can be arranged,, interweave etc. through cyclic shift like sub-carrier interleaving, symbol interleaving.After interweaving, the adjacent encoder stream of exporting from encoder no longer has correlation, and the burst error that produces in the channel is scatter, and demonstrates the characteristics of random error.Receiving terminal is corrected these random errors through using the strong channel decoder of error correcting capability through after the deinterleaving, improves the reliability of system.

In many systems, interweave and form by three steps, intersymbol interweaves, sub-carrier interleaving and circulation interweave.Symbol interleaving is placed on different OFDM symbols with script at the data branch of an OFDM symbol, can resist the noise of frequency band broad like this.And sub-carrier interleaving is upset the different subcarriers order in an OFDM symbol, thereby can resist narrow band interference.In addition, the OFDM symbol also will carry out the subcarrier circulation in each OFDM symbol inside and move, and this is for further increase system antijamming capability.

But because the high hundreds of megahertzes of some broadband system operating frequency need the very high RAM of operating frequency, but the RAM cost of hundreds of megahertzes of working are very high, power consumption is also very big.Can reduce the operating frequency of interleaver through multidiameter delay, but reduce operating frequency, mean that needs can support the RAM that multidiameter delay is read and write, yet this can increase the RAM cost again, does not utilize low-cost low complex design.In addition; If use register to build interleaver, can satisfy the requirement that operating frequency is high or multidiameter delay is read and write, problem is that the integrated level of register will be much smaller than array ram; And when interleaver is bigger; Need realize it being to generate complicated decoding logic at hardware, the result causes area very big, is not easy to control power consumption and cost.

Summary of the invention

In order to solve above-mentioned technical problem, a kind of deinterleaving method and device of ofdm system is provided, its purpose is to reduce area, cost and the power consumption of interleaving apparatus, satisfies low cost, small size and the low-power consumption requirement of wireless telecommunication system.

The invention provides a kind of deinterleaving method of ofdm system, comprising:

Step 1 is carried out serial to parallel conversion to serial data stream and is formed parallel data stream;

Step 2 is split as a prime number RAM with interleaver, calculates the address of said RAM and the interior address of said RAM according to the read/write address of interleaver, utilizes this prime number RAM that parallel data stream is interweaved.

Said RAM is a dual port RAM; The memory space of each RAM among the said prime number RAM is identical.

The address is according to computes in the address of said RAM and the described RAM:

Address=mod of said RAM (read/write address of interleaver, the quantity of RAM);

The quantity of the interior address of said RAM=(address of the read/write address-RAM of interleaver)/RAM.

The one ROM and the 2nd ROM are set, and the interior address of the address of said RAM and said RAM is stored a said ROM and said the 2nd ROM into, and a said ROM is used for write address to said interleaver being provided, and said the 2nd ROM is used for providing to said interleaver and reads the address.

First counter and second counter are set, and a said ROM provides the address by said first counter, and said the 2nd ROM provides the address by said second counter.

The invention provides a kind of interlaced device of ofdm system, comprising:

The serial to parallel conversion module is used for that serial data stream is carried out serial to parallel conversion and forms parallel data stream;

Interleaver, this interleaver comprise a prime number RAM; The interior address of the address of said RAM and said RAM calculates according to the read/write address of interleaver, and a said prime number RAM interweaves to parallel data stream.

Said RAM is a dual port RAM; The memory space of each RAM among the said prime number RAM is identical.

The address is according to computes in the address of said RAM and the described RAM:

Address=mod of said RAM (read/write address of interleaver, the quantity of RAM);

The quantity of the interior address of said RAM=(address of the read/write address-RAM of interleaver)/said RAM.

This interlaced device also comprises a ROM and the 2nd ROM; The interior address of the address of said RAM and said RAM is stored a said ROM and said the 2nd ROM into; A said ROM is used for write address to said interleaver being provided, and said the 2nd ROM is used for providing to said interleaver and reads the address.

This interlaced device also comprises first counter and second counter, and a said ROM provides the address by said first counter, and said the 2nd ROM provides the address by said second counter.

The present invention can reduce area, cost and the power consumption of interleaving apparatus, satisfies low cost, small size and the low-power consumption requirement of wireless telecommunication system.

Description of drawings

Fig. 1 is a deinterleaving method flow chart provided by the invention;

Fig. 2 is an interleaving apparatus sketch map provided by the invention.

Embodiment

The present invention operates through multidiameter delay and reduces the interleaver operating frequency, improves the RAM readwrite bandwidth.At first interleaver is realized that required buffer memory splits into a prime number little block RAM, and then increase the read/write conflict that the RAM bandwidth avoids reading while write a plurality of operands, wherein each little block RAM is called body.Like this, if each body and function two-port RAM realizes that then interleaver can use N piece two-port RAM to realize.The read/write address of interleaver and then convert body address and inner address into, shown in formula (1):

bank_addr＝mod(c，bank_num)；

bank_inner_addr＝(c-bank_addr)/bank_num； (1)

Read/write address when wherein c is interleaver work, bank_num is the sum of body, and mod () is for asking the mould operation, and bank_addr is the body address, and bank_inner_addr is an inner address.

The present invention provides suitable read/write address generator.After interleaver splits into a prime number RAM body; Need mod circuit and divider; Because system is multidiameter delay work, then need a plurality of mod circuits and division circuit the result of counter is converted into corresponding body address and inner address, hardware realization expense is quite big like this.The present invention is converted into corresponding body address and inner address in advance with the read/write address of interleaver and stores in the ROM; Two counters are set then as the ROM address; So just can to spatial cache read/write address be provided in real time, avoid hardware to realize the big problem of expense simultaneously.If with the read-write control signal transposing is exactly the interleaver of receiving terminal.

In system bandwidth is in the wideband OFDM system of 528MHz, and sample frequency is 528MHz.At transmitting terminal, each coding back output 3bits of encoder is mapped as QPSK.Soft-decision at receiving terminal sampling 3bits.Interweave in the bit of symbol interleaver behind 1200 codings.Its list entries U (i) and output sequence S (i) relation are suc as formula shown in (2).I=0 wherein ..., (6/TSF) * N _CBPS-1, TSF=1, N _CBPS=200, the maximum integer smaller or equal to this number is returned in Floor () expression, and Mod () is the operation that rems.

$S\left(i\right)=U\{\mathrm{Floor}\left(\frac{1}{N_{\mathrm{CBPS}}}\right)+(6/\mathrm{TSF})*\mathrm{Mod}(i,N_{\mathrm{CBPS}})\}(6/\mathrm{TSF})*N_{\mathrm{CBPS}}---\left(2\right)$

The output of symbol interleaver is the input of sub-carrier interleaving device, wherein every N _CBPSIndividual bit interweaves by formula (3).N wherein _Tint=N _CBPS/ 10, i=0 wherein ..., N _CBPS-1.The relation of list entries S (i) and output sequence T (i) is suc as formula shown in (3).

$T\left(i\right)=S\{\mathrm{Floor}\left(\frac{i}{N_{\mathrm{Tint}}}\right)+10\mathrm{Mod}(i,N_{\mathrm{Tint}})\}---\left(3\right)$

The output T (i) of sub-carrier interleaving device is pressed N _CBPSIndividual bit is divided for one group, its output sequence be V (b, i), every group of data are by formula 4 cyclic shifts, i=0 wherein ..., N _CBPS-1, A (b) value is following:

V(b，i)＝T(b，mod(i+A(b)，N _CBPS)) (5)

According to top analysis, can find out that in wideband OFDM system complete interleaver can be accomplished by three steps, intersymbol interweaves, interweaving and circulate between subcarrier interweaves.Interleaver is designed to three grades according to the data flow order, and (b is i) with the mapping relations of U (i), then as long as one-level interweaves just passable to have confirmed V.The mapping relations of its input and output are as follows:

Step 1: make i, j, t1, t2, the initial value of t are 0; Work as N _CBPS=200, cyclic is 66 during TSF=2, and other patterns are 33.

Step 2: make t=j+cyclic * i; If t is greater than N _CBPS, t=t-N then _CBPS

Step 3: the result's that interweaves output inner address t1=floor (t/N _TNIT)+10 * mod (t, N _TINT).

Step 4: output body address t2=6/TSF * t1+i of the result that interweaves.

Step 5: if j＜N _CBPSJump to step 2, and j=j+1; If j=N _CBPSJump to step 6.

Step 6: if i＜6/TSF jumps to step 2, and i=i+1; If i=6/TSF finishes.

Wherein mod () is respectively with floor () and asks mould and rounding operation.

For sending interleaver, its write address adds up by natural order, is that mapping relations by formula 2-5 change and read the address.In this instance, the highspeed serial data stream of input is 528Mbps, and in order to reduce operating frequency, the employing MUX is gone here and there and changed, and high-speed data-flow is converted into the two-way rate data streams of the 264Mbps of low speed, shown in Fig. 1 first step.In this instance, each circuit-switched data stream is that the convolution coder of 1/3 code check generates, and need write 6 words simultaneously so the two-way rate data streams means interleaver; In addition, interleaver need be follow-up QPSK mapping block input mapping (enum) data, so interleaver will be follow-up 4 words of mapping block output in this instance.

Write 6 word latter from an interleaver simultaneously and read 4 words, need the RAM that realizes interleaver can support 6 port read writes, cost was very high when this realized at hardware.This instance splits to increase readwrite bandwidth the RAM that realizes interleaver; When the bank_num in the formula 1 is prime number; Once write 6 word latter from interleaver and read 4 words, in an individuality, read two words at most, this instance requires to be chosen as that to tear block count open be 7 according to instance system.Like this, if the cheap two-port RAM of each body and function replaces, then the monoblock interleaver is with just using 7 two-port RAMs to realize that wherein every block RAM is 176 * 3bits.Shown in second step of Fig. 1.

But after the RAM fractionation, interleaver need design a plurality of read/write address generators, shown in the 3rd step of Fig. 1.Ask modular arithmetic and divide operations in the mapping relations of formula 2-5 input and output need mod circuit and divider, because in this example, need four tunnel read operations or six road write operations at most simultaneously.Then need 10 mod circuits and division circuit the result of counter is converted into corresponding body address and inner address, hardware realization expense is quite big like this.A kind of simple implementation method is read/write address to be converted into corresponding body address and inner address in advance store in the ROM (ROM can be independent of interleaver) among the present invention; Two counters are set then as the ROM address, so just can to spatial cache read/write address be provided in real time.If with the read-write control signal transposing is exactly the interleaver of receiving terminal.

Detailed implementation is as shown in Figure 2, and whole interleaver utilizes two 1200x3bit RAM to form ping-pong structure and realizes, wherein the RAM of every 1200x3 utilizes 176 * 3bitRAM of 7 dual-ports to form, and sequence number is BANK0-BANK6.In addition, generate two read-write counters by natural order counting, this counter is respectively as the address of reading of two ROM, the ROM storage inside be the V that pre-deposits (b, i) with the mapping relations of U (i), just the body address and the inner address of each two-port RAM.Like this, can conveniently realize interweaving memory cell and address generator.Utilize the cheap two-port RAM array of low speed to realize the interleaver of speed through this structure up to 528MHz.

Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but confirm by the scope of claims.

Claims (10)

1. the deinterleaving method of an ofdm system is characterized in that, comprising:

Step 1 is carried out serial to parallel conversion to serial data stream and is formed parallel data stream;

Step 2 is split as a prime number RAM with interleaver, calculates the address of said RAM and the interior address of said RAM according to the read/write address of interleaver, utilizes this prime number RAM that parallel data stream is interweaved.

2. the deinterleaving method of ofdm system as claimed in claim 1 is characterized in that, said RAM is a dual port RAM; The memory space of each RAM among the said prime number RAM is identical.

3. the deinterleaving method of ofdm system as claimed in claim 2 is characterized in that, calculate according to the following equation the interior address of described address ram and said RAM:

Address=mod of said RAM (read/write address of interleaver, the quantity of RAM);

The quantity of the interior address of said RAM=(address of the read/write address-RAM of interleaver)/RAM.

4. the deinterleaving method of ofdm system as claimed in claim 3; It is characterized in that; The one ROM and the 2nd ROM are set; The interior address of the address of said RAM and said RAM is stored a said ROM and said the 2nd ROM into, and a said ROM is used for write address to said interleaver being provided, and said the 2nd ROM is used for providing to said interleaver and reads the address.

5. the deinterleaving method of ofdm system as claimed in claim 4 is characterized in that, first counter and second counter are set, and a said ROM provides the address by said first counter, and said the 2nd ROM provides the address by said second counter.

6. the interlaced device of an ofdm system is characterized in that, comprising:

The serial to parallel conversion module is used for that serial data stream is carried out serial to parallel conversion and forms parallel data stream;

Interleaver, this interleaver comprise a prime number RAM; The interior address of the address of said RAM and said RAM calculates according to the read/write address of interleaver, and a said prime number RAM interweaves to parallel data stream.

7. the interlaced device of ofdm system as claimed in claim 6 is characterized in that, said RAM is a dual port RAM; The memory space of each RAM among the said prime number RAM is identical.

8. the interlaced device of ofdm system as claimed in claim 7 is characterized in that, the address is according to computes in the address of said RAM and the described RAM:

Address=mod of said RAM (read/write address of interleaver, the quantity of RAM);

The quantity of the interior address of said RAM=(address of the read/write address-RAM of interleaver)/RAM.

9. the interlaced device of ofdm system as claimed in claim 8; It is characterized in that; This interlaced device also comprises a ROM and the 2nd ROM; The interior address of the address of said RAM and said RAM is stored a said ROM and said the 2nd ROM into, and a said ROM is used for write address to said interleaver being provided, and said the 2nd ROM is used for providing to said interleaver and reads the address.

10. the interlaced device of ofdm system as claimed in claim 9; It is characterized in that; This interlaced device also comprises first counter and second counter, and a said ROM provides the address by said first counter, and said the 2nd ROM provides the address by said second counter.

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