CN104539568A - CDR modulation module and subframe distribution module thereof - Google Patents

CDR modulation module and subframe distribution module thereof Download PDF

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Publication number
CN104539568A
CN104539568A CN201410840083.5A CN201410840083A CN104539568A CN 104539568 A CN104539568 A CN 104539568A CN 201410840083 A CN201410840083 A CN 201410840083A CN 104539568 A CN104539568 A CN 104539568A
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China
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module
sub
frame allocation
data
addr
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顾明飞
郑鑫
汤善武
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Chengdu Kaitengsifang Sifang Digital Broadcast & Television Equipment Co Ltd
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Chengdu Kaitengsifang Sifang Digital Broadcast & Television Equipment Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2628—Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource
    • H04W72/0446—Resources in time domain, e.g. slots or frames

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

The invention discloses a CDR modulation module and a subframe distribution module thereof and relates to digital information transmission. The CDR modulation module is efficient, saves more storage resources, and reduces time delay. The CDR modulation module is characterized in that the CDR modulation module comprises a subframe distribution control module, a subcarrier mapping module, a constellation mapping module, an OFDM modulation module, a beacon module, a logic framing module, a physical layer signal frame module and a base band to radio frequency conversion module, wherein the subframe distribution control module, the subcarrier mapping module, the constellation mapping module, the OFDM modulation module, the beacon module, the logic framing module, the physical layer signal frame module and the base band to radio frequency conversion module are connected in sequence, and the CDR modulation module further comprises a data input analyzing module, a service data channel, a service description channel, a system parameter channel and a scattered pilot module, wherein the data input analyzing module is in signal connection with the service data channel, the service description channel and the system parameter channel; the service data channel, the service description channel and the system parameter channel are in signal connection with the subframe distribution control module.

Description

A kind of CDR modulation module and sub-frame allocation module thereof
Technical field
The present invention relates to digital information transmission, relate to the Digital Implementation of the transmitting terminal modulator of CDR (Chinese Digital audio broadcasting) system.
Background technology
OFDM: OFDM; CDR: Chinese Digital audio broadcasting; LDPC: low density parity check code; MSC: main business passage; CIC: business description passage; CPT: system configuration information; SPT: scattered pilot information.
" People's Republic of China's radio, film and television industry standard " GY/T 268.1-2013 (hereinafter referred to as " standard ") proposes the basic framework of CDR (broadcast of China Digital Radio Chinese Digital) transmitting terminal modulator and realizes requirement, see Fig. 1, the CDR modulation module that standard proposes comprises main business data channel, business description passage, system parameters passage, OFDM modulation module, logical frame framing module, scattered pilot module, beacon module, sub-frame allocation module, physical layer signal frame module and radio frequency modular converter, main business data channel, business description passage and system parameters passage, scattered pilot module all has signal with OFDM modulation module and is connected, OFDM modulation module and beacon module all have signal with logical frame framing module and are connected, logical frame framing module, sub-frame allocation module, physical layer signal frame module and radio frequency modular converter are linked in sequence.
Sub-frame allocation is such:
In CDR modulated process, the maximum length related to of sub-frame allocation is a superframe, and a superframe length is 2560ms, and the physical layer signal frame that each superframe is 640ms by 4 length forms, it is the subframe of 160ms that each physical layer signal frame comprises 4 length, and each subframe comprises 1 beacon and S nindividual OFDM symbol, S nvalue under transmission mode 1,2,3 is respectively 56,111,61.Logical frame, logic subframe and OFDM symbol structural relation are as Fig. 2.
Sub-frame allocation, in units of logic subframe, is carried out subframe and is rearranged in a superframe, and standard specifies that it has 3 kinds of methods of salary distribution, and sub-frame allocation mode 1 does not change four original orders of logic subframe in each logical frame, as Fig. 3.Sub-frame allocation mode 2 is redistributed, as Fig. 4 with each logic subframe in continuous print two logical frame.Sub-frame allocation mode 3 is redistributed, as Fig. 5 with each logic subframe in a superframe.
That is, sub-frame allocation is the process that the subframe in the superframe received is redistributed according to sub-frame allocation rule, stored by sub-frame allocation module in each logical frame, if the physics realizations such as FPGA are carried out causing storage resources to waste with sequential organization, and increase time delay, data after general IFFT are 16bit bit wide, buffer memory superframe data, 2 memories are rattled, and the capacity of the required storage resources of waste is: 50688 × 4 × 4 × 16 × 2 × 2=51904512bit.
Summary of the invention
Technical problem to be solved by this invention is: for above-mentioned Problems existing, provides one more to save storage resources, reduce time delay simultaneously, optimization architecture, the CDR modulation module of effective implemention.
The present invention has done following improvement on the CDR modulation module basis that standard proposes, and comprises data input parsing module, business datum passage, business description passage, system parameters passage, scattered pilot module, sub-carrier mapping module, constellation mapping block, OFDM modulation module, logic framing module, beacon module, physical layer signal frame module and base band to radio frequency modular converter; Wherein,
Data input parsing module has signal with business datum passage, business description passage, system parameters passage respectively and is connected.
Business datum passage, business description passage, system parameters passage have signal with sub-carrier mapping module and are connected.
Business datum passage comprises sub-carrier interleaving module; Business description passage comprises business description channel bit interleaving block; System parameters passage comprises system parameters channel bit interleaving block.
Sub-carrier mapping module, constellation mapping block, OFDM modulation module, logic framing module, physical layer signal frame module and base band are linked in sequence to radio frequency modular converter.
Scattered pilot module and sub-carrier mapping module have signal and are connected; Beacon module has signal with logic framing module and is connected.
In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:
1, the present invention realizes the CDR modulation module framework that standard proposes, and carrying out structural adjustment optimization, saving storage resources, shortening time delay, having simplified structure, achieving CDR modulation module efficiently capable and vigorously when realizing.
2, the invention provides a kind of subframe allocation method, achieve the requirement of standard neutron frame allocation rule.
3, native system clock uses the clock setting of simplifying, four kinds of different clocks are set in the module, the input of network interface that the clock setting of 25MHz is compatible, 81.6 MHz adopt high clock rate, can complete encoding tasks at a high speed, effectively reduce system delay, clock rate and the system output speed of 816kHz match, and simplify OFDM symbol sub-carriers packing module, the design of OFDM modulation module, base band adopts 3.264MHZ clock to radio-frequency module.In a word, employing is simplified timing topology as above and is well met system requirements, and simplifies design.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is the CDR modulation module that standard proposes;
Fig. 2 is logical frame, logic subframe and OFDM symbol structure chart;
Fig. 3 is sub-frame allocation mode 1; Fig. 4 is sub-frame allocation mode 2; Fig. 5 is sub-frame allocation mode 3;
Fig. 6 is the FB(flow block) that CDR modulation module FPGA of the present invention realizes;
Fig. 7 is subcarrier matrix structure; Fig. 8 is the symbolic number of MSC and CIC under each transmission mode;
Fig. 9 is the placement location of CIC in subcarrier matrix under each transmission mode;
Figure 10 is that CPT arranges position in subcarrier matrix;
Figure 11 is that the placement that repeats of CPT is gone; Figure 12 is that SPT arranges position in subcarrier matrix;
Figure 13 is that transmission mode 1 time four subband intersection chart show;
Figure 14 is transmission mode 1 time MSC data volume in each ofdm symbol;
Figure 15 transmission mode 1 time 4 subband weaving flow journey;
Figure 16 is CIC acoustic convolver structure; Figure 17 is that CIC Bit Interleave address produces desired parameters;
Figure 18 is that CIC Bit Interleave address produces flow chart;
Figure 19 is that Bit Interleave realizes block diagram; Figure 20 is CRC check circuit structure;
Figure 21 is the realization of the sub-frame allocation function of main business information;
Figure 22 is the realization of the sub-frame allocation function of business description information;
Figure 23 is sub-carrier mapping module internal structure block diagram;
Figure 24 is 2048 subcarrier diagrams; Figure 25 is the power normalization of each modulating mode;
Figure 26 is QPSK mapped constellation points; Figure 27 is 16QAM mapped constellation points; Figure 28 is 64QAM mapped constellation points;
Figure 29 1024 and 2048 to count configurable FFT/IFFT processor overall structure figure;
Figure 30 is the arithmetic element structure of FFT/IFFT processor;
Figure 31 is logic framing control flow; Figure 32 is native system Clock Design diagram.
Embodiment
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Arbitrary feature disclosed in this specification, unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object.That is, unless specifically stated otherwise, each feature is an example in a series of equivalence or similar characteristics.
As Fig. 6, the CDR modulation module that the present invention proposes comprises data input parsing module, business datum passage, business description passage, system parameters passage, scattered pilot module, sub-frame allocation control module, sub-carrier mapping module, constellation mapping block, OFDM modulation module, beacon module, logic framing module, physical layer signal frame module and radio frequency modular converter.
Wherein, data input parsing module has signal with business datum passage, business description passage, system parameters passage respectively and is connected.Multiplexed data flow inputs data by network interface and enters parsing module, and multiplexed data flow is resolved to main business data (MSC), business description data (CIC) and system parameters (CPT) to form 3 paths information needed for modulator by data input parsing module.Interface parsing work mainly completes 3 functions: in CPT stream, extract modulation intelligence, complete the parallel-serial conversion of data, generation superframe is enable, logical frame enable signal.
Business datum passage, business description passage, system parameters passage have signal with sub-frame allocation control module and are connected.
Sub-frame allocation control module, sub-carrier mapping module, constellation mapping block, OFDM modulation module, logic framing module, physical layer signal frame module and radio frequency modular converter are linked in sequence.
Scattered pilot module and sub-carrier mapping module have signal and are connected; Beacon module has signal with logical frame framing module and is connected.
Below the composition and working principle of modulation module each several part of the present invention is elaborated.
The process of 1.MSC channel data
1.1 in digital communication, needs occurring that 0 or 1 of length carries out signal randomization, otherwise can affect the antijamming capability of data.In order to eliminate this phenomenon, usually adopt signal scrambling technique, and unnecessary information need not be increased.The scrambler generator polynomial of main business data is:
P (i)=x 12+ x 11+ x 8+ x 6+ 1 formula 1
1.2 scrambled after data enter LDPC processing module.
Map process after 1.3 LDPC codings export, map is the bit splicing in units of bit number needed for constellation mapping, using this Bit String as a qam symbol, participation sub-carrier interleaving and sub-frame allocation, and after formal constellation mapping is positioned at sub-frame allocation.Such as, the generation bit of a 4QAM symbol is 10, then the Bit String 10 of continuous adjacent is used as a 4QAM symbol, needs 6bit at most for 64QAM, so the data after map represented with required maximum 6bit bit wide.After completing splicing, data send sub-carrier interleaving resume module.
In 1.4 subcarrier matrixes, data genaration is filled
Each OFDM symbol has N v* N iindividual effective subcarrier, it comprises: continuous pilot, scattered pilot and data subcarrier (business description information and main business data).Structure line number is 4*S n, columns is N v* N isubcarrier matrix M s,t, (as Fig. 7).Wherein S nbe the OFDM symbol line number of a logic subframe, N ifor effective sub band number, N vfor subcarrier matrix M s,tcolumns, then a logical frame comprises effective sub-carrier number: (4*S n) * (N v* N i).Fig. 7 illustrates the structure of subcarrier matrix.
1.4.1MSC in subcarrier matrix in units of logical frame from top to bottom, from left to right put successively (in Fig. 7 arrow order).MSC data message transmits in units of a logical frame, and under list band, its various transmission mode data symbol number is as Fig. 8.
1.4.2 CIC transmits in units of a logical frame, and CIC is placed on subcarrier matrix M s,ton in the position of specifying, the concrete quantity of placing CIC information is shown in Fig. 8, and subcarrier matrix position is as 1 to N in Fig. 9, figure sDISndata element in row is all CIC, N sDISn1 to N in+1 row sDISvaliddata element be also CIC.The disposing way of CIC in subcarrier matrix and MSC similar, according to from top to bottom, from left to right, i.e. arrow direction indication in Fig. 7.
1.4.3 CPT transmits in units of a logic subframe, and CPT is placed on subcarrier matrix M s,ton middle position of specifying, its position arranged in each row as shown in Figure 10.Under a logic subframe, 108 symbols of system information repeat two to three times, and the concrete line number that repeats is shown in Figure 11.
1.4.4 scattered pilot is filled in units of lower 3 OFDM symbol of list band, and scattered pilot is placed on the position of specifying in subcarrier matrix, and its position arranged in each row as shown in figure 12.Scattered pilot fills given data symbol, and its generator polynomial is poly=x 11+ x 9+ 1, data symbol adopts QPSK modulation, and the relative displacement of I road bit stream and Q road bit stream is 8, adopts [01010100101] to be initial condition value.Under different transmission mode, the bit length of I/Q two-way is L pn i, wherein N ifor sub band number, L pfor SPT number in lower 3 OFDM symbol of list band.L in transmission mode 1 and 3 pbe 62, L in transmission mode 2 pbe 32.The symbol of the PN sequence more than produced after QPSK modulation brings to the right band by the left side and is successively placed on relevant position.SPT in logic subframe with 3 OFDM symbol for the cycle repeats.
1.4.5 sub-carrier interleaving for be MSC, it realizes the intertexture being divided into the intertexture in single subband and multiple intersubband, if the just transfer of data of single subband, only complete the intertexture in single subband, multiple subband data transmits the intertexture of intertexture and the intersubband then simultaneously completed in single subband.Be implemented as follows: the transfer of data of single subband interweaves and realizes: the data interlacing algorithm in single subband is Bit Interleave algorithm, itself and CIC information channel, the Bit Interleave algorithm of CPT information channel is identical.
If the list entries before interweaving is wherein N mUXfor the length of interleaving block, the output sequence after intertexture is: then v n=u r (n), wherein R (n) can try to achieve according to following algorithm:
formula 2
Wherein, p (0)=0,
formula 3
Here at transmission mode 1,2 times N mUXvalue is 46080, and transmission mode 3 times values are 50688, by N mUXbring formula 2 into, 3, obtain sequence and be respectively (0, 16383, 32762, 15603 ... 36045), (0, 16383, 32762, 49121 ... 36045), to two sequences be 0 stored in address respectively above, 1, 2 ... 46079, 0, 1, 2 ... in the array of 50687, be numerical value 0 by value in array, 1, 2 ... 46079, 0, 1, 2 ... 50687, corresponding address value takes out and forms new address sequence (0, 41520, 14074, 15173 ... 17921), (0, 45662, 15548, 5722 ... 2793), this address sequence is the new address of data through interweaving in subband or after Bit Interleave that order enters this interleaving block.
The data interlacing of multiple subband realizes: the realization of the data interlacing of multiple subband will complete the intertexture of intertexture in single subband and intersubband, here with transmission mode 1 (4 maximum subbands), whole interleaving process is described, Figure 13 is seen in the interleaving data block position of each intersubband, in figure, 0 is CIC data, 1,2,3,4 is 4 subbands of actual intertexture.Before each actual intertexture subband data is distributed in and interweaves in subband, the data after intertexture are put from top to bottom with OFDM symbol number.The main business data of each subband data volume in each ofdm symbol as shown in figure 14.
It is that from top to bottom, from left to right come successively, be designated as subband nature_subbands before interweaving, the position in the current sub-band of data place is designated as nature_addr with subband 1 to subband 4 that a upper module data sends.Data in Figure 13 in each clinodiagonal are actual intertexture subband, and the main business amount of N number of subband is then the N in Fig. 8 times (N refers to number of sub-bands here, gets 1,2,4).In many subbands business datum interweaves, it enters intertexture in units of symbol, and the intertexture of 4 subbands is comparatively typical, its weaving length is 4 subbands of a logical frame.Be 46080 × 4 in transmission mode 1,2 times length, transmission mode 3 times length are 50688 × 4.According to the sequencing of data flow, each subband is related to that its address is for (0 ~ 46079,0 ~ 50687), namely logical frame has 4 such circulation addresses.By address nature_addr quarter to produce address nature_addr_sub, its relation is as table one.
Table one nature_addr and nature_addr_sub Figure of the quantitative relationship
The calculating of current interlace subband subbands_inv is carried out by nature_addr_sub, the initial ranges of current data address place circulation fritter is calculated by formula 4, wherein cycle_num is the length of the cycle of main business data in every 3 OFDM symbol in subband, in transmission mode 1,3, get 640, in transmission mode 2, get 322.Remain1 is residual value.
Nature_addr_sub=quotient1*cycle_num+remain1 formula 4
After obtaining quotient quotient1 and residual value remain1, the occurrence of subbands_inv can be found by table two.In table two, quotient1 [1:0] gets the low 2 of binary number for quotient1.
Current interlace subband value under table two transmission mode 1
Remain1 value in table two is become (0 ~ 105; 106 ~ 213; Other value) namely obtain the occurrence of the subbands_inv under transmission mode 2; Remain1 value in table two is become (0 ~ 213; 214 ~ 427; Other value) namely obtain the occurrence of the subbands_inv under transmission mode 3.
The method calculating final interleaving address due to transmission mode 1,2,3 is afterwards similar, sets forth interleaving address generation method herein for transmission mode 1.The front address of intertexture due to each subband is (0,1,2 ... 46079) (have here 4 such address), try to achieve each subband data according to the method interweaved in aforementioned subband and carry out the rear address (0,41520,14074,15173 that interweaves that interweaves in single subband to obtain ... 17921), represent with num_addr_inv.Here in order to ensure the interleaving address producing data continuously, the mode of tabling look-up is adopted to generate interleaving address num_addr_inv.
Because the actual intertexture subband after intertexture in subband residing for it does not become, and MSC data volume is with the circulation of (214,212,214) in each OFDM symbol row in list band, so (MSC data address counts the final address in the OFDM symbol at data place after can calculating intertexture easily according to actual intertexture subband (0,1,2,3) and the interleaving address in this subband thereof in OFDM symbol row from 0 here, from left to right, increase progressively from top to bottom, be not counted in the OFDM symbol row without MSC data).
Can obtain quotient quotient2 by formula 5 and residual value remain2, quotient2 have how many cycle_num (transmission mode gets 640 1 time) in single subband, remain2 is remainder.
The final interleaving address generated of order is final_addr again, is calculated by formula 7.Wherein, integer_addr is the cycle_num × N of integral multiple, N is transfer of data subband number, gets 4, see formula 6 in the present embodiment; Block_addr is calculated by formula 8; Add_addr is calculated by formula 9.
Table look-up three according to quotient quotient2 and residual value remain2, table four, remain_addr when table five can obtain transmission mode one, two, three respectively.
Num_addr_inv=quotient2*cycle_num+remain2 formula 5
Integer_addr=quotient2*cycle_num*N formula 6
Final_addr=block_addr+integer_addr+remain_addr-add_addr formula 7
formula 8
formula 9
。
Remain_addr exploitation in table three transmission mode 1
Quotient2 [1:0] in table gets the low 2 of binary number for quotient2.
Remain_addr exploitation in table four transmission mode 2
Remain_addr exploitation in table five transmission mode 3
Data after final intertexture in address are OFDM symbol from left to right, are arranged in order desired data from top to bottom.Concrete intertexture flow process is shown in Figure 15.The data interlacing of multiple subbands of other transmission mode is similar.
The process of 2.CIC channel data
2.1 CIC scrambled portions are identical with MSC.
The acoustic convolver of 2.2 CIC resets linear feedback shift register in the original position of each logical frame, and concrete structure is shown in Figure 16.Convolution results is the parallel data of 4 bits, it is stored in respectively in 4 memories.
The Output rusults of 2.3 acoustic convolvers will be used for interweaving, and the interleaving block size of CIC Bit Interleave is relevant to modulating mode and transmission mode, and the interleaving address that can be obtained under various transmission mode and modulating mode by formula 3 produces desired parameters (Figure 17).
CIC Bit Interleave is identical with the interleaving address production method of CPT Bit Interleave, and idiographic flow is shown in Figure 18.
The convolution results of a upper module being placed in 4 memories is in order to avoid carrying out parallel-serial conversion, to reduce complexity.The higher bit position of the Bit Interleave address produced is used as the address (bit wide changes according to weaving length) of data in reading 4 memories, the road that low bit (minimum 2) reads data in 4 memories for gating exports, as: 00 gating ram1_inv1 is as output, 01,10,11 analogize, and concrete structure is shown in Figure 19.
Data after 2.4 CIC Bit Interleaves carry out map (map process is shown in 1.3).
Data after map are stored into cic_ram1 by 2.5, and in cic_ram2, two ram become ping-pong structure.
The process of 3.CPT channel data
48 bit system parameters are sent into generate CRC check position in shift register by 3.1 successively, generate formula be: G6 (x)=x6+x5+x3+x2+x+1, structural reference standard as shown in figure 20:
3.2 convolution, Bit Interleave, map, final data enters memory and CIC part is similar.
4. sub-frame allocation realizes
4.1 sub-frame allocation principles are shown in background technology
The realization of the sub-frame allocation function of 4.2 main business information.Here set forth with the realization of 2 subbands, 4 subbands are similar.The address of 2 subband interleaved data is designated as msis_addr_inv, its span in a logical frame length, if the scope under transmission mode 1 is (0 ~ 92159).Enter the priority of sub-frame allocation functional module according to data, add up its logical frame belonging in a superframe, be designated as msis_logic_num, (00), (01), (10), (11) represent the 1st respectively, 2,3,4 logical frame.Value according to address msis_addr_inv divides logic subframe, address realm (0 ~ 23039), (23040 ~ 46079), (46080 ~ 69119), (69120 ~ 92159) are correspondence the 1st, 2,3 respectively, 4 logic subframes, represent with msis_sublogic_num.Require (Fig. 3, Fig. 4, Fig. 5) according to sub-frame allocation, in units of logic subframe, the address after sub-carrier interweaves is recalculated, and obtain the address after sub-frame allocation to realize sub-frame allocation function, idiographic flow is shown in Figure 21.Concrete distribution method comprises:
Sub-frame allocation mode one
When main business data belong to the first logical frame before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv; When main business data belong to the second logical frame before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength; Loglength is a logical frame length of main business data; When main business data belong to the 3rd logical frame before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2; When main business data belong to the 4th logical frame before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3;
Sub-frame allocation mode two
The address of the main business data after subband interweaves is designated as msis_addr_inv,
When main business data belong to the first logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv; When main business data belong to the first logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 1/4; When main business data belong to the first logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 1/2; When main business data belong to the first logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3/4;
When main business data belong to the second logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 1/4; When main business data belong to the second logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 1/2; When main business data belong to the second logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3/4; When main business data belong to the second logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength;
When main business data belong to the 3rd logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2; When main business data belong to the 3rd logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2+loglength × 1/4; When main business data belong to the 3rd logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2+loglength × 1/2; When main business data belong to the 3rd logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2+loglength × 3/4;
When main business data belong to the 4th logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2+loglength × 1/4; When main business data belong to the 4th logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2+loglength × 1/2; When main business data belong to the 4th logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2+loglength × 3/4; When main business data belong to the 4th logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3.
Sub-frame allocation mode three
Or comprise: the address of the main business data after subband interweaves is designated as msis_addr_inv,
When main business data belong to the first logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv;
When main business data belong to the first logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3/4;
When main business data belong to the first logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × (1+1/2);
When main business data belong to the first logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × (2+1/4);
When main business data belong to the second logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 1/4;
When main business data belong to the second logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength;
When main business data belong to the second logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × (1+3/4);
When main business data belong to the second logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × (2+1/2);
When main business data belong to the 3rd logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 1/2;
When main business data belong to the 3rd logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 5/4;
When main business data belong to the 3rd logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 2;
When main business data belong to the 3rd logical frame the 4th subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 11/4;
When main business data belong to the 4th logical frame the 1st subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3/4;
When main business data belong to the 4th logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3/2;
When main business data belong to the 4th logical frame the 3rd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 9/4;
When main business data belong to the 4th logical frame the 2nd subframe before sub-frame allocation, then the address msis_ram_addr of the main business data after sub-frame allocation equals msis_addr_inv+loglength × 3.
The realization of the sub-frame allocation function of 4.3 business description information.Here set forth with the realization of 2 of transmission mode 1 subbands, 4 subbands are similar.The address of business description information interleaved data is designated as sdis_addr_inv, and its span is in a superframe length of business description information, and the scope under transmission mode 1 is (0 ~ 13631).Because subband 1 and subband 2 enter sub-frame allocation module successively in units of logical frame, therefore in first logical frame, subband 1 address is (0 ~ 1703), subband 2 is (1704 ~ 3407), in second logical frame, subband 1 address is (3408 ~ 5111), subband 2 is (5112 ~ 6815), in 3rd logical frame, subband 1 address is (6816 ~ 8519), subband 2 is (8520 ~ 10223), in 4th logical frame, subband 1 address is (10224 ~ 11927), and subband 2 is (11928 ~ 13631).The realization of the sub-frame allocation function of business description information realizes respectively on 2 subbands, and the data of subband 1 and subband 2 are divided into 16 equal portions respectively, and be 16 logic subframes in this subband, the logic subframe identifying subband 1 and subband 2 according to the sequencing sdis_logic_num of data flow, is respectively (0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27), (4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31).
Require (Fig. 3, Fig. 4, Fig. 5) according to sub-frame allocation, in units of the logic subframe in logical frame, recalculate the address after business description information interweaves, obtain the address after sub-frame allocation, realize sub-frame allocation function, idiographic flow is shown in Figure 22.Specifically comprise:
The address of the business description data after interweaving is designated as sdis_addr_inv, the address sdis_ram_addr of the business description data after sub-frame allocation.
Sub-frame allocation mode one
Address sdis_ram_addr after sub-frame allocation equals sdis_addr_inv.
Sub-frame allocation mode two
When business description data belong to the first subband the 1st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 2nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 1/8; Sdloglength is the length of a business description data logical frame; When business description data belong to the first subband the 3rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 3/4; When business description data belong to the first subband the 4th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 7/8; When business description data belong to the first subband the 5th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 6th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 1/8; When business description data belong to the first subband the 7th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 3/4; When business description data belong to the first subband the 8th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 7/8; When business description data belong to the first subband the 9th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 7/8; When business description data belong to the first subband the 10th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 3/4; When business description data belong to the first subband the 11st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 1/8; When business description data belong to the first subband the 12nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 13rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 7/8; When business description data belong to the first subband the 14th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 3/4; When business description data belong to the first subband the 15th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 1/8; When business description data belong to the first subband the 16th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv;
When business description data belong to the second subband the 1st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the second subband the 2nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 1/8; When business description data belong to the second subband the 3rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 3/4; When business description data belong to the second subband the 4th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 7/8; When business description data belong to the second subband the 5th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the second subband the 6th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 1/8; When business description data belong to the second subband the 7th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 3/4; When business description data belong to the second subband the 8th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × 7/8; When business description data belong to the second subband the 9th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 7/8; When business description data belong to the second subband the 10th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 3/4; When business description data belong to the second subband the 11st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 1/8; When business description data belong to the second subband the 12nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the second subband the 13rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 7/8; When business description data belong to the second subband the 14th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 3/4; When business description data belong to the second subband the 15th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × 1/8; When business description data belong to the second subband the 16th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv.
Sub-frame allocation mode three
The address of the business description data after interweaving is designated as sdis_addr_inv;
When business description data belong to the first subband the 1st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 2nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1-1/8); When business description data belong to the first subband the 3rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (2-1/4); When business description data belong to the first subband the 4th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (3-3/8); When business description data belong to the first subband the 5th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 6th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1-1/8); When business description data belong to the first subband the 7th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (2-1/4); When business description data belong to the first subband the 8th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (3-3/8); When business description data belong to the first subband the 9th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × (1+1/8); When business description data belong to the first subband the 10th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 11st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1-1/8); When business description data belong to the first subband the 12nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (2-1/4); When business description data belong to the first subband the 13rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × (1/8-1); When business description data belong to the first subband the 14th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the first subband the 15th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1-1/8); When business description data belong to the first subband the 16th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (2-1/4);
When business description data belong to the second subband the 1st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv-sdloglength × (2+1/4); When business description data belong to the second subband the 2nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1/8-1); When business description data belong to the second subband the 3rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the second subband the 4th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1-1/8); When business description data belong to the second subband the 5th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1,4-2); When business description data belong to the second subband the 6th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1/8-1); When business description data belong to the second subband the 7th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the second subband the 8th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1-7/8); When business description data belong to the second subband the 9th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (3/8-3); When business description data belong to the second subband the 10th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1/4-2); When business description data belong to the second subband the 11st equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1/8-1); When business description data belong to the second subband the 12nd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv; When business description data belong to the second subband the 13rd equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (3/8-3); When business description data belong to the second subband the 14th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1/4-2); When business description data belong to the second subband the 15th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv+sdloglength × (1/8-1); When business description data belong to the second subband the 16th equal portions before sub-frame allocation, then the address sdis_ram_addr of the main business data after sub-frame allocation equals sdis_addr_inv.
The implementation method of the sub-frame allocation function of system parameters sub-frame allocation and business description information is similar, does not repeat them here.5. subcarrier maps
The function that this part realizes is that OFDM modulation does data encasement, according to subcarrier putting position and the sequence requirement of spectrum mode and each OFDM symbol.Under the effect of control logic, from the external RAM at MSC data place, CIC, the internal RAM at CPT data place, pilot generation unit, virtual subnet carrier generation unit is peeked, and the data of taken out data or generation are sent into No. 5 selectors, selector selects one group of data as final output, see Figure 23 according to the enable situation sending into signal.Export data and be filled into (Figure 24) on the subcarrier of each OFDM symbol according to sequencing successively, under 1024 idea carrier modes, the filling of next son carrier wave is carried out, similar process under 2048 idea carrier modes when data bulk reaches 1024.This part realizes sub-frame allocation function simultaneously, be different from without sub-frame allocation, when having sub-frame allocation function, the subcarrier that control logic selects the logic sub-frame data in MSC, CIC, CPT, pilot tone to carry out OFDM symbol according to the transmission sequencing of logic subframe is filled.
Subcarrier in standard is from (-1024 or-512), but IFFT computing is from subcarrier 0 is, so for the MSC be stored in RAM, CIC, the information such as CPT, all will fetch data from the sign-on of second OFDM frame, to adapt to this point.Figure 24 is 2048 subcarrier diagrams, and 1024 similar.(CDR standard has comparatively detailed description)
6. constellation point
System information is fixing adopts QPSK mapping mode, and business datum and business description information can adopt QPSK, 16QAM or 64QAM mapping mode.Bit stream after Bit Interleave is mapped as QPSK, 16QAM or 64QAM symbol stream and sends, and various sign map adds the power normalization factor, makes the average power of various sign map convergent.Normalization factor under miscellaneous service is as Figure 25.The mapped constellation points of QPSK, 16QAM or 64QAM is as Figure 26, Figure 27, Figure 28.7.OFDM modulates
FFT/IFFT processor achieves OFDM modulation, and it is the important module in native system.Therefore, design a kind of high speed, high-throughput, highly versatile FFT/IFFT processor become crucial.The FFT/IFFT processor of this programme design adopts single butterfly 4 road parallel organization, and not only can realize the FFT/IFFT conversion of and at 1024 at 2048, bit wide can also according to system requirements arbitrary disposition.Configurable FFT/IFFT processor of counting, test result indicates the correctness of design, and speed, throughput are far above the requirement of system.
The basic structure of 7.1 processors
The overall structure of FFT/IFFT processor as shown in figure 29, mainly comprises RAM buffer memory, address generating module, output order adjusting module, shift control module, index generation module, butterfly processing element and ROM.
FFT/IFFT processor adopts 4 tunnel concurrent operations, and real part and imaginary part store respectively, and this needs 8 block RAMs, in order to realize, to continuous continuable data flow input and output, all adopting ping-pong structure at input and output side, so have needs 32 block RAM altogether.Read/write address control module in Figure 29 mainly produces and writes data and the address from RAM sense data to RAM.Whole sequence module is selected the data in two groups of ping-pong rams, and carries out order adjustment.In order to improve precision, what this module adopted is block floating point algorithm, and index generation module, according to the result of calculation of butterfly unit, produces the maximal index after this grade of computing as final computing index.Shift module carries out displacement and selects, and every one-level operational data shares an index.Original position computing is have employed in this module.
The design of 7.2 butterfly units
Because design will realize 1024 and 2048 points simultaneously, 1024 adopt the computing of Pyatyi base 4, and 2048 needs Pyatyi bases 4 and one-level base 2 computing, radix-4 butterfly unit is as shown in Figure 30 (a).One-level Radix 4 Unit comprises two-stage base 2 unit, therefore can realize base 4 computing and base 2 computing uses a Radix 4 Unit jointly, which save resource, what adopt due to the design is input sequence, export the method for inverted order, so to the amendment of butterfly unit as shown in Figure 30 (b).Selector in Figure 30 (b) controls butterfly unit and completes base 4 or base 2 computing.When selector selects control to be 1, data enter from A, B, C, D, through first order base 2 computing and second level base 2 computing, complete base 4 computing; When selector selects control to be 0, data do not carry out base 2 calculation process of the second level, directly export operation result by selected cell, complete base 2 computing.
8. logic framing
Data after modulation and beacon are carried out windowing process and are exported according to certain sequencing by logic framing module, and this module specific implementation is as Figure 31.
9. system clock structure
Native system clock uses the clock setting of simplifying, and data input parsing module adopts 25MHZ clock, as the clk1 in Figure 32; Before subcarrier maps, (before p5 point) adopts 81.6 MHZ clocks, as the clk2 in Figure 32; Subcarrier mapping rear (after p5 point, comprising p5) adopts 816k clock, the clk3 in Figure 32; Base band adopts 3.264MHZ clock to radio frequency, the clk4 in Figure 32.The input of network interface that the clock setting of clk1 is compatible, clk2 adopts high clock rate can complete encoding tasks at a high speed, effective reduction system delay, clock rate and the systems baseband speed of clk3 match, and simplify OFDM symbol sub-carriers packing module, the design of OFDM modulation module.In a word, employing is simplified timing topology as above and is well met system requirements, and simplifies design.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature of disclosing in this manual or any combination newly, and the step of the arbitrary new method disclosed or process or any combination newly.

Claims (9)

1. a CDR modulation module, it is characterized in that, comprise data input parsing module, business datum passage, business description passage, system parameters passage, scattered pilot module, sub-carrier mapping module, constellation mapping block, OFDM modulation module, logic framing module, beacon module, physical layer signal frame module and base band to radio frequency modular converter; Wherein,
Data input parsing module has signal with business datum passage, business description passage, system parameters passage respectively and is connected;
Business datum passage, business description passage, system parameters passage have signal with sub-carrier mapping module and are connected;
Business datum passage comprises sub-carrier interleaving module; Business description passage comprises business description channel bit interleaving block; System parameters passage comprises system parameters channel bit interleaving block;
Sub-carrier mapping module, constellation mapping block, OFDM modulation module, logic framing module, physical layer signal frame module and base band are linked in sequence to radio frequency modular converter;
Scattered pilot module and sub-carrier mapping module have signal and are connected; Beacon module has signal with logic framing module and is connected.
2. a kind of CDR modulation module according to claim 1, it is characterized in that, data input parsing module adopts 25MHz clock, business datum passage, business description passage and system parameters passage adopt 81.6MHz clock, sub-carrier mapping module, scattered pilot module, constellation mapping block, OFDM modulation module, logic framing module, beacon module and physical layer signal frame module adopt 816kHz clock, and base band adopts 3.264MHz clock to radio frequency modular converter.
3. a kind of CDR modulation module according to claim 2, it is characterized in that, business datum passage comprises the business datum passage scrambling module, LPDC coding module, business datum passage map module, sub-carrier interleaving module and the business datum sub-frame allocation module that are linked in sequence.
4. a kind of CDR modulation module according to claim 2, it is characterized in that, business description passage comprises the business description passage scrambling module, business description passage convolutional encoder module, business description channel bit interleaving block, business description passage map module and the business description data burst distribution module that are linked in sequence.
5. a kind of CDR modulation module according to claim 2, it is characterized in that, system parameters passage comprises the generation system information module, system parameters passage convolutional encoder module, system parameters channel bit interleaving block, system parameters passage map module and the system parameters sub-frame allocation module that are linked in sequence.
6. a kind of CDR modulation module according to claim 3 or 4 or 5, it is characterized in that, sub-carrier interleaving module is used for the memory address after interweaving in 1 subband or 2 subbands or 4 subbands according to its business datum received of sub-carrier interleaving rule calculating and memory address is exported to business datum sub-frame allocation module;
Business description channel bit interleaving block is used for the memory address after interweaving in single subband according to its business description data received of Bit Interleave rule calculating and memory address is exported to business description data burst distribution module;
System parameters channel bit interleaving block is used for the memory address after interweaving in single subband according to its system parameter data received of Bit Interleave rule calculating and memory address is exported to system parameters sub-frame allocation module.
7. a kind of CDR modulation module according to claim 6, it is characterized in that, business datum sub-frame allocation module be used for according to the memory address of business datum sub-frame allocation rule and the business datum after interweaving calculate the business datum after sub-frame allocation memory address and according to described memory address storage service data;
Business description data burst distribution module be used for according to business description data burst allocation rule and the business description address data memory after interweaving calculate the business description data after sub-frame allocation memory address and according to described memory address storage service data of description;
System parameters sub-frame allocation module be used for according to system parameters sub-frame allocation rule and the system parameter data memory address after interweaving calculate the system parameter data after sub-frame allocation memory address and according to described memory address stores system parameters data.
8. a kind of CDR modulation module according to claim 7, it is characterized in that, sub-carrier mapping module comprises:
Business datum memory, adopt the dual-memory of ping-pong structure, each memory is for storing the business datum of a superframe after sub-frame allocation;
Business description data storage, adopt the dual-memory of ping-pong structure, each memory is for storing the business description data of a superframe after sub-frame allocation;
System parameters memory, adopt the dual-memory of ping-pong structure, each memory is for storing a system parameter data superframe after sub-frame allocation;
Gating unit, for exporting the data in above-mentioned three kinds of memories according to 1024 subcarriers or 2048 subcarrier mapping principle gatings, pilot data that described scattered pilot module exports and virtual carrier data stuffing be to the subcarrier of each OFDM symbol.
9. a sub-frame allocation module for CDR modulation module, is characterized in that,
For calculate according to the memory address of business datum sub-frame allocation rule and the business datum after interweaving the business datum after sub-frame allocation memory address and according to described memory address storage service data;
Or, for calculate according to business description data burst allocation rule and the business description address data memory after interweaving the business description data after sub-frame allocation memory address and according to described memory address storage service data of description;
Or, for calculate according to system parameters sub-frame allocation rule and the system parameter data memory address after interweaving the business description data after sub-frame allocation memory address and according to described memory address storage service data of description.
CN201410840083.5A 2014-12-30 2014-12-30 CDR modulation module and subframe distribution module thereof Pending CN104539568A (en)

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