CN101882970A - Address generating method and device for plurality of modes of interlacing and deinterlacing - Google Patents
Address generating method and device for plurality of modes of interlacing and deinterlacing Download PDFInfo
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Abstract
The invention discloses address generating method and device for a plurality of modes of interlacing and deinterlacing, belonging to the technical field of wireless communication. In the method, three times of data permutations are carried out in the interlacing and deinterlacing process in the manner of permutations and combinations. The method concretely comprises the following steps of: combining a second time of data permutation operation in the interlacing process into a row order written address of a first time of permutation; combining a third time of data permutation operation in the interlacing process into a column order read address of the first time of permutation; and completing the three times of permutations in the interlacing and deinterlacing process through the data writing and reading operations once. The invention effectively solves the problems of large overhead and inflexible configuration of the plurality of modes of interlacing and deinterlacing in a wireless communication system, can be used for designs of interleavers and deinterleavers of the standards, such as, IEEE 802.11n/a/g, 802.16d/e, HiperLAN/2, and the like and has excellent reference value and practical value.
Description
Technical field
The present invention relates to wireless communication technology field, be specifically related to a kind of multimodal interweaving and deinterleaving address generating method and device.
Background technology
For the memory characteristic of resisting actual channel and the error-correcting performance that improves chnnel coding, usually the transmission data are interweaved to disperse the burst structure of mistake in the digital communication.Diversity is to improve one of most important technology of communication system performance in fading channel, interweave wireless communication system is realized that frequency and space diversity have important function, in the root mean square time delay expansion is under the Rayleigh fading channel of 75ns, adopt the modulation of QPSK 1/2 code check, PER is that 1% o'clock system is approximately 5dB from the gain that interleaver obtains.
IEEE 802.11a/g/n, 802.16d/e and all to have adopted interleave depth in the wireless communication standard such as HiperLAN/2 be the block interleaved device of an OFDM symbolic coding bit number, IEEE802.11a/g wherein, 802.16d/e and carry out 2 secondary data displacements interweaving in the HiperLAN/2 standard altogether, 802.11n interweaves has increased secondary frequencies rotation displacement on the basis of preceding twice displacement.With k, i, j, r represent to replace data order preceding and after first, second and third time displacement respectively.Displacement for the first time is mapped on the non-conterminous data subcarrier adjacent bit, rule as shown in the formula:
i＝N
ROW(kmodN
COL)+floor(k/N
COL) (1)
K=0 wherein, 1 ..., N
CBPSS(i
SS)-1, N
CBPSS(i
SS) the every symbolic coding bit number of expression, N
COLThe columns of expression interleaver matrix is divided into 13,16 and 18 3 kind of pattern.N
ROW=N
CBPSS(i
SS)/N
COLThe line number of expression interleaver matrix.Mod and floor represent delivery and following rounding operation respectively.
Displacement for the second time makes adjacent coded-bit alternately be mapped to the high significance bit and the low order bit of constellation, to avoid existing of low reliability bits continuously.The rule as shown in the formula:
j＝s(i
SS)×floor(i/s(i
SS))+(i+N
CBPSS(i
SS) (2)
-floor(N
COL×i/N
CBPSS(i
SS)))mods(i
SS)
I=0 wherein, 1 ..., N
CBPSS(i
SS)-1, s (i
SS)=max (N
BPSCS(i
SS)/2,1) by the number of coded bits N of every subcarrier
BPSCC(i
SS) determine.
The frequency rotation is carried out in displacement for the third time, to reduce the correlation between the MIMO adjacent encoder data flow bit.The rule as shown in the formula:
r＝(j-(((i
SS-1)×2mod3+3×floor((i
SS-1)/3)) (3)
×N
ROT×N
BPSCS(i
SS))modN
CBPSS(i
SS)
J=0 wherein, 1 ..., N
CBPSS(i
SS)-1, N
ROTExpression frequency twiddle factor, its value is respectively 11 and 29 under 20MHz in the 802.11n standard and the 40MHz bandwidth mode.
The process of deinterleaving is followed successively by the inverse transformation process of the displacement that interweaves equally through the displacement of three secondary data.
The implementation method of interleaver mainly contains ROM and tables look-up and two kinds of address generations.For random interleaving or the complicated employing ROM look-up table usually that interweaves of replacing, this method principle is simple, but needs the read/write address of a large amount of ROM storage different modes.Realize for the rule general address generation method that adopts that interweaves, pare down expenses but need the design address generating device.802.11n interweave and have 36 kinds of different modes, the MIMO transceiver of 4 * 4 antennas needs 4 interleavers and 4 deinterleavers simultaneously, adopts the ROM look-up table to realize, needs the ROM expense of 680960 bits altogether, is unfavorable for that the SoC of system realizes.Generate the write-read address that interweaves if directly adopt the displacement formula to calculate, from the rule formula of above-mentioned three displacements as can be seen the computational process complexity be unfavorable for that hardware realizes.If three independently displacements of employing can simply design address generating device, but will introduce extra time-delay, and maximum delay are to be subjected to confirm in the MAC agreement that the timing demand of wrapping short interframe gap (SFIS) limits.Thereby, in order to satisfy the multi-mode of standards such as 802.11n, 802.16d to interweaving with deinterleaving, high-throughput, the requirement of low delay, the multi-mode that needs to propose a kind of low hardware complexity interweaves and the deinterleaving address generating method.
Summary of the invention
(1) technical problem that will solve
The multi-mode that the objective of the invention is to propose a kind of low hardware complexity interweaves and deinterleaving address generating method and device, to satisfy the requirement of standards such as 802.11n, 802.16d to interweaving with multi-mode, high-throughput and the low delay of deinterleaving.
(2) technical scheme
Be an aspect that achieves the above object, the invention provides a kind of multimodal interweaving and the deinterleaving address generating method, this method interweave with the deinterleaving process in carry out three secondary data displacements, the mode that adopts displacement to merge specifically comprises: the data replacement operation second time of interleaving process is merged in the capable sequential write address of displacement for the first time; The operation of data replacement for the third time of interleaving process is merged in the row sequential read address of displacement for the first time; One secondary data is write, three displacements that interweave with the deinterleaving process are finished in read operation.
In the such scheme, the described displacement second time is that adjacent coded-bit alternately is mapped to the high significance bit of constellation and the replacement process of low order bit, displacement for the second time directly is included in the write address that interweaves by the row order, and this write address is realized by the method that plot adds constant offset; The described frequency that is replaced into is for the third time rotated displacement, and displacement for the third time is included in reading in the address of the column major order that interweaves, and this is read the address and realizes by the method that the initial offset address is set and utilize the row plot to add constant offset.
In the such scheme, described being replaced into for the third time by being about to data writes interleaver matrix, reads by being about to data behind the rotary manipulation; This reads the address is that column major order is read, and the sequence address of will going rotation converts with the rotation of row sequence address.
In the such scheme, the write address of described deinterleaving, read the address and merge by described displacement and realize, the displacement of interleaving process is merged the read address of the write address of back generation as the deinterleaving process, read the write address of address after the displacement of interleaving process merged, realize that multimodal deinterleaving address generates as the deinterleaving process.
Be another aspect that achieves the above object, the invention provides a kind of multimodal interweaving and the deinterleaving address generating device, this device comprises:
Write address generates parts, is used for generating the multimodal write address that interweaves and need with the deinterleaving process;
Read the address and generate parts, be used for generating and multimodal interweaving read the address with the deinterleaving process needs; And
Constant generates parts, is used to generate the write address parts and reads the required constant of address unit.
In the such scheme, described write address generates parts and produce corresponding write address according to interlace mode when receiving Address requests; This write address adds the method that is offset the location by the base address to be realized; This write address is a line direction, thereby realize by increasing 1 counter certainly the base address; Determine the position of current base address in the minimum repetitive of replacement rule by the circulating register that the row, column direction is set, thereby determine corresponding write address skew location.
In the such scheme, the described address of reading generates parts and produces according to interlace mode when receiving Address requests and read the address accordingly, and this is read the address and realizes from the method that increases Ncol by initial address; This reads the address is column direction, and the next column that a row base register is used for mark current address column is set; After a column address had generated, the address assignment was the row base value, and the row plot is from increasing 1 simultaneously; When the row plot increased to (Ncol-1), the row plot was changed to 0; The initial read address generates parts by described constant and provides.
In the such scheme, described constant generation parts respectively interweave according to the mode select signal generation of importing or the address of deinterleaving pattern generates required constant; Mode select signal comprises: the sky branch coded data stream sequence number at mapping mode, system bandwidth, beacon and Data Labels and interlaced device or de-interleaving apparatus place, required constant comprises: constant offset, interleaver matrix row, column size and interleave depth.
Be another aspect that achieves the above object, the invention provides a kind of interweaving or de-interleaving apparatus, this device is made of generating device of the address, address control assembly, Data Control parts and single port RAM parts, wherein the write address that generates in Shu Ru data based this generating device of the address writes two single port RAM successively in turn, and reads address sense data successively from two single port RAM according to what generate in this generating device of the address.
In the such scheme, described generating device of the address comprises:
Write address generates parts, is used for generating the multimodal write address that interweaves and need with the deinterleaving process;
Read the address and generate parts, be used for generating and multimodal interweaving read the address with the deinterleaving process needs; And
Constant generates parts, is used to generate the write address parts and reads the required constant of address unit.
Be another aspect that achieves the above object, the invention provides a kind of interweaving or de-interleaving apparatus, this device is made of generating device of the address, Data Control parts and two-port RAM parts, wherein the write address that generates in Shu Ru the data based generating device of the address writes two two-port RAMs successively in turn, and reads address sense data successively from two two-port RAMs according to what generate in the generating device of the address.
In the such scheme, described generating device of the address comprises:
Write address generates parts, is used for generating the multimodal write address that interweaves and need with the deinterleaving process;
Read the address and generate parts, be used for generating and multimodal interweaving read the address with the deinterleaving process needs; And
Constant generates parts, is used to generate the write address parts and reads the required constant of address unit.
(3) beneficial effect
The multi-mode of this low hardware complexity provided by the invention interweaves and deinterleaving address generating method and device, can eliminate and separate the time-delay that interweaves that displacement is introduced, displacement merges back multimodal address generation and only adopts adder and circulating register to realize, and is simple in structure.With respect to traditional method for designing, the present invention has realized the interleaver and the deinterleaver of multi-mode, high-throughput under hardware spending still less, but and the interlace mode flexible configuration, effectively satisfied the requirement of standards such as 802.11n, 802.16d to interweaving with multi-mode, high-throughput and the low delay of deinterleaving.
Description of drawings
Fig. 1 is the replacement rule figure for the first time that interweaves;
Fig. 2 is the replacement rule figure for the second time that interweaves under BPSK, the QPSK mapping mode;
Fig. 3 is the replacement rule figure for the second time that interweaves under the 16QAM mapping mode;
Fig. 4 is the replacement rule figure for the second time that interweaves under the 64QAM mapping mode;
Fig. 5 is the replacement rule figure for the third time that interweaves;
Fig. 6 is that the displacement that interweaves that proposes among the present invention merges schematic diagram;
Fig. 7 be among the 802.11n under the 20MHz bandwidth MCS be the write address table of displacement after merging that interweaved in 7 o'clock;
Fig. 8 be among the 802.11n under the 20MHz bandwidth MCS be that the displacement that interweaved in 7 o'clock is read address table after merging;
Fig. 9 is that propose among the present invention multimodal interweaves or deinterleaving address generating device structured flowchart;
Figure 10 is the multi-mode write address generating structure figure after the displacement that interweaves of embodiment 1 merges among the present invention;
Figure 11 is that embodiment 1 multi-mode of displacement after merging that interweave read address generating structure figure among the present invention;
Figure 12 is the multi-mode write address generating structure figure after the displacement that interweaves of embodiment 2 merges among the present invention;
Figure 13 is that embodiment 3 interweaves or the structured flowchart of de-interleaving apparatus among the present invention;
Figure 14 is that embodiment 4 interweaves or the structured flowchart of de-interleaving apparatus among the present invention.
Embodiment
In order to further specify multimodal the interweaving and deinterleaving address generating method and device that the present invention proposes, describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
The multi-mode that the invention provides a kind of low hardware complexity interweaves and deinterleaving address generating method and device, and provides a kind of multi-mode address generating device implementation based on adder and circulating register based on the displacement merging.
The process that the displacement that interweaves merges is as follows:
The replacement operator second time that (a) will interweave merges in the write address of the replacement operator first time;
The replacement operator for the third time that (b) will interweave merges to reading in the address of replacement operator for the first time;
The line direction that is replaced into for the third time of interleaving process rotates, and be the row orders and read the address, thereby line displacement need be converted to the column position of reading in the address table.Rotation amount rot_offset through type 4 calculates, postrotational initial column plot col_base_ini, line position row_cnt_ini and read first address addr_r_ini under the different interleaving pattern according to formula 5,6, and 7 convert.
N wherein
ROTThe expression twiddle factor, N
BPSCS(i
SS) expression i
SSThe number of coded bits of each subcarrier in the spatial data of road.
col_base_ini＝floor(rot_offset/N
ROW)+1 (5)
row_cnt_ini＝rot_offsetmodN
ROW (6)
addr_ini＝col_base_ini+row_cnt_ini×N
COL-1 (7)
Because deinterleaving is replaced into the inverse permutation process that interweaves, thereby only need the read address of the write address that interweaves after the displacement merging as deinterleaving, the address of reading that will interweave realizes promptly that as the write address that interweaves the deinterleaving address generates.
The multi-mode address generating device that the present invention proposes mainly comprises the write address generation module, reads address generation module and constant selection module three parts.
Write address generation module: produce corresponding write address according to interlace mode when being used to receive Address requests.Write address adds the method that is offset the location by the base address to be realized.Write address is a line direction, thereby realize by increasing 1 counter certainly the base address.Corresponding different interlace modes, the skew location difference of write address.In system is that BPSK or QPSK modulation system hour offset location are 0; When the system modulation mode is 16QAM, the skew location have 0 and ± N
COLThree kinds of situations; When the system modulation mode is 64QAM, the skew location has 0, ± N
COLAnd ± (2 * N
COL) five kinds of situations.Determine the position of current base address in the minimum repetitive of replacement rule by the circulating register that the row, column direction is set, thereby determine corresponding write address skew location.
Read the address generation module: produce according to interlace mode when being used to receive Address requests and read the address accordingly.Read the address and increase N certainly by initial address
COLMethod realize.Reading the address is column direction, thereby the next column that a row base register is used for mark current address column is set.After a column address had generated, the address assignment was the row base value, and the row plot is from increasing 1 simultaneously.When the row plot increases to (N
COL-1) time, the row plot is changed to 0.When realizing, hardware will need initial column plot col_base_ini, the line position row_cnt_ini of interlace mode and read first address addr_r_ini to be made into table.
Constant is selected module: be used for according to the required constant of mode producing reading, writing address that interweaves.The mode select signal of importing this module comprises mapping mode, system bandwidth, the sky at beacon and Data Labels and interleaver place are divided coded data stream sequence number, and the constant of generation comprises the address offset constant of each interlace mode, the row, column size of interleaver matrix, interleave depth.This module realizes by selector switch.
Fig. 1 has provided IEEE 802.11a/g/n, the replacement rule first time of the block interleaved that generally adopts in the standards such as 802.16d/e and HiperLAN/2.Data write interleaver matrix successively by the direction of arrow of write data order among Fig. 1, press read data arrow indication column direction sense data successively then.Fig. 2,3,4 is the second time replacement rule of above-mentioned block interleaved under system's different mappings mode, data write interleaver matrix successively by column direction, press in the form behind the arrow swap data position, read interleaver matrix successively by column direction.Fig. 2 represents BPSK and the following replacement rule for the second time of QPSK mapping mode, and data do not have place-exchange.Fig. 3 represents the replacement rule second time under the 16QAM mapping mode, Fig. 4 represents the replacement rule second time under the 64QAM mapping mode, data have been carried out the place-exchange operation, make adjacent coded-bit alternately be mapped to the high significance bit and the low order bit of constellation, to avoid existing of low reliability bits continuously.Fig. 5 is the displacement for the third time of block interleaved among the 802.11n, and data write interleaver matrix successively by line direction, by the direction of arrow among the figure data is carried out whole circulation rotation displacement, then by row sense data successively.
Fig. 6 interweaves among the present invention with replacing the schematic diagram that merges, and is about to displacement for the second time and merges in the capable sequential write address of the displacement first time, and displacement for the third time merges in the row sequential read address of displacement for the first time.Realize the displacement of three secondary data by once writing read operation, eliminated repeatedly extra time-delay of displacement and the expense of the RAM that will interweave and be reduced to 1/3 of separation method of replacing.802.11n under the middle 20MHz bandwidth MCS be the write address that interweaves after displacement in 7 o'clock merges as shown in Figure 7, write address is followed successively by 0,27,15 in proper order ....Read the address as shown in Figure 8, reading sequence of addresses is 0,13,26 ....The reading when write address that Fig. 8 provides rotates for no frequency then needs calculate initial column plot col_base_ini, the line position row_cnt_ini that reads the address and read first address addr_r_ini by the method described in the summary of the invention if frequency is rotated in the address.
The present invention proposes multimodal interweave with deinterleaving address generating device structured flowchart as shown in Figure 9, comprise write address generation module 101, read address generation module 102 and constant and select module 103.
Write address generation module 101 produces corresponding write address according to corresponding interlace mode after being used to receive the write address request signal.Reading address generation module 102 is used to receive read behind the address request signal to produce according to corresponding interlace mode and reads the address.Constant is selected module 103 to be used for producing and is write, reads the constant that the address needs, and comprises skew location ± N
COL, ± (2 * N
COL), read address initial column plot col_base_ini, line position row_cnt_ini, read first address addr_r_ini, interleaver matrix line number N
ROWAnd interleave depth N
CBPSS(i
SS) totally 9.
Figure 10 is the implementation structure block diagram of write address generation module 101.Constant selects module 201 to be used to produce the required constant of write address generation module, realizes by selector switch.The constant of 201 outputs is given selector 203 and 204.202 and 205 are circulating register, be used for determining the position of current address at the minimum repetitive of write address rule, to be among the 802.11n MCS under the 20MHz bandwidth be 7 o'clock the minimum repetitive of write address rule to the nine palace lattice in the upper left corner among Fig. 7, thereby get final product for circulating register row_flag_64qam and the col_flag_64qam that the 64QAM mapping mode only need be provided with two 3 bits.For the 16QAM mapping mode, the ranks sign row_flag_16qam and the col_flag_16qam of two 1 bits of design.Because the data replacement free of data swap operation second time of BPSK and QPSK mapping mode, thereby side-play amount is always 0.Above-mentioned circulating register also can replace by counter when realizing, but adopts the counter expense relatively large.Shift register 202 and 205 switch controlling signals as selector 203,204, the output offset constant is given selector 206.The system map pattern is exported final constant offset and is given adder 210 as the switch controlling signal of selector 206.The mode that write address adopts the base address to add constant offset produces, and the base address produces by counter 207, when receiving that Address requests counter 207 begins counting.Adder 210 is used to realize base address and constant offset addition, and the address value of output is given selector 211.Selector 211 is used for control and generates first 0 write address, and the final write address that produces outputs to register 212 and deposits.
Figure 11 is an implementation structure block diagram of reading address generation module 102.Constant is selected module 301 to be used to produce and is read the required constant in address, and module 301 and aforementioned modules 201 all are included in aforementioned constant and select in the module 103.Counter 302 is used for reading the row plot counting of address, and the initial value of counter 302 is the 301 initial column plot col_base_ini that produce, and the row plot counting that counter 302 produces outputs to selector 305.Adder 303 is used to realize that the address is from increasing N
COLOperation is because N under the different mode
COLVary in size, thereby occurrence selects module 301 to determine by constant.Counter 304 is used for the line position counting of current address at permutation matrix, and selector 305 control address assignment are the row base value after a column address has produced.Selector 306 is used for control and produces and to read first address, and the final address of reading that produces outputs to register 308 and deposits.
Described abovely be the address generating method that interweaves and the specific embodiment of device, reciprocal owing to interweave with the deinterleaving process, thereby the enforcement of deinterleaving address generating method and device is consistent with interleaving process, only the write address module 101 that interleaving process need be produced is as the address module of reading of deinterleaving, get final product reading the write address module of address generation module 102 as deinterleaving, other specific implementation process are consistent with the above-mentioned implementation process that interweaves.
Figure 12 is the another kind of implementation method of write address generation module of interweaving.401 and 404 for shift register is respectively applied for the write address constant offset of controlling under 64QAM and the 16QAM mapping mode, as the switch controlling signal of selector 402 and 405. Selector 402 and 405 produces constant offset and outputs to adder 407 and 406 respectively.Counter 403 is used to produce the base address, owing to replace the free of data swap operation second time of BPSK and QPSK, thereby the write address under BPSK and the QPSK mapping mode is directly produced by counter 403.Write address under 64QAM and the 16QAM pattern is generated by the mode that the skew location adds the base address, and adder 406 and 407 is respectively applied for the summation of skew location and base address, and OPADD is input to selector 409 and 408 respectively.Selector 408 and 409 is used to produce the first write address of 64QAM and 16QAM pattern, and each write address outputs to selector 410.Selector 410 is used for according to the final write address of system map pattern output.
Described above for displacement merges interweave a kind of implementation method of write address of back multi-mode, for the deinterleaving process, this embodiment is the enforcement of reading the address.
Figure 13 is the structured flowchart of interweaving of the embodiment of the invention 3 or de-interleaving apparatus.
In Figure 13, interweave or deinterleaving address generating device 502 according to input interweave or deinterleaving pattern OPADD to address control unit 503.502 constituting herein by the address generating device among aforesaid embodiment 1 or the embodiment 2.
Recording controller 501 is used for the interleaving data of input is outputed to single port RAM0 and single port RAM1 by certain time sequence, respectively 505 and 504 in the corresponding diagram.Recording controller needs to produce 505 and 504 chip selection signal, read-write control signal simultaneously.And send Address requests to address control unit 503.
Address control unit 503 is used for producing address request signal to generating device of the address, and distributes to 504 and 505 respectively according to the address that generating device of the address 502 produces.
Single port RAM0 and single port RAM1 are used to realize interleaving data table tennis read-write operation, eliminate the wait time-delay of the continuous symbol data that interweave, and make system realize the data flow aquation.The single port RAM degree of depth is 648, and data bit width can be adjusted according to system's soft-decision demand.Interweave or deinterleaving after data output to recording controller 501, unify the output of control data and output effectively by recording controller.
Adopt single port RAM in the present embodiment, can reduce overhead.But single port RAM has only a cover address, thereby introduces a simple address control module.Generating device of the address is to interweave or key that de-interleaving apparatus is realized, adopts interweaving and the deinterleaving generating device of the address that the present invention proposes, can realize multimodal interweaving and deinterleaving under low-down hardware spending.Can be widely used in 802.11a/g/n, in the communication system of standards such as 802.16d/e and HiperLAN/2 based on IEEE.
Figure 14 is that embodiment 4 interweaves or the structured flowchart of de-interleaving apparatus among the present invention.
In Figure 14, interweave or deinterleaving address generating device 602 according to input interweave or deinterleaving pattern OPADD to two-port RAM 0 and two-port RAM 1,603,604 in the corresponding diagram respectively.In this example interweave or deinterleaving address generating device 602 is made of the address generating device among previous embodiment 1 or the embodiment 2.
Recording controller 601 is used for producing the read/write address request signal according to the input interleaving data.The interleaving data of input is outputed to two-port RAM 0 and two-port RAM 1 by certain time sequence, and produce the chip selection signal and the read-write control signal of dual-port 603 and 604.
Two-port RAM 0 and two-port RAM 1 are used to realize interleaving data table tennis read-write operation, eliminate the wait time-delay of the continuous symbol data that interweave, and make system realize the data flow aquation.The two-port RAM degree of depth is 648, and data bit width can be adjusted according to system's soft-decision demand.Interweave or deinterleaving after data output to recording controller 601, unify the output of control data and output effectively by recording controller.
Owing to adopt two-port RAM to interweave or the writing of deinterleaved data, read operation, two-port RAM has two cover addresses, thereby has lacked the address control module with respect to aforesaid embodiment 3 in the present embodiment.Interweave or the address of writing, read that the deinterleaving generating apparatus produces is directly inputted to two-port RAM.Adopt two-port RAM bigger, but can simplify control logic with respect to single port RAM hardware spending.Further, also can only adopt a slice two-port RAM in the present embodiment, but can increase the wait time-delay that interweaves like this, can not realize the streamlined that system data is handled.
Above-mentioned 4 embodiment describe propose among the present invention multimodal in detail and interweave and deinterleaving address generating method and device, in embodiment 3 and embodiment 4, enumerated of the present invention interweave with the deinterleaving address generating device interweaving with de-interleaving apparatus in application.Adopt VerilogHDL to describe to embodiment 3, and carried out FPGA and ASIC realizes, it satisfies interweaving and the deinterleaving requirement under whole 77 kinds of modulation coding modes of 802.11n the checking presentation of results.In Quartus II 8.0, use the maximum clock frequency fmax of Stratix II EP2S60F672C3 device synthesis to be 327.23MHz.When data bit width was 3, the combination logic resource of use was 210, and register resources is 163, and storage resources is 2 * 648 * 3 bits.Its circuit area is 0.0667mm2 under SMIC (SMIC integrated circuit Manufacturing Co., Ltd) 0.13um1.08V 1P6M CMOS technology, maximum operating frequency reaches 400MHz, 160MHz with the 400MHz operating frequency under its power consumption be respectively 4.2mW and 10.8mW.
Should be noted that at last: the above only is preferred embodiment of the present invention, should not be regarded as the restriction of protection range of the present invention.According to the description of technical scheme of the present invention and preferred embodiment thereof, those skilled in the technology concerned can make various be equal to change or replacements.Therefore, within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc. and all should belong within the claim scope of the present invention.
Claims (12)
1. multimodal interweaving and the deinterleaving address generating method, it is characterized in that, this method interweave with the deinterleaving process in carry out three secondary data displacements, the mode that adopts displacement to merge specifically comprises: the data replacement operation second time of interleaving process is merged in the capable sequential write address of displacement for the first time; The operation of data replacement for the third time of interleaving process is merged in the row sequential read address of displacement for the first time; One secondary data is write, three displacements that interweave with the deinterleaving process are finished in read operation.
2. multi-mode according to claim 1 interweaves and the deinterleaving address generating method, it is characterized in that, the described displacement second time is that adjacent coded-bit alternately is mapped to the high significance bit of constellation and the replacement process of low order bit, displacement for the second time directly is included in the write address that interweaves by the row order, and this write address is realized by the method that plot adds constant offset; The described frequency that is replaced into is for the third time rotated displacement, and displacement for the third time is included in reading in the address of the column major order that interweaves, and this is read the address and realizes by the method that the initial offset address is set and utilize the row plot to add constant offset.
3. multi-mode according to claim 1 interweaves and the deinterleaving address generating method, it is characterized in that, described being replaced into for the third time by being about to data writes interleaver matrix, reads by being about to data behind the rotary manipulation; This reads the address is that column major order is read, and the sequence address of will going rotation converts with the rotation of row sequence address.
4. multi-mode according to claim 1 interweaves and the deinterleaving address generating method, it is characterized in that, the write address of described deinterleaving, read the address and merge by described displacement and realize, the displacement of interleaving process is merged the read address of the write address of back generation as the deinterleaving process, read the write address of address after the displacement of interleaving process merged, realize that multimodal deinterleaving address generates as the deinterleaving process.
5. multimodal interweaving and the deinterleaving address generating device, it is characterized in that this device comprises:
Write address generates parts, is used for generating the multimodal write address that interweaves and need with the deinterleaving process;
Read the address and generate parts, be used for generating and multimodal interweaving read the address with the deinterleaving process needs; And
Constant generates parts, is used to generate the write address parts and reads the required constant of address unit.
6. multimodal interweaving and the deinterleaving address generating device according to claim 5 is characterized in that, described write address generates parts and produce corresponding write address according to interlace mode when receiving Address requests; This write address adds the method that is offset the location by the base address to be realized; This write address is a line direction, thereby realize by increasing 1 counter certainly the base address; Determine the position of current base address in the minimum repetitive of replacement rule by the circulating register that the row, column direction is set, thereby determine corresponding write address skew location.
7. multimodal interweaving and the deinterleaving address generating device according to claim 5, it is characterized in that, the described address of reading generates parts and produces according to interlace mode when receiving Address requests and read the address accordingly, and this is read the address and realizes from the method that increases Ncol by initial address; This reads the address is column direction, and the next column that a row base register is used for mark current address column is set; After a column address had generated, the address assignment was the row base value, and the row plot is from increasing 1 simultaneously; When the row plot increased to (Ncol-1), the row plot was changed to 0; The initial read address generates parts by described constant and provides.
8. multimodal interweaving and the deinterleaving address generating device according to claim 5 is characterized in that, described constant generation parts respectively interweave according to the mode select signal generation of importing or the address of deinterleaving pattern generates required constant; Mode select signal comprises: the sky branch coded data stream sequence number at mapping mode, system bandwidth, beacon and Data Labels and interlaced device or de-interleaving apparatus place, required constant comprises: constant offset, interleaver matrix row, column size and interleave depth.
9. one kind interweaves or de-interleaving apparatus, it is characterized in that, this device is made of generating device of the address, address control assembly, Data Control parts and single port RAM parts, wherein the write address that generates in Shu Ru data based this generating device of the address writes two single port RAM successively in turn, and reads address sense data successively from two single port RAM according to what generate in this generating device of the address.
10. according to claim 9 interweaving or de-interleaving apparatus is characterized in that, described generating device of the address comprises:
Write address generates parts, is used for generating the multimodal write address that interweaves and need with the deinterleaving process;
Read the address and generate parts, be used for generating and multimodal interweaving read the address with the deinterleaving process needs; And
Constant generates parts, is used to generate the write address parts and reads the required constant of address unit.
11. one kind interweaves or de-interleaving apparatus, it is characterized in that, this device is made of generating device of the address, Data Control parts and two-port RAM parts, wherein the write address that generates in Shu Ru the data based generating device of the address writes two two-port RAMs successively in turn, and reads address sense data successively from two two-port RAMs according to what generate in the generating device of the address.
12. according to claim 11 interweaving or de-interleaving apparatus is characterized in that, described generating device of the address comprises:
Write address generates parts, is used for generating the multimodal write address that interweaves and need with the deinterleaving process;
Read the address and generate parts, be used for generating and multimodal interweaving read the address with the deinterleaving process needs; And
Constant generates parts, is used to generate the write address parts and reads the required constant of address unit.
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