CN106817198A - The intertexture de-interweaving method of Turbo decodings suitable for LTE system - Google Patents
The intertexture de-interweaving method of Turbo decodings suitable for LTE system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6525—3GPP LTE including E-UTRA
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0066—Parallel concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Abstract
The invention discloses a kind of de-interleaving interleaving design scheme of the turbo decoders for being applied to LTE system.Decoding data is handled as follows first, is grouped to receiving data according to different coding data length, each group of data are respectively processed, most 16 circuit-switched data parallel processings, can so greatly reduce decoding time, improve the throughput of decoding.Intertexture de-interleaving technique is used for digital independent and write-in.Interleaved transforms read data using column address conversion, then complete to interweave using row mapping.Deinterleave conversion and change the conversion of row data using row inverse mapping, converted using column address, write-in data complete to deinterleave conversion.The present invention determines the line translation of interleave and deinterleave by shift register using the correlation between row data.Relative to prior art, several critical datas are only calculated, without individually calculating each row of data mapping table, save resource, saved power consumption.
Description
Technical field
The invention belongs to wireless communication technology field, more particularly to a kind of intertexture of the decodings of the Turbo suitable for LTE system
Deinterleave method for designing.
Background technology
1993, in IIC (Intemational Information Conference) conference, C.Berrou,
A.Glavieux and P.Thitimajshima proposes the concept of Turbo code.The proposition of Turbo code has landmark meaning,
Extensive concern and the research of scholars are caused with its excellent properties limited close to Shannon.Turbo code be actually it is a kind of simultaneously
Row cascade convolution code (Parallel Concatenated Convolutional Codes).It is dexterously by two simple point
Amount code constructs the long code with pseudo-random characteristics by pseudo random interleaver parallel cascade, and by two groups it is soft enter/it is soft go out
(SISO) successive ignition is carried out between decoder and realizes pseudorandom decoding.Due to performance considerably beyond other coding staffs
Formula, Turbo code is gradually applied in the real-time communication systems such as satellite communication, network, broadcast, personal communication.Current Turbo
Code is as the channel coding standard of 3G and 4G.
In order to reduce decoding delay, Turbo decoders employ data packing technique.But the intertexture of data is deinterleaved and needed
To calculate in real time, occupy larger resource while also improving extra power consumption.
The content of the invention
In order to solve problems of the prior art, a kind of de-interleaving interleaving scheme especially set out is applied to the present invention
In LTE system turbo decodings, while new departure ensure that intertexture speed and accuracy, hardware spending and work(are greatly reduced
Consumption,.
According to an aspect of the present invention, there is provided a kind of intertexture de-interweaving method of the Turbo code suitable for LTE system, its
It is characterised by, including：
Input data is divided at least one set, according to institute's packet count, code length and the system that interweaves in the case of point multigroup
Number determines initialization and the circulating register number of circulating register, and initialization includes determining circulating register
In data and order；
Interweave and read data, the storage sequence number according to initialization calculates the position of data interlacing column address, calculate corresponding
Parameter, then according to storage sequence number selection circulating register, further according to the parameter, calculates circulating register displacement
Length, the data in register after displacement are used for row and interweave；
Write-in data are deinterleaved, for the data that interweave according to the corresponding relation of row address, reflection is incident upon normal sequence, then
Calculate the column address write-in for interweaving.
Further, described at least one set of for 1 group, 4 groups, 8 groups or 16 groups, packet count correspond to the length of shift register
Degree.
Further, the cyclic shift length of circulating register determines by the first every trade mapping address, the first row
The corresponding shift register address of row mapping address is cyclic shift value.
Further, formula f (x) of the intertexture is：
F (x)=(f0x+f1x2) mod N,
Wherein N is data length, f0And f1It is interleave parameter, the normal sequence of addresses of x correspondences；
Corresponding interleaved transforms are：
F (x+d)=(f (x)+g (x)) mod N
G (x)=(f0d+2f1dx+f1d2)mod N
G (x+d)=(g (x)+delta) mod N
Delta=2d2f1mod N
Wherein g (x) and delta is intermediate variable, and d is step-length.
After packet, block length is K, and packet count is M, understands that the column interleaving address values do not gone together are according to above-mentioned formula
Unanimously, same rank addresses interweave and are divided into forward recursion and backward recursion, step-length d=1.
Column address forward recursion formula is：
fcol(x+1)=(fcol(x)+gcol(x))mod K
gcol(x)=(f0+2f1x+f1)mod K
gcol(x+1)=(gcol(x)+deltacol)mod K
deltacol=2f1mod K
Column address backward recursion formula is
fcol(x+1)=(fcol(x)+g′col(x))mod K
g′col(x)=K-gcol(x)mod K
Further, when for 4 groups when, the relation of the mapping is fixed, the circulating register number be 1, circulation
The digit of shift register cyclic shift determines according to the corresponding mapping relations of the first row.
Further, when to be grouped into 8,
According to formula g (x)=(f0+2f1x+f1K it is two kinds of situations that) %M is divided to, and K is every group of length, and M is 8；
The first situation, f1It is 4 integral multiple, then row mapping relations are fixed, is present in a cyclic shift deposit
In device；
Second situation, f1Can not be divided exactly by 4, the circulating register is 2 each, it is odd number that sequence number x is stored respectively
Data, and sequence number x for even number data.
Further, when for 8 groups when,
When packet count is 16, according to formula grow(x)=(f0+2f1x+f1K) mod M points is three kinds of situations, K
It is every group of length, M is 16；
The first situation, f1It is 8 integral multiple, row mapping relations are fixed, and the circulating register number is
1；
Second situation, f1It is 4 integral multiple, the circulating register number is 2, it is strange that sequence number x is stored respectively
Several data, and sequence number x is the data of even number；
The third situation, f1Can not be divided exactly by 4, the circulating register number, mod (x, 4)=0 is corresponded to respectively,
1,2,3 storage condition.
From above-mentioned technical proposal as can be seen that being compared with current row address mapping, new departure need not be added and subtracted
Calculate, it is only necessary to be circulated displacement in the circulating register for having initialized and can obtain corresponding mapping result.Reduce
Hardware spending and power consumption.
Brief description of the drawings
Fig. 1 is the embodiment of the present invention Turbo decoders interleave and deinterleave block diagram, wherein address suitable for LTE system
Generator includes the calculating of row address and column address；
Fig. 2 a and 2b are respectively embodiment of the present invention column address in column interleaving address computation block diagram LTE system and change
For calculating process figure and intermediate variable gcolThe calculating process figure of (x)；
Fig. 3 a, 3b and 3c are respectively the embodiment of the present invention first in row interleave parameter computing block diagram LTE system
The calculating figure of every trade mapping address, intermediate variable gcolThe calculating process figure and intermediate variable forward_row of (x) and
The calculating process figure of backward_row；
Fig. 4 is embodiment of the present invention row intertexture mapping diagram suitable for LTE system.
Specific embodiment
Core concept of the invention is calculated to simplify to interweave with deinterleaving, and reduces hardware spending, reduces power consumption.It is based on
This, the embodiment of the present invention provides a kind of turbo decoder interleaving schemes suitable for LTE system, enters in terms of the storage of design
Row is following to be set：Input data is grouped first, according to intertexture coefficient, code length and block length determine that cyclic shift is deposited
The initialization of device and circulating register number.
The reading of data is divided into order reads and interweaves and read two kinds of situations, for the first situation, data according to suitable
Sequence reads, and not through line translation, is directly output to computing unit.For second situation, calculated according to sequence number interweave first
The position of column address, calculates corresponding parameter, then selects circulating register according to sequence number, and further according to parameter, calculating is followed
Ringed shift register shift length, the data in register after displacement are used for row and interweave.The reading of so data completes friendship
Knit process.
In two kinds of situation, a kind of situation is to be sequentially written in for the write-in of data, and another situation is to deinterleave write-in.Correspondence the
A kind of situation, data need not be mapped, in writing corresponding address in sequence.Situation in correspondence second, interweaves first
Data reflect and are mapped to normal sequence according to the corresponding relation of row address.Calculate the column address write-in of intertexture again afterwards, complete number
According to deinterleaving convert.Wherein row mapping relations are also to be obtained by circulating register cyclic shift.
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in further detail.
Three road decoding datas being input into terms of data processing, are grouped by reference picture 1 first, will be per length all the way
For the data of N are divided into every group of length of M groups for K.M is packet count, and span is [1 48 16].f0And f1It is interleave parameter, root
Be given by LTE specification according to different data lengths.
Lothrus apterus interleaving formula is in Turbo code in LTE system：
F (x)=(f0x+f1x2)mod N
Calculated to reduce multiplication, above-mentioned multiplication formula can be rewritten as recursion additional calculation, and formula is
F (x)=(f0x+f1x2)mod N
F (x+d)=(f (x)+g (x)) mod N
G (x)=(2f1dx+f0d+f1d2)mod N
G (x+d)=(g (x)+delta) mod N
Delta=2d2f1 mod N
Wherein g (x) and delta is intermediate variable, and d is step-length.
Reference picture 2a and 2b, packet rank rear address computation formula are fcol(x)=(f0x+f1x2) mod K, the row of next line
Address understands f by formulacol(x+K)=(f0(x+K)+f1(x+K)2) mod K=fcol(x).By above-mentioned formula it can be seen that
The column address value do not gone together is identical.
Column address is calculated and can be iterated calculating by two additions, and Fig. 2 a give column address iterative process,
For forward direction column address, selecting switch is 1, fcol(x+1)=(fcol(x)+gcol(x))mod K.For backward column address, selection
Switch is 0, fcol(H-x-1)=(fcol(H-x)+gcol(H-x)) mod K, wherein H are backward initial position.Initial value is
fcol(0)=0.
fcol(H)=(f0H+f1H2)mod K
Fig. 2 b give intermediate variable gcolThe calculating process of (x).For forward direction median, step-length d=1, selecting switch are made
It is 1, gcol(x+1)=(gcol(x)+(2f1mod K))mod K.For backward median, step-length d=-1 is made, selecting switch is
0, gcol(H-x-1)=(gcol(H-x)+K-(2f1mod K))mod K.Wherein initial value is
gcol(0)=f0+f1
gcol(H)=K- ((2f1H-f1+f0)mod K)
Reference picture 3a, 3b and 3c, row mapping address are calculated and can be iterated calculating by three additions, and Fig. 3 a give
The calculating of the first every trade mapping address, for forward direction column address, selecting switch is 1, frow(x+1)=(frow(x)+grow(x))
mod M.For backward column address, selecting switch is 0, frow(H-x-1)=(frow(H-x)+grow(H-x))mod M.Wherein just
Initial value is
frow(0)=0
frow(H)=floor ((f0H+f1H2)/K)mod M
Fig. 3 b give intermediate variable gcolThe calculating process of (x).For forward direction median, step-length d=1, selecting switch are made
It is 1, grow(x+1)=(grow(x)+forward_row)mod M.For backward median, step-length d=-1 is made, selecting switch is
0, gcol(H-x-1)=(gcol(H-x)+K-(2f1mod K))mod K.Wherein initial value is
gcol(0)=floor ((f0+f1)/K)mod M
gcol(H)=M- (floor ((2f1H-f1+f0)/K))mod M
Fig. 3 c give the calculating process of intermediate variable forward_row and backward_row.For forward direction median,
Selecting switch is 1, forward_row=(forward_row+forward_c_in) mod M.For backward median, selection
It is 0, backward_row=(backward_row+backward_c_in) mod M to switch.Wherein initial value is
Forward_row=(floor (2f1/K))mod M
Backward_row=M- (floor (2f1/K))mod M-1
Reference picture 4, ensures that block length K can be divided exactly by 4, then have the i.e. g (x) of delta=0 to keep not in a packet first
Become.Below to packet count for 4,8,16 situation is described respectively.
When packet count is 4, g (x) can be rewritten as g (x)=(f0+f1K) %M, then row mapping relations are fixed
, there may be in a circulating register, determine circulating register according to the corresponding mapping relations of the first row
The digit of cyclic shift.
When packet count is 8, according to formula g (x)=(f0+2f1x+f1K) %M can be divided into two kinds of situations, first
The situation of kind, f1It is 4 integral multiple, then row mapping relations are fixed, in there may be a circulating register.Second
Situation, f1Can not be divided exactly by 4, then need two registers to store the situation that sequence number x is odd number respectively, and sequence number x is even number
Situation.
When packet count is 16, according to formula g (x)=(f0+2f1x+f1K) %M can be divided into three kinds of situations, first
The situation of kind, f1It is 8 integral multiple, then row mapping relations are fixed, in there may be a circulating register.Second
Situation, f1It is 4 integral multiple, then needs two registers to store the situation that sequence number x is odd number respectively, and sequence number x is even number
Situation.The third situation, f1Can not be divided exactly by 4, then need four circulating registers, mod (x, 4)=0,1 is corresponded to respectively,
2,3 situation.
By such scheme, the present invention only with a small amount of circulating register and some it is simple judge on the basis of solution
Intertexture deinterleaving problem.Hardware spending is reduced, power consumption is reduced.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail bright, it should be understood that the foregoing is only specific embodiment of the invention, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc. should be included in protection of the invention
Within the scope of.
Claims (7)
1. a kind of intertexture de-interweaving method of the Turbo code suitable for LTE system, it is characterised in that including：
Input data is divided at least one set, it is true according to institute's packet count, code length and intertexture coefficient in the case of point multigroup
The initialization of cyclic shift register and circulating register number, initialization are included in determination circulating register
Data and order；
Interweave and read data, the storage sequence number according to initialization calculates the position of data interlacing column address, calculate corresponding parameter,
Then according to storage sequence number selection circulating register, further according to the parameter, circulating register shift length is calculated,
The data in register after displacement are used for row and interweave；
Write-in data are deinterleaved, for the data that interweave according to the corresponding relation of row address, reflection is incident upon normal sequence, then calculates
The column address write-in of intertexture.
2. method according to claim 1, it is characterised in that it is described it is at least one set of be 1 group, 4 groups, 8 groups or 16 groups, if
Block length is K, and packet count is M, and wherein packet count correspond to the length of shift register.
3. method according to claim 1, it is characterised in that the cyclic shift length of circulating register is by the first row
Row mapping address determines that the corresponding shift register address of the first every trade mapping address is cyclic shift value.
4. method according to claim 2, it is characterised in that formula f (x) of the intertexture is：
F (x)=(f0x+f1x2) mod N,
Wherein N is data length, f0And f1It is interleave parameter, x corresponds to normal sequence of addresses, then corresponding interleaved transforms are：
F (x+d)=(f (x)+g (x)) mod N
G (x)=(f0d+2f1dx+f1d2)mod N
G (x+d)=(g (x)+delta) mod N
Delta=2d2f1mod N
Wherein g (x) and delta is intermediate variable, and d is step-length；
After packet, block length is K, and packet count is M, and intertexture is divided into two parts, and a part interweaves for column address, and a part is row
Mapping；
Understand that the column interleaving address values do not gone together are consistent according to above-mentioned formula, same rank addresses interweave and are divided into forward recursion
And backward recursion, step-length d=1；
Column address forward recursion formula is：
fcol(x+1)=(fcol(x)+gcol(x))mod K
gcol(x)=(f0+2f1x+f1)mod K
gcol(x+1)=(gcol(x)+deltacol)mod K
deltacol=2f1mod K
Column address backward recursion formula is：
fcol(x+1)=(fcol(x)+g′col(x))mod K
g′col(x)=K-gcol(x)mod K
According to formula above do not go together mapping recurrence formula be：
frow(x)=floor ((f0x+f1x2)/K)mod M
frow(x+K)=(frow(x)+grow(x))mod M
grow(x)=(f0+2f1x+f1K)mod M
grow(x+1)=(grow(x)+deltarow)mod K
deltacol=floor (2f1/K)mod M
Complete mapping of not going together.
5. method according to claim 4, it is characterised in that when for 4 groups when, the relation of the mapping is fixed, described to follow
Ringed shift register number is 1, and the digit of circulating register cyclic shift comes true according to the corresponding mapping relations of the first row
It is fixed.
6. method according to claim 4, it is characterised in that when for 8 groups when,
According to formula grow(x)=(f0+2f1x+f1K it is two kinds of situations that) mod M are divided to, and K is block length, and M is 8；
The first situation, f1It is 4 integral multiple, then row mapping relations are fixed, is present in a circulating register；
Second situation, f1Can not be divided exactly by 4, the circulating register is 2, it is the number of odd number that sequence number x is stored respectively
According to, and sequence number x is the data of even number.
7. method according to claim 4, it is characterised in that when for 8 groups when,
When packet count is 16, according to formula g (x)=(f0+2f1x+f1K) %M points is three kinds of situations, and K is every group leader
Degree, M is 16；
The first situation, f1It is 8 integral multiple, row mapping relations are fixed, and the circulating register number is 1；
Second situation, f1It is 4 integral multiple, the circulating register number is 2, it is the number of odd number that sequence number x is stored respectively
According to, and sequence number x is the data of even number；
The third situation, f1Can not be divided exactly by 4, the circulating register number, mod (x, 4)=0,1,2,3 is corresponded to respectively
Storage condition.
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