CN117976793A - Preparation method of ITO composite film and LED flip chip - Google Patents
Preparation method of ITO composite film and LED flip chip Download PDFInfo
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- CN117976793A CN117976793A CN202410371150.7A CN202410371150A CN117976793A CN 117976793 A CN117976793 A CN 117976793A CN 202410371150 A CN202410371150 A CN 202410371150A CN 117976793 A CN117976793 A CN 117976793A
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Abstract
The invention discloses a preparation method of an ITO composite film layer and an LED flip chip, wherein the method comprises the following steps: providing a deposition epitaxial layer, using Ar as a working gas, sputtering on the deposition epitaxial layer in a preset cavity pressure environment in a magnetron sputtering mode to form an ITO first sub-layer, sputtering on the ITO first sub-layer to form an ITO second sub-layer, sputtering on the ITO second sub-layer to form an ITO third sub-layer, and sputtering on the ITO third sub-layer to form an Al layer; according to the invention, the carrier transport capacity is improved by magnetron sputtering of the ITO composite film, and meanwhile, the compound on the surface of the target is removed in a 'disinfection' mode for the magnetron sputtered target, so that the process of producing the line magnetron sputtering ITO composite film is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a preparation method of an ITO composite film layer and an LED flip chip.
Background
The LED is a novel high-efficiency and low-energy-consumption lighting technology, and the preparation process mainly comprises three steps: growing epitaxial wafer, preparing chip and packaging.
In the current LED chip preparation structure, there are three structures of a forward chip, a vertical chip and a flip chip, and the LED flip chip has the advantages of no electrode shielding, high brightness, high stability, good heat dissipation performance and the like compared with the forward chip and the vertical chip, so that the LED flip chip is widely applied to the fields of illumination and display.
In the process of preparing the ITO composite film layer by mass production of the LED flip chip, the coating time is long, and the brightness of the prepared LED flip chip is not high enough.
Disclosure of Invention
In view of the above-mentioned situation, it is necessary to provide a method for preparing an ITO composite film layer and an LED flip chip, which are required to solve the problems of long ITO coating time and insufficient brightness of the LED flip chip in mass production of the LED flip chip in the prior art.
A preparation method of an ITO composite film and an LED flip chip comprises the following steps:
S1: providing a deposition epitaxial layer, using Ar as working gas, and sputtering on the deposition epitaxial layer in a preset cavity pressure environment in a magnetron sputtering mode to form an ITO first sub-layer, wherein a contact interface is formed between the lower part of the ITO first sub-layer and a P-type layer on the deposition epitaxial layer;
S2: ar is used as working gas, and an ITO second sub-layer is formed on the ITO first sub-layer in a sputtering mode in a preset cavity pressure environment, wherein the ITO second sub-layer is a collective movement area for hole transport;
S3: ar is used as working gas, and an ITO third sub-layer is formed on the ITO second sub-layer in a sputtering mode in a preset cavity pressure environment, wherein the ITO third sub-layer forms a barrier layer;
S4: ar is used as working gas, an Al layer is formed on the ITO third sub-layer in a sputtering mode in a preset cavity pressure environment, and a contact interface with the electrode layer is formed above the Al layer.
Compared with the prior art, the invention has the beneficial effects that: compared with the ITO composite film layer with the total thickness 1112.98A formed by mass production of the ITO composite film layer through sputtering in a production line, the thickness of the ITO composite film layer prepared by the invention can be controlled to be 251.63A-609.06A, the film plating time is shorter because the thickness of the deposited film layer is in direct proportion to the time, the film layer thickness corresponds to the energy band level, the thicker the single layer is, the stronger the bending degree of the energy band is, the more the energy band is, the hole diffusion is restrained, the hole movement capability is required to be enhanced because the bending degree of the energy band is strong, the slower the bending degree of the energy band is, the stronger the hole diffusion capability is, the blocking layer can ensure that the collective movement area for transporting the hole is not directly contacted with an Al layer, the thickness of the Al layer is extremely thin and forms good ohmic contact with an electrode layer, in particular, the flip chip RB 0B is taken as an example, the spot measurement result shows that the light yield and the lifting effect generated by the flip chip is good, if the voltage VF4 is not obviously changed, and the work voltage of the ITO chip is not suitable to be obviously raised when the light-lifting effect of the flip chip is higher.
Further, in the method for preparing the ITO composite film, in the step S1, when the ITO first sub-layer is formed by sputtering, the Ar flow is controlled to 8sccm to 18sccm, the preset chamber pressure environment is 0.2pa to 0.33pa, the sputtering power is controlled to 390w to 410w, the direct current power is controlled to 125w to 130w, and the sputtering time is controlled to 88S to 212S.
Further, in the method for preparing the ITO composite film, in the step S2, when the ITO second sub-layer is formed by sputtering, the Ar flow is controlled to 8 sccm-18 sccm, the preset chamber pressure environment is 0.2 pa-0.33 pa, the sputtering power is controlled to 390 w-410 w, the direct current power is controlled to 550 w-600 w, and the sputtering time is controlled to 88S-211S.
Further, in the method for preparing the ITO composite film, in the step S3, when the third ITO sub-layer is formed by sputtering, the Ar flow is controlled to 7sccm to 16sccm, the preset chamber pressure environment is 0.2pa to 0.33pa, the sputtering power is controlled to 390w to 410w, the direct current power is controlled to 500w to 600w, and the sputtering time is controlled to 88S to 212S.
Further, in the preparation method of the ITO composite film layer, in the step S4, ar flow of the sputtered Al layer is controlled to be 0.5 sccm-2.5 sccm, the preset cavity pressure environment is 0.2 Pa-0.33 Pa, sputtering power is controlled to be 390W-405W, direct current power is controlled to be 495W-505W, and sputtering time is controlled to be 10S-12S.
Further, in the preparation method of the ITO composite film layer, in the step S1, the step S2, and the step S3, targets for sputtering to form the ITO first sub-layer, the ITO second sub-layer, and the ITO third sub-layer are all ITO targets, in the step S4, targets for sputtering to form the Al layer are Al targets, and before the step S1, the preparation method further includes a step S0: and polishing the ITO target.
Further, in the preparation method of the ITO composite film layer, the content ratio of indium oxide to tin oxide in the ITO target is 90:10.
Further, in the preparation method of the ITO composite film layer, polishing sand paper with 50 meshes, 80 meshes and 240 meshes is used in the step S0 respectively.
In the invention, before the ITO composite film layer is deposited, an ITO target is polished, and the polishing step S0 specifically comprises the following steps:
A. Firstly, carrying out rough grinding work by adopting 240-mesh rough grinding sand paper;
B. then carrying out fine polishing operation by using 80-mesh fine polishing sand paper, and finally carrying out 'disinfection' on the surface of the ITO target by using refined 50-mesh polishing sand paper;
C. And (5) after finishing polishing, carrying out hot nitrogen sweeping on the surface of the ITO target material to remove surface dirt. After the surface of the ITO target is cleared, the quality of the deposited ITO composite film layer is effectively improved, the service life of the ITO target is further prolonged, and the service time is prolonged.
Further, the LED flip chip comprises a substrate, a deposited epitaxial layer, a silicon dioxide layer, an ITO composite film layer, an electrode layer, a DBR reflection layer and a bonding pad layer, wherein the ITO composite film layer is prepared according to the preparation method of the ITO composite film layer, and the thickness of the ITO composite film layer is controlled to be 251.63A-609.06A.
In general, before starting the preparation process of the LED flip chip, the following process needs to be completed:
And growing the obtained epitaxial wafer in an epitaxial workshop by using an MOCVD furnace: the method is characterized in that after a sapphire substrate with the thickness of 650 mu m is processed by PSS technology, different raw materials are carried into a reaction chamber through hydrogen, chemical reaction is carried out under the high-temperature condition, and a layer of N-type gallium nitride with the thickness of 4.8 mu m-5.2 mu m is deposited firstly; and then depositing a layer of quantum well which is used as a semiconductor light-emitting layer and has the thickness of 38-42 nm, and finally depositing a layer of P-type gallium nitride to form a deposited epitaxial layer, wherein the thickness of the deposited epitaxial layer is 280-320 nm, and the prepared wafer can be sent to prepare the LED flip chip.
The preparation method of the LED flip chip comprises six steps of preparation process flows, and specifically comprises the following steps:
A. CBL process: firstly, an organic cleaning solvent is used for cleaning a wafer, then a PECVD machine is used for depositing a silicon dioxide layer of 1800-2200A, then a layer of adhesion promoter HMDS is coated on the wafer at the temperature of 80-100 ℃ to be used for increasing the adhesion force between the silicon dioxide layer and photoresist, a positive photoresist is coated at the temperature of 100-120 ℃ and the rotating speed of 3800-4000 r/s for 2.3-2.7 mu m thickness, after the positive photoresist on the wafer is exposed by using an exposure dose of 230 kJ/cm 2~270kJ/cm2, the purpose is to irradiate the photoresist under the ultraviolet light condition to enable the photoresist to be degraded, develop 40-44 s at the temperature of 120-140 ℃, and finally the wafer is sent to a wet workshop to be etched at normal temperature by using a BOE solution and soaked in a photoresist removing solution at the temperature of 80-90 ℃ for 1100s to 130 s, and a semi-finished chip I prepared under the first process condition is obtained.
B. MSA and ITO integrated process: mainly removes part of the P-type gallium nitride layer and the quantum well luminescent layer, and deposits the ITO composite film layer needed to prepare the semi-finished chip II. The MSA and ITO integrated process has the advantages that when the MSA and ITO integrated process is used, the yellow light condition operation only needs one gluing exposure development flow, and compared with the case that the MSA and ITO processes are separately performed, the MSA and ITO integrated process has two yellow light condition operations, namely gluing exposure development, so that the MSA and ITO integrated process can effectively save time, materials, reduce labor cost and the like. The specific flow of the MSA and ITO integrated process is as follows: TCL wafer cleaning, TCL deposition of ITO, TCL wafer alloy, MSA photoresist coating, MSA photoresist exposure, MSA photoresist development, TCL etching of ITO post baking, MSA ICP etching, MSA photoresist removal and inspection, and the specific steps are as follows: firstly, a hydrochloric acid solution is used for cleaning a TCL wafer of a semi-finished chip I, then TCL deposition ITO is carried out, a magnetron sputtering instrument is used for sequentially depositing an ITO composite film layer on the wafer on which a silicon dioxide layer is deposited under the air pressure condition of 0.2 Pa-0.33 Pa, and then TCL wafer alloy is carried out, the principle is that the defect elements in the film layer are removed through high temperature, the lattice is matched again, the stress of the film layer is eliminated, and the effect is that SnO and O 2 in the film layer are combined into SnO 2 in the high temperature state in ITO annealing, so that the molecular structure in the film layer is more stable, the conductivity is better, and the light transmittance is better. Setting an annealing machine to carry out thermal annealing operation on the ITO composite film layer for 10min at the temperature of 550 ℃; then, a yellow light process is performed: the method comprises the steps of MSA photoresist coating, MSA photoresist exposure and MSA photoresist development, wherein the MSA photoresist coating is to coat positive photoresist for 2.8 mu m thickness on a wafer of an ITO composite film layer under the conditions of the temperature of 120 ℃ and the rotating speed of 2700r/s, the MSA photoresist exposure is to expose the positive photoresist on the wafer of the ITO composite film layer under the condition of 180 kJ/cm <2 >, the MSA photoresist development is to develop for 30s under the condition of the temperature of 120 ℃, the MSA photoresist is sent to a wet workshop to etch ITO, hydrochloric acid and ferric chloride solution are used for etching the ITO composite film layer under the conditions of the temperature of 50 ℃ and the time of 360 s-480 s, the subsequent baking after the ITO etching is to bake for 45min in an oven with the temperature of 65 ℃, finally the MSA ICP is sent to etch ICP 450s, the place without photoresist protection is etched to the N-type gallium nitride layer, the MSA photoresist is removed, and photoresist removal (N-methylpyrrolidone, organic alkali and other auxiliary agents are used for forming isopropanol) is used, wherein the photoresist removal solution is used for preparing a second semi-finished product II chip under the conditions of the temperature of 90 ℃ and the time of 1400 s.
C. an ISO process: the obtained semi-finished chip II is cleaned by using an organic cleaning solvent, positive photoresist is coated with 10-12 mu m thickness at the temperature of 100-130 ℃ and the rotating speed of 1250-1350 r/s, the positive photoresist is exposed by using 1300 kJ/cm 2~1500kJ/cm2 exposure dose, the positive photoresist is developed for 100-120 s at the temperature of 100-120 ℃, the semi-finished chip II is sent to ICP etching 1100-1200 s, the photoresist is removed for 1100-2400 s at the temperature of 80-90 ℃, and the edge of the N-type gallium nitride layer is removed to obtain a third yellow light prepared semi-finished chip III, and an electrode layer is formed.
D. PD1 process: firstly, coating negative adhesive with the thickness of 3.5 mu m to 4.2 mu m on a semi-finished chip III at the temperature of 100 ℃ to 120 ℃ and the rotating speed of 3100r/s to 3300r/s, exposing the semi-finished chip III to exposure dose of 250 kJ/cm 2~280kJ/cm2, developing for 35s to 45s at the temperature of 100 ℃ to 120 ℃, then sending oxygen ion for cleaning, carrying out wafer water washing for 800s to 900s and spin-drying for 10min to 20min, evaporating a PAD electrode with the thickness of 1.5 mu m to 2.0 mu m, and finally removing floating and photoresistance to obtain a semi-finished chip IV prepared by a fourth yellow light, namely forming a bonding PAD layer.
E. PV1 technology: firstly, depositing a silicon dioxide layer of 4800-5200A on a semi-finished chip IV by using a PECVD machine, using a DBR-34L deposition process, in the DBR prepared by a 34L light control method, the first layer is titanium oxide, coating a tackifier HMDS at the temperature of 90-110 ℃ after the periodical film thickness of the silicon dioxide layer/titanium oxide layer is ：822 Å、474 Å、714 Å、415 Å、768 Å、454 Å、781 Å、480 Å、827 Å、446 Å、700 Å、453 Å、758 Å、449 Å、887 Å、544 Å、1315 Å、457 Å、943 Å、506 Å、1260 Å、522 Å、990 Å、508 Å、1131 Å、585 Å、1008 Å、523 Å、1099 Å、666 Å、909 Å、564 Å、260 Å. in sequence, coating positive photoresist at the temperature of 100-120 ℃ and the rotating speed of 1750-1850 r/s for 9-11 mu m thickness, exposing the semi-finished chip V by using an exposure dose of 750kJ/cm 2~850kJ/cm2, developing the semi-finished chip V at the temperature of 110-130 ℃, baking the semi-finished chip V for 350-460 s in an oven at the temperature of 135-145 ℃, and removing photoresist at the temperature of 80-90 ℃ for 1100-130 s to obtain a semi-finished chip V prepared in a fifth step, namely the DBR layer.
F. PD2 process: the semi-finished chip V is coated with negative adhesive with the thickness of 3.5-4.0 mu m under the conditions of the temperature of 100-120 ℃ and the rotating speed of 3050-3150 r/s, the semi-finished chip V is exposed by using the exposure dose of 250kJ/cm 2~300kJ/cm2, developed for 35-45 s under the conditions of the temperature of 100-120 ℃, then is subjected to oxygen ion cleaning, the wafer is subjected to acid cleaning for 25-35 s and water cleaning for 600-650 s at the normal temperature, a PAD electrode with the thickness of 2.4-2.6 mu m is evaporated, and then the coated wafer is subjected to floating and photoresist removal to obtain a LED flip chip finished product prepared by the sixth yellow light, namely the bonding PAD layer.
The ITO composite film layer is prepared by the preparation method of the ITO composite film layer, and is applied to a wafer, specifically, after finishing six steps of preparation process flow, the wafer is sent to be ground, the wafer with the thickness of 170 mu m is ground into the thickness of 130 mu m, a blue film is used for pasting, and finally, the required chips which are orderly arranged are obtained through a cutting process.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of the preparation process of the ITO composite film layers of example 1, example 2, and example 3.
Fig. 2 is a process flow chart of the preparation of the ITO composite film layer of example 4.
Fig. 3 is a schematic structural diagram of the ITO composite film layer of comparative example 1.
Fig. 4 is a schematic structural diagram of the ITO composite film layers of example 1, example 2, example 3, and example 4.
Fig. 5 a shows the band diagrams of the ITO sublayers of comparative example 1, and fig. 5B shows the band diagrams of the ITO sublayers of examples 1, 2 and 3.
Fig. 6 is a process flow diagram of the preparation of the LED flip chips of comparative example 1, example 2, example 3, example 4.
Fig. 7 is a schematic structural diagram of the LED flip chip of comparative example 1, example 2, example 3, example 4.
Fig. 8 a shows the effect of the ITO target of example 4 before polishing, and fig. 8B shows the effect of the ITO target of example 1 after polishing.
Reference numerals: 1. a substrate; 2. depositing an epitaxial layer; 3. a silicon dioxide layer; 4. an ITO composite film layer; 5. an electrode layer, 6, DBR reflective layer; 7. a pad layer; 9. an ITO first sub-layer; 10. an ITO second sub-layer; 11. an ITO third sub-layer; 12. an Al layer; 21. an N-type gallium nitride layer; 22. a quantum well light emitting layer; 23. a P-type gallium nitride layer; 101. an ITO fourth sub-layer; 102. and a fifth sublayer of ITO.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
Example 1
Referring to fig. 1 and 4, the preparation method of the ITO composite film layer 4 includes steps S0 to S4;
S0: polishing the ITO target;
Specifically, firstly, carrying out rough grinding work by adopting 240-mesh rough grinding sand paper;
B. then carrying out fine polishing operation by using 80-mesh fine polishing sand paper, and finally carrying out 'disinfection' on the surface of the ITO target by using refined 50-mesh polishing sand paper;
C. and (5) after finishing polishing, carrying out hot nitrogen sweeping on the surface of the ITO target material to remove surface dirt.
S1: providing a deposited epitaxial layer, using Ar as a working gas, and sputtering on the deposited epitaxial layer in a preset cavity pressure environment in a magnetron sputtering mode to form an ITO first sub-layer 9, wherein a contact interface is formed between the lower part of the ITO first sub-layer 9 and a P-type layer on the deposited epitaxial layer;
Specifically, a piece of silicon wafer is placed on a magnetron sputtering machine, the silicon wafer and the wafer are simultaneously sent into a chamber for measuring the thickness of a deposited ITO composite film layer 4,5 measuring points are arranged on each silicon wafer in total and distributed on the upper part, the middle part, the lower part, the left part and the right part of the silicon wafer, the lower end of the lower part is a flat edge and is flush with the magnetron sputtering machine, after sputtering deposition is completed, the silicon wafer and the wafer are tested on an ellipsometer, and the average value is used as the thickness of the deposited ITO composite film layer 4 which is actually sputtered by counting the test data of 5 measuring points; during sputtering, ar flow is 8sccm, cavity pressure environment is 0.2Pa, sputtering power is 410W, direct current power is 125W, sputtering time is 88s, ITO first sub-layer 9 is formed by the contact interface between the ITO first sub-layer 9 and P-GaN, good ohmic contact is formed, work function matching is carried out, wherein work function of P-GaN is 7.5eV, work function of ITO is 5.0eV, and the ITO first sub-layer 9 can be better connected at the contact interface through sputtering deposition.
S2: ar is used as working gas, and an ITO second sub-layer 10 is formed on the ITO first sub-layer 9 in a sputtering mode in a preset cavity pressure environment, wherein the ITO second sub-layer 10 is a collective movement area for hole transportation;
Specifically, after the first sub-layer 9 of ITO is sputtered and deposited, the operation of vacuumizing for 20 seconds and not introducing argon is performed, when the second sub-layer 10 of ITO is started, the Ar flow is 8sccm, the cavity pressure environment is 0.2Pa, the sputtering power is 410W, the direct current power is 550W, the sputtering time is 88 seconds, the second sub-layer 10 of ITO forms a collective movement area for hole transport, an effective movement area for carriers is formed in the LED flip chip, the transport of holes is accelerated, and the transfer capacity of the LED flip chip is improved.
S3: ar is used as working gas, and an ITO third sub-layer 11 is formed on the ITO second sub-layer 10 in a sputtering mode in a preset cavity pressure environment, wherein the ITO third sub-layer 11 forms a barrier layer;
Specifically, after the second sub-layer 10 of ITO is sputtered and deposited, the operation of vacuumizing for 20 seconds and not introducing argon is performed, when the third sub-layer 11 of ITO is started, the Ar flow is 7sccm, the cavity pressure environment is 0.2Pa, the sputtering power is 410W, the direct current power is 500W, the sputtering time is 88 seconds, the third sub-layer 11 of ITO forms an electrode mosaic contact surface, the matching with the work function of the electrode is performed, the work function of the ITO is 5.0eV, wherein the work functions of the metal Ni, au, pt, pd are 5.15eV, 5.1eV, 5.65eV and 5.12eV respectively, and finally good ohmic contact is formed with the electrode.
S4: ar is used as working gas, an Al layer 12 is formed on the ITO third sub-layer 11 in a sputtering mode in a preset cavity pressure environment, and a contact interface between the Al layer 12 and an electrode layer is formed;
Specifically, after the third sub-layer 11 of ITO is deposited, vacuum is applied for 10s, an Al target is used to set the Ar flow to 2.5sccm, the chamber pressure environment is 0.2Pa, the sputtering power is 395W, the direct current power is 500W, the sputtering time is 10s, and the deposition of the ultra-thin Al layer 12 is performed, mainly by increasing the ohmic contact between ITO and the electrode, the work function of Al is 4.28eV, and the work function and the connection electrode are better matched.
The ITO target can produce the phenomenon of target "poisoning", the main reason is that ITO can produce the compound in the sputter deposition process, when the speed is less than the speed of synthetic compound during the sputtering, lead to the insulating layer to appear on the target surface easily, when the bombarded atom receives the barrier of insulating layer, can reduce the quality of ITO complex film layer 4 that follow-up reaction sputtering produced, this kind of phenomenon influences ITO complex film layer 4's electrical property easily, when gathering insulators such as too much compound on the target, need polish the operation, in order to promote the quality effect of use of target, and then promote the life of target.
Specifically, a deposition program SDDA025A-4 is set by a magnetron sputtering machine, steps S1, S2, S3 and S4 are completed, so that the ITO composite film layer 4 of the embodiment is obtained, a silicon wafer and a wafer are placed in a carrier plate position together and enter a chamber for sputtering, and the thicknesses formed by magnetron sputtering on the upper part, the middle part, the lower part, the left part and the right part of the silicon wafer are 253.1A, 256A, 248.6A, 249.9A and 250.6A respectively, and the average value is 251.64A.
The 251.64 a ITO composite film layer 4 is used to manufacture a first flip chip, and the first flip chip uses RB0620B as an example, and in general, before starting the preparation process of the first flip chip of the LED, the following process needs to be completed:
And growing the obtained epitaxial wafer in an epitaxial workshop by using an MOCVD furnace: after the sapphire substrate 1 with the thickness of 650 mu m is processed by PSS technology, different raw materials are carried into a reaction chamber by hydrogen, chemical reaction is carried out under the high temperature condition, and firstly, an N-type gallium nitride layer 21 with the thickness of 5.0 mu m is deposited; next, a quantum well light-emitting layer 22 is deposited, the thickness of which is 40nm, and finally a P-type gallium nitride layer 23 is deposited, so as to form a deposited epitaxial layer 2, the thickness of which is 300nm, and the prepared wafer can be sent to prepare an LED flip chip, and the preparation flow of the first flip chip is as shown in fig. 6 and 7, and the preparation flow of the first flip chip comprises:
A. CBL process: firstly, cleaning a wafer by using an organic cleaning solvent, then depositing a silicon dioxide layer 3 of 2000A by using a PECVD machine, then coating a layer of adhesion promoter HMDS on the wafer at 90 ℃ to increase the adhesion of the silicon dioxide layer 3 and photoresist, coating positive photoresist with the thickness of 2.5 μm at 110 ℃ and 3900, exposing the positive photoresist on the wafer by using the exposure dose of 250 kJ/cm 2, irradiating the photoresist under the condition of ultraviolet light to enable the photoresist to be degraded, developing for 42s at 130 ℃, finally, sending to a wet workshop to etch at normal temperature by using a BOE solution and soaking for 1200s in a photoresist removing solution at 85 ℃ to obtain a semi-finished chip I prepared under the first yellow light condition.
B. MSA and ITO integrated process: mainly removes part of the P-type gallium nitride layer 23 and the quantum well luminescent layer 22, and deposits the ITO composite film layer 4 needed to prepare the semi-finished chip II. The MSA and ITO integrated process has the advantages that when the MSA and ITO integrated process is used, the yellow light condition operation only needs one gluing exposure development flow, and compared with the case that the MSA and ITO processes are separately performed, the MSA and ITO integrated process has two yellow light condition operations, namely gluing exposure development, so that the MSA and ITO integrated process can effectively save time, materials, reduce labor cost and the like. The specific flow of the MSA and ITO integrated process is as follows: TCL wafer cleaning, TCL deposition of ITO, TCL wafer alloy, MSA photoresist coating, MSA photoresist exposure, MSA photoresist development, TCL etching of ITO post baking, MSA ICP etching, MSA photoresist removal and inspection, and the specific steps are as follows: firstly, a hydrochloric acid solution is used for cleaning a TCL wafer of a semi-finished chip I, then TCL deposition ITO is carried out on the wafer on which a silicon dioxide layer 3 is deposited by using a magnetron sputtering instrument, an ITO composite film layer 4 is deposited under the air pressure condition of 0.22Pa in sequence, and then TCL wafer alloy is carried out, the principle is that the defect elements in the film layer are removed through high temperature, the lattice is matched again, the stress of the film layer is eliminated, and the effect is that SnO and O 2 in the film layer are combined into SnO 2 in the high temperature state in ITO annealing, so that the molecular structure in the film layer is more stable, the conductivity is better, and the light transmittance is better. Carrying out thermal annealing operation on the ITO composite film layer 4 for 10min under the condition that the temperature of an annealing machine is 550 ℃; then, a yellow light process is performed: MSA photoresist coating, MSA photoresist exposure and MSA photoresist development, wherein the MSA photoresist coating is to coat positive photoresist 2.8 mu m in thickness on a wafer of the ITO composite film layer 4 under the conditions of the temperature of 120 ℃ and the rotating speed of 2700r/s, the MSA photoresist exposure is to expose the positive photoresist on the wafer of the ITO composite film layer 4 under the condition of the exposure of 180 kJ/cm < 2 >, the MSA photoresist development is to develop for 30s under the condition of the temperature of 120 ℃, the MSA photoresist is sent to a wet workshop to etch ITO, hydrochloric acid and ferric chloride solution are used for etching the ITO composite film layer 4 under the conditions of the temperature of 50 ℃ and the time of 360-480 s, the subsequent post baking of the TCL etching ITO composite film layer 4 is to bake for 45min in an oven with the temperature of 65 ℃, finally the ICP etching of the TCA is to etch 450s, the places without the protection of the photoresist are etched to the N-type gallium nitride layer 21, the MSA photoresist is removed, photoresist is removed by using photoresist removing (N-methylpyrrolidone, organic alkali auxiliary agent such as isopropanol) and the like, wherein the temperature of the second photoresist is to remove the semi-finished chip under the condition of 1400s, and the second time of the second photoresist is to remove the second time of 90 s.
C. An ISO process: the obtained semi-finished chip II is cleaned by using an organic cleaning solvent, the thickness of positive photoresist is coated with 11 mu m at the temperature of 115 ℃ and the rotating speed of 1300r/s, the positive photoresist is exposed by using the exposure dose of 1400 kJ/cm 2, then developed for 110s at the temperature of 110 ℃, transferred to ICP etching 1150s and removed by photoresist for 2350s at the temperature of 85 ℃, and then the N-type gallium nitride layer 21 is subjected to edge removing, thus obtaining the semi-finished chip III prepared by the third yellow light.
D. PD1 process: firstly, a semi-finished chip III is coated with negative adhesive with the thickness of 3.9 mu m at the temperature of 110 ℃ and the rotating speed of 3200, is exposed by using the exposure dose of 2650kJ/cm 2, is developed for 40s at the temperature of 110 ℃, is then sent to oxygen ion cleaning, is subjected to wafer water cleaning 850s and spin-drying for 15min, is then evaporated with a PAD electrode with the thickness of 1.75 mu m, and finally is subjected to floating and photoresist removal to obtain a semi-finished chip IV prepared by a fourth yellow light, namely an electrode layer 5 is formed.
E. PV1 technology: firstly, depositing a 5000A silicon dioxide layer 3 on a semi-finished chip IV by using a PECVD machine, preparing a DBR by using an optically controlled DBR-34L, wherein the first layer is titanium oxide, coating a tackifier HMDS at a temperature of 90-110 ℃ after the periodical film thickness of the silicon dioxide layer 3/titanium oxide layer is ：822 Å、474 Å、714 Å、415 Å、768 Å、454 Å、781 Å、480 Å、827 Å、446 Å、700 Å、453 Å、758 Å、449 Å、887 Å、544 Å、1315 Å、457 Å、943 Å、506 Å、1260 Å、522 Å、990 Å、508 Å、1131 Å、585 Å、1008 Å、523 Å、1099 Å、666 Å、909 Å、564 Å、260 Å., coating positive photoresist with a thickness of 10 μm at a temperature of 110 ℃ and a rotating speed of 1800r/s, exposing the semi-finished chip IV by using an exposure dose of 800kJ/cm 2, developing for 95s at a temperature of 120 ℃, baking for 40min in an oven at a temperature of 140 ℃, transmitting ICP etching 1550s and photoresist removing for 1200s at a temperature of 85 ℃ to obtain a semi-finished chip V prepared by fifth yellow light, namely the DBR reflecting layer 6.
F. PD2 process: the semi-finished chip V is coated with negative adhesive with the thickness of 3.75 mu m at the temperature of 110 ℃ and the rotating speed of 3100r/s, exposed by using the exposure dose of 275kJ/cm 2, developed for 40s at the temperature of 110 ℃, then sent to oxygen ion cleaning, subjected to wafer pickling for 30s and water washing for 625s at the normal temperature, evaporated with a PAD electrode with the thickness of 2.5 mu m, and finally the film-coated wafer is subjected to floating and photoresist removal to obtain the LED flip chip finished product prepared by the sixth yellow light, namely the bonding PAD layer 7.
After the six-step preparation process flow is completed, the wafer is sent to be ground, the wafer with the thickness of 170 mu m is ground into the thickness of 130 mu m, the blue film is used for pasting, and finally the required first flip chip with orderly arrangement is obtained through the cutting process.
Example 2
This example is essentially the same as example 1, except that:
In step S1, ar flow is 13sccm, chamber pressure environment is 0.26Pa, sputtering power is 400W, DC power is 128W, and sputtering time is 159S.
In the step S2, ar flow is 13sccm, chamber pressure environment is 0.26Pa, sputtering power is 400W, direct current power is 600W, and sputtering time is 158S.
In step S3, ar flow is 14sccm, chamber pressure environment is 0.26Pa, sputtering power is 400W, direct current power is 580W, and sputtering time is 159S.
In step S4, ar flow is 1.5sccm, chamber pressure environment is 0.26Pa, sputtering power is 400W, direct current power is 505W, and sputtering time is 11S.
Specifically, a deposition program SDDA045A-4 is set by a magnetron sputtering machine, steps S1, S2, S3 and S4 are completed, so that the ITO composite film layer 4 of the embodiment is obtained, a silicon wafer and a wafer are placed in a carrier plate position together and enter a cavity for sputtering, and the thicknesses formed by magnetron sputtering on the upper part, the middle part, the lower part, the left part and the right part of the silicon wafer are measured to be 477.1A, 473A, 445.6A, 470.1A and 472.6A respectively, and the average value is 467.68A.
The 467.68 a ITO composite film layer 4 is used to manufacture a second flip chip, and the second flip chip uses RB0620B as an example, and the manufacturing process of the second flip chip is the same as that of the first flip chip.
Example 3
This example is essentially the same as example 1, except that:
in step S1, ar flow is 18sccm, chamber pressure environment is 0.33Pa, sputtering power is 390W, DC power is 130W, and sputtering time is 212S.
In step S2, ar flow is 18sccm, chamber pressure environment is 0.33Pa, sputtering power is 390W, DC power is 560W, and sputtering time is 211S.
In step S3, ar flow is 16sccm, chamber pressure environment is 0.33Pa, sputtering power is 390W, DC power is 600W, and sputtering time is 212S.
In the step S4, ar flow is 0.5sccm, chamber pressure environment is 0.33Pa, sputtering power is 405W, direct current power is 495W, and sputtering time is 12S.
Specifically, a deposition program SDDA060A-4 is set by a magnetron sputtering machine, steps S1, S2, S3 and S4 are completed, so that the ITO composite film layer 4 in this embodiment is obtained, a silicon wafer and a wafer are placed in a carrier plate position together and enter a chamber to be sputtered, and the thicknesses formed by magnetron sputtering on the upper part, the middle part, the lower part, the left part and the right part of the silicon wafer are measured to be 623.2 a, 618.5 a, 610A, 596.4 a and 597.2 a respectively, and the average value is 609.06 a.
The 609.06 a ITO composite film layer 4 is used to manufacture a third flip chip, and the preparation process of the third flip chip, taking RB0620B as an example, is the same as the preparation process of the first flip chip.
Comparative example 1
The preparation method of the comparative example comprises the following steps of S01 and S02:
Step S01: placing a piece of silicon wafer on a magnetron sputtering machine table, simultaneously feeding the silicon wafer and the wafer into a chamber for measuring the thickness of the deposited ITO composite film layer 4, arranging 5 measuring points on each silicon wafer, and distributing the measuring points on the upper part, the middle part, the lower part, the left part and the right part of the silicon wafer, wherein the lower end of the lower part is a flat edge and is flush with the magnetron sputtering machine table, testing on an ellipsometer after sputtering deposition is completed, and counting the test data of the 5 measuring points, wherein the average value is used as the thickness of the deposited ITO composite film layer 4 actually sputtered; during sputtering, ar flow is 55sccm, cavity pressure environment is 0.22Pa, sputtering power is 400W, direct current power is 140W, sputtering time is 582s, the main purpose is to ionize argon into argon ions so as to effectively bombard an ITO target, the proportion of indium oxide to tin oxide in the target is 90:10, the contact interface between the layer of the ITO fourth sub-layer 101 and P-GaN is formed, good ohmic contact is formed, work function matching is carried out, wherein the work function of the P-GaN is 7.5eV, the work function of the ITO is 5.0eV, and the sputtering deposition of the ITO fourth sub-layer 101 enables the two to carry out linking effect, and the ITO fourth sub-layer 101 serves as a carrier transport layer;
Step S02: after the sputtering deposition of the ITO fourth sub-layer 101, the operation of vacuumizing for 40s and not introducing argon is mainly used for performing the sputtering deposition of the ITO fifth sub-layer 102 to play a role of buffering, when the sputtering deposition of the ITO fifth sub-layer 102 is started, the Ar flow is 40sccm, the cavity pressure environment is 0.22Pa, the sputtering power is 400W, the direct current power is 600W, the sputtering time is 582s, the ITO fifth sub-layer 102 forms an electrode mosaic contact surface, the matching with the work functions of the electrode, namely the metal Ni, au, pt, pd.15 eV, 5.1eV, 5.65eV and 5.12eV is performed, the work function of the ITO is 5.0eV, and the current source is mainly used for depositing a compact composite film layer to form good ohmic contact, and the ITO fifth sub-layer 102 is used as an ohmic contact layer.
Specifically, through steps S01 and S02, an ITO fourth sub-layer 101 and an ITO fifth sub-layer 102 as shown in fig. 3 are formed, an ITO composite film layer 4 with a total thickness of 1100 a is deposited, a silicon wafer and a wafer are placed in a carrier plate position together and enter a chamber for sputtering, and the thicknesses formed by magnetron sputtering on the upper part, the middle part, the lower part, the left part and the right part of the silicon wafer are measured to be 1132.2 a, 1129.9 a, 1077.7 a, 1096.3 a and 1128.8 a respectively, and the average value is 1112.98 a.
Summarizing the time taken for the deposition of comparative example 1, example 2, and example 3, it can be seen that the deposition thickness is directly proportional to the time taken, the shorter the time taken for the deposition thickness, the thicker the deposition thickness, the longer the time taken for the deposition thickness, as shown in table 1:
TABLE 1
Specifically, the ITO composite film layer of 1112.98 a is used to fabricate a fourth flip chip, and compared with the fourth flip chip, the preparation process of RB0620B is the same as the preparation process of the first flip chip.
Flip chip RB0620B is respectively deposited on the ITO composite film layer 4 with the thicknesses of 250A, 450A, 600 and 1112.98A, and the dot test result shows that compared with the ITO composite film layer 4 with the thickness of 1112.98A, the brightness of the ITO composite film layer 4 with the thickness of 251.64A is relatively improved by 6.23%, the voltage is relatively increased by 0.02V, and the yield is relatively improved by 2.13%; the thickness of the ITO composite film layer 4 is 467.68A, the brightness is relatively improved by 4.43%, the voltage is unchanged, and the yield is relatively improved by 6.55%; the thickness of the ITO composite film layer 4 is 609.06A, the brightness is relatively improved by 2.00%, the voltage is unchanged, and the yield is relatively improved by 1.00%. Further, the brightness and yield of the LED flip chip are improved, the unchanged voltage condition is ensured as much as possible, and detailed data are shown in the table 2:
TABLE 2
If the ITO composite film layer 4 is five or more layers, the brightness of the chip will be higher, but the operating voltage of the chip will be significantly increased, so that the selection is not preferable.
As shown in fig. 5a, a is the ITO sub-layer energy band level of comparative example 1, and in fig. 5B is the ITO sub-layer energy band level of example 1, example 2, and example 3, it can be seen that the ITO sub-layer energy band levels of comparative example 1 and example 1, example 2, and example 3 are different, the ITO composite film layer 4 of comparative example 1 has a thickness of 1112.98 a, the ITO fourth sub-layer and the ITO fifth sub-layer are formed by sputtering, the ITO composite film layer 4 of example 1, example 2, and example 3 has a thickness of 251.64 a, 467.68 a, 609.06 a, and the ITO composite film layer 4 of example 1, 609.06 a, respectively, has a thickness of the ITO first sub-layer 9, the ITO second sub-layer 10, the ITO third sub-layer 11, and the Al layer 12, the ITO sub-layer of comparative example 1 has a thickness of one layer less than that of example 1, the ITO sub-layer thickness affects the band bending variation, the ITO sub-layer thickness is thicker, the band bending is stronger, the band bending is more, the more bending is suppressed, the hole bending is suppressed, the more gradually the hole is suppressed, the chip is the more light, and the chip is the hole is more capable of being flipped, and the luminance is the flip-chip is the most capable of being improved.
Example 4
The preparation method of this example is basically the same as that of example 1, and is shown in fig. 2, wherein the difference is that:
The ITO preparation method does not comprise the step S0.
Specifically, the ITO composite film layer 4 formed by sputtering 251.64 a in embodiment 4 is used to fabricate a fifth flip chip, and the preparation process of the fifth flip chip, taking RB0620B as an example, is the same as the preparation process of the first flip chip.
The first flip chip of example 1 has 0.7% improvement in brightness, no significant difference in voltage, and 0.76% improvement in yield, as compared with the fifth flip chip of example 4, the effect before polishing the ITO target of example 4 is shown in fig. 8 a, and the effect after polishing the ITO target of example 1 is shown in fig. 8B.
The lightning surge test is a test method for testing the protection capability of an LED chip under the condition that the voltage is increased from a certain value, and aims to evaluate the capability of the chip to normally operate in a specific environment and finally protect the self condition. Taking flip chip RB0620B as an example, the EOS capability of each of the two groups of the first flip chip, the second flip chip, the third flip chip and the fourth flip chip was compared, and the death voltage was 16V, and the results indicate that the lightning surge capability of example 1, example 2 and example 3 is consistent with the lightning surge capability of comparative example 1, and the effects are shown in table 3:
TABLE 3 Table 3
According to the invention, carrier transport capacity is improved through magnetron sputtering of the ITO composite film layer 4, meanwhile, a magnetron sputtering target material is subjected to a disinfection mode, compounds on the surface of the target material are removed, and then the process of producing the line magnetron sputtering ITO is improved, specifically, flip chips RB0620B are respectively deposited on the ITO composite film layer 4 with the thicknesses of 251.64 a, 467.68 a, 609.06 and 1112.98 a, and spot measurement results show that compared with a fourth flip chip of comparative example 1, the brightness of the first flip chip manufactured by using the embodiment 1 is improved by 6.23%, the voltage is relatively high by 0.02V, and the yield is relatively improved by 2.13%; compared with the fourth flip chip of comparative example 1, the second flip chip prepared in example 2 has 4.43% improvement in brightness, no obvious change in voltage, and 6.55% improvement in yield; compared with the fourth flip chip of comparative example 1, the third flip chip manufactured by using example 3 has 2.00% of brightness, no obvious change in voltage and 1.00% of yield, so that the brightness and yield of the LED flip chip are improved, and meanwhile, the voltage is ensured to be unchanged as much as possible, for example, when the ITO composite film layer is sputtered to form 5 layers or more, the brightness of the chip is higher, but the working voltage of the chip is obviously increased, so that the selection is not convenient; by comparing the data, the ITO composite film layer 4 of the preparation embodiment 2 has the best effect when being applied to the flip chip, thereby effectively improving the brightness and the coating time of the LED flip chip and further improving the productivity benefit.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (9)
1. The preparation method of the ITO composite film layer is characterized by comprising the following steps:
S1: providing a deposition epitaxial layer, using Ar as working gas, and sputtering on the deposition epitaxial layer in a preset cavity pressure environment in a magnetron sputtering mode to form an ITO first sub-layer, wherein a contact interface is formed between the lower part of the ITO first sub-layer and a P-type layer on the deposition epitaxial layer;
S2: ar is used as working gas, and an ITO second sub-layer is formed on the ITO first sub-layer in a sputtering mode in a preset cavity pressure environment, wherein the ITO second sub-layer is a collective movement area for hole transport;
S3: ar is used as working gas, and an ITO third sub-layer is formed on the ITO second sub-layer in a sputtering mode in a preset cavity pressure environment, wherein the ITO third sub-layer forms a barrier layer;
S4: ar is used as working gas, an Al layer is formed on the ITO third sub-layer in a sputtering mode in a cavity pressure environment of 0.2 Pa-0.33 Pa, and a contact interface with the electrode layer is formed above the Al layer.
2. The method for preparing the ITO composite film layer according to claim 1, characterized in that: in the step S1, when the ITO first sub-layer is formed by sputtering, ar flow is controlled to be 8-18 sccm, the preset cavity pressure environment is 0.2-0.33 Pa, sputtering power is controlled to be 390-410W, direct current power is controlled to be 125-130W, and sputtering time is controlled to be 88-212S.
3. The method for preparing the ITO composite film layer according to claim 1, characterized in that: in the step S2, when the ITO second sub-layer is formed by sputtering, ar flow is controlled to be 8-18 sccm, the preset cavity pressure environment is 0.2-0.33 Pa, sputtering power is controlled to be 390-410W, direct current power is controlled to be 550-600W, and sputtering time is controlled to be 88-211S.
4. The method for preparing the ITO composite film layer according to claim 1, characterized in that: in the step S3, when the ITO third sub-layer is formed by sputtering, ar flow is controlled to be 7 sccm-16 sccm, the preset cavity pressure environment is 0.2 Pa-0.33 Pa, sputtering power is controlled to be 390W-410W, direct current power is controlled to be 500W-600W, and sputtering time is controlled to be 88s-212S.
5. The method for preparing the ITO composite film layer according to claim 1, characterized in that: in the step S4, when an Al layer is formed by sputtering, ar flow is controlled to be 0.5 sccm-2.5 sccm, the preset cavity pressure environment is 0.2 Pa-0.33 Pa, sputtering power is controlled to be 390W-405W, direct current power is controlled to be 495W-505W, and sputtering time is controlled to be 10S-12S.
6. The method for preparing the ITO composite film layer according to claim 1, characterized in that: in the step S1, the step S2, and the step S3, targets for sputtering to form the ITO first sub-layer, the ITO second sub-layer, and the ITO third sub-layer are all ITO targets, in the step S4, targets for sputtering to form an Al layer are Al targets, and before the step S1, the preparation method further includes a step S0: and polishing the ITO target.
7. The method for preparing the ITO composite film according to claim 6, wherein the method comprises the following steps: the content ratio of indium oxide to tin oxide in the ITO target is 90:10.
8. The method for preparing the ITO composite film according to claim 6, wherein the method comprises the following steps: and the step S0 is to use polishing sand paper with 50 meshes, 80 meshes and 240 meshes respectively.
9. An LED flip chip, characterized in that: the LED flip chip comprises a substrate, a deposited epitaxial layer, a silicon dioxide layer, an ITO composite film layer, an electrode layer, a DBR reflection layer and a bonding pad layer which are sequentially deposited on the substrate, wherein the ITO composite film layer is prepared according to the preparation method of any one of claims 1 to 8, and the thickness of the ITO composite film layer is controlled to be 251.63A-609.06A.
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