CN117976704A - Semiconductor device, manufacturing method and display panel - Google Patents

Abstract

The application discloses a semiconductor device, a preparation method and a display panel, which relate to the technical field of semiconductors and comprise the following steps: a gate layer; the diversion layer is positioned at one side of the grid electrode layer; the drain electrode end and the source electrode end are positioned at two sides of the flow guide layer; the first medium end and the second medium end are respectively connected to two sides of the flow guiding layer, the first medium end is connected with the drain end, and the second medium end is connected with the source end; the drain electrode terminal is connected with the drain electrode through a drain electrode, wherein a first gap is formed between the drain electrode terminal and the drain electrode terminal, and a second gap is formed between the drain electrode terminal and the drain electrode terminal. According to the semiconductor device provided by the application, the current flowing direction between the drain electrode end and the source electrode end is changed by adjusting the position of the current guiding layer, so that current does not need to pass through the current guiding layer for many times when the drain electrode end and the source electrode end are conducted, the current loss between the drain electrode end and the source electrode end is reduced, the performance of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.

Description

Semiconductor device, manufacturing method and display panel

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method and a display panel.

Background

In the existing semiconductor device, an amorphous silicon layer is disposed under the drain and source of the transistor, resulting in that current between the drain and source needs to vertically pass through the amorphous silicon layer twice. Because the amorphous silicon layer has a special structure, the resistance value of the amorphous silicon layer in the vertical direction is larger, the current loss is overlarge when the current vertically flows through the amorphous silicon layer, so that the semiconductor device cannot stably operate, the structure of the amorphous silicon layer is easily damaged by the vertical flow of the current, and the service life of the semiconductor device is further shortened.

Disclosure of Invention

The embodiment of the application provides a semiconductor device, a preparation method and a display panel, which are used for solving the technical problems of high current loss and short service life of the semiconductor device in the prior art.

In order to solve the technical problems, the embodiment of the application discloses the following technical scheme:

In a first aspect, there is provided a semiconductor device having a second direction Y, comprising:

A gate layer;

The diversion layer is positioned on one side of the grid electrode layer;

The drain electrode end and the source electrode end are positioned on two sides of the flow guide layer; and

The first medium end and the second medium end are respectively connected to two sides of the flow guide layer, the first medium end is connected with the drain electrode end, and the second medium end is connected with the source electrode end;

wherein the drain terminal, the guide layer and the source terminal are arranged along the second direction Y; a first gap is formed between the diversion layer and the source electrode end, and a second gap is formed between the diversion layer and the drain electrode end.

With reference to the first aspect, the diversion layer includes a first connection layer and a second connection layer, and the second connection layer is located at a side of the first connection layer away from the gate layer;

the first connecting layer is respectively connected with the first medium end and the second medium end.

In combination with the first aspect, the semiconductor device has a first direction X perpendicular to the second direction Y, along which the first dielectric end and the second dielectric end have a first height, and the first connection layer has a second height, which is greater than or equal to the first height.

With reference to the first aspect, at least a portion of the first connection layer structure covers the first medium end and the second medium end.

In combination with the first aspect, an isolation layer is disposed between the gate layer and the diversion layer, and the isolation layer covers the gate layer, and the first medium end and the second medium end are connected to a side, far away from the gate layer, of the isolation layer.

With reference to the first aspect, the semiconductor device has a first direction X perpendicular to the second direction Y, and along the first direction X, the first dielectric end and the second dielectric end have a first orthographic projection and a second orthographic projection on the isolation layer, respectively;

Along the first direction X, the source terminal and the drain terminal have a third orthographic projection and a fourth orthographic projection, respectively, on the insulating layer;

Wherein the third orthographic projection is located in the first orthographic projection, and the fourth orthographic projection is located in the second orthographic projection.

In combination with the first aspect, the semiconductor device further includes a protective layer covering the source terminal, the drain terminal, and the guiding layer.

With reference to the first aspect, the protection layer fills the first gap and then is connected with the first medium end, and the protection layer fills the second gap and then is connected with the second medium end.

In a second aspect, a method for manufacturing a semiconductor device is provided, the method comprising:

Obtaining a grid electrode layer;

sequentially depositing a dielectric layer and a metal layer on the grid electrode layer;

etching the metal layer to obtain a drain terminal and a source terminal which are separated from each other;

etching the dielectric layer to obtain a first dielectric end and a second dielectric end which are mutually separated;

obtaining a diversion layer to connect the first medium end and the second medium end, wherein the first medium end and the second medium end are respectively positioned at two sides of the diversion layer;

The drain terminal, the current guiding layer and the source terminal are arranged along a second direction Y; a first gap is formed between the diversion layer and the source electrode end, and a second gap is formed between the diversion layer and the drain electrode end.

In a third aspect, there is provided a display panel comprising the semiconductor device according to any one of the first aspects, or a semiconductor device in the display panel obtained using the semiconductor device manufacturing method according to the second aspect.

One of the above technical solutions has the following advantages or beneficial effects:

In contrast to the prior art, a semiconductor device of the present application has a second direction Y, comprising: a gate layer; the diversion layer is positioned at one side of the grid electrode layer; the drain electrode end and the source electrode end are positioned at two sides of the flow guide layer; the first medium end and the second medium end are respectively connected to two sides of the flow guiding layer, the first medium end is connected with the drain end, and the second medium end is connected with the source end; wherein the drain terminal, the guide layer and the source terminal are arranged along the second direction Y; a first gap is formed between the current guiding layer and the source electrode end, and a second gap is formed between the current guiding layer and the drain electrode end. According to the semiconductor device provided by the application, the current flowing direction between the drain electrode end and the source electrode end is changed by adjusting the position of the current guiding layer, so that current does not need to pass through the current guiding layer for many times when the drain electrode end and the source electrode end are conducted, the current loss between the drain electrode end and the source electrode end is reduced, the performance of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.

In the application, a preparation method of a semiconductor device comprises the following steps: obtaining a grid electrode layer; sequentially depositing a dielectric layer and a metal layer on the grid electrode layer; etching the metal layer to obtain a drain terminal and a source terminal which are separated from each other; etching the dielectric layer to obtain a first dielectric end and a second dielectric end which are mutually separated; obtaining a flow guiding layer to connect a first medium end and a second medium end, wherein the first medium end and the second medium end are respectively positioned at two sides of the flow guiding layer; wherein the drain terminal, the guide layer and the source terminal are arranged along the second direction Y; a first gap is formed between the current guiding layer and the source electrode end, and a second gap is formed between the current guiding layer and the drain electrode end. According to the preparation method of the semiconductor device, the drain terminal and the source terminal are obtained on the gate layer, and the first medium terminal and the second medium terminal carrying the drain terminal and the source terminal are connected through the current-guiding layer, so that the current loss between the drain terminal and the source terminal is reduced, and the semiconductor device can normally operate.

Drawings

The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic cross-sectional structure of a semiconductor device after molding according to an embodiment of the present application;

Fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application after a metal layer is deposited;

Fig. 4 is a schematic cross-sectional structure of a semiconductor device after etching a metal layer and a dielectric layer according to an embodiment of the present application;

fig. 5 is a schematic cross-sectional structure diagram of a drain terminal and a source terminal obtained by etching a semiconductor device according to an embodiment of the present application;

fig. 6 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present application after a first connection layer is deposited;

fig. 7 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present application after a second connection layer is deposited;

Fig. 8 is a schematic top view of the semiconductor device of fig. 7 according to an embodiment of the present application.

The reference numerals are as follows:

100-gate layer, 200-isolation layer, 300-dielectric layer, 310-first dielectric end, 320-second dielectric end, 400-metal layer, 410-first isolation layer, 420-second isolation layer, 430-drain end, 440-source end, 500-protective layer, 600-amorphous silicon layer, 610-conduction layer, 620-cover layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Those skilled in the art will note that in most of the existing semiconductor devices, amorphous silicon, i.e., a-Si, is used as the bottom gate structure, in which the drain and gate of the semiconductor device are located directly above the amorphous silicon. This structural design results in the need for two perpendicular passes of current from drain to source through the amorphous silicon layer. The resistance value of the amorphous silicon layer in the vertical direction is larger due to the film layer specificity of the amorphous silicon layer in the vertical direction, so that the current from the drain electrode to the source electrode can be greatly attenuated. And the current vertically passes through the amorphous silicon layer for many times can cause damage to the upper layer part, thereby affecting the stability of the semiconductor device.

The following examples illustrate embodiments of the application:

As shown in fig. 1, an embodiment of the present application provides a semiconductor device having a second direction Y, including: a gate layer 100; a guide layer 600, the guide layer 600 being located at one side of the gate layer 100; a drain terminal 430 and a source terminal 440, the drain terminal 430 and the source terminal 440 being located at both sides of the current guiding layer 600; and a first medium end 310 and a second medium end 320, wherein the first medium end 310 and the second medium end 320 are respectively connected to two sides of the guiding layer 600, the first medium end 310 is connected to the drain end 430, and the second medium end 320 is connected to the source end 440; wherein the drain terminal 430, the guiding layer 600 and the source terminal 440 are arranged along the second direction Y; a first gap is provided between the drain terminal 430 and the drain terminal 600, respectively. Specifically, the drain terminal 430 is located above the first dielectric terminal 310 and is connected to the first dielectric terminal 310, and the source terminal 440 is located above the second dielectric terminal 320 and is connected to the second dielectric terminal 320. The first medium end 310 and the second medium end 320 are connected and conducted through the flow guiding layer 600, and the first medium end 310 and the second medium end 320 are made of the same material and are made of amorphous silicon materials doped with phosphorus. In the embodiment of the present application, the first dielectric terminal 310 and the second dielectric terminal 320 are used as the buffer layers of the drain terminal 430 and the source terminal 440, so that when the drain terminal 430 and the source terminal 440 are conducted, the resistance between the drain terminal 430 and the source terminal 440 and the current guiding layer 600 is reduced, and the current between the drain terminal 430 and the source terminal 440 is increased. Also, the current between the drain terminal 430 and the source terminal 440 does not need to vertically pass through the conductive layer 600 a plurality of times, and thus, the loss of current is small and the semiconductor device can stably operate.

As shown in fig. 1, in the embodiment of the present application, the diversion layer 600 includes a first connection layer 610 and a second connection layer 620, and the second connection layer 620 is located on a side of the first connection layer 610 away from the gate layer 100; wherein the first connection layer 610 is connected to the first medium terminal 310 and the second medium terminal 320, respectively. Specifically, as shown in fig. 1, the semiconductor device has a first direction X and a second direction Y perpendicular to each other. The first connection layer 610 has both ends connected to the first medium end 310 and the second medium end 320, respectively, and the first connection layer 610 is flush with the first medium end 310 and the second medium end 320 in the second direction Y. It can be appreciated that if the current at the drain terminal 430 vertically passes through the second connection layer 620 and the first connection layer 610 from the first dielectric terminal 310, and then passes through the second connection layer 620 to enter the second dielectric terminal 320, the current loss is excessive due to the excessively large resistance of the second connection layer 620. And the first connection layer 610, the first dielectric terminal 310 and the second dielectric terminal 320 are disposed on the same horizontal plane, so that the resistance between the drain terminal 430 and the source terminal 440 can be reduced, and further, the current loss can be reduced, and the stability of the semiconductor device can be improved.

As shown in fig. 1, in the embodiment of the present application, the first dielectric end 310 and the second dielectric end 320 have a first height along the first direction X, and the first connection layer 610 has a second height, which is greater than or equal to the first height. Specifically, the first connection layer 610 and the second connection layer 620 have different qualities, the first connection layer 610 has a low forming speed, the film layer has a high quality and a low resistance, the second connection layer 620 has a high forming speed, the film layer has a relatively poor quality compared with the first connection layer 610, and the second connection layer 620 has a high resistance and a relatively poor stability. Therefore, the second height of the first connection layer 610 is set to be higher than the first heights of the first medium terminal 310 and the second medium terminal 320, so that the second connection layer 620 can be effectively prevented from forming connection with the first medium terminal 310 and the second medium terminal 320. Therefore, the current loss between the drain terminal 430 and the source terminal 440 can be reduced by connecting and conducting the first dielectric terminal 310 and the second dielectric terminal 320 through the first connection layer 610 with better film quality, thereby improving the stability and the working efficiency of the semiconductor device.

As shown in fig. 1, in an embodiment of the present application, at least a portion of the structure of the first connection layer 610 covers the first dielectric end 310 and the second dielectric end 320. Specifically, covering the first dielectric terminal 310 and the second dielectric terminal 320 by the first connection layer 610 may increase a contact area between the first connection layer 610 and the first dielectric terminal 310 and the second dielectric terminal 320, thereby reducing a resistance between the first connection layer 610 and the first dielectric terminal 310 and the second dielectric terminal 320, and further reducing a current loss between the drain terminal 430 and the source terminal 440.

As shown in fig. 1, in the embodiment of the application, an isolation layer 200 is disposed between the gate layer 100 and the guiding layer 600, and the isolation layer 200 covers the gate layer 100, and the first dielectric terminal 310 and the second dielectric terminal 320 are connected to a side of the isolation layer 200 away from the gate layer 100. Specifically, the isolation layer 200 is used to isolate the gate layer 100 from the drain terminal 430 and the source terminal 440. The insulating layer 200 is generally made of silicon nitride or silicon oxide. The first medium end 310 and the second medium end 320 are disposed on the insulating layer 200, and are in contact with the insulating layer 200. The gate layer 100, the drain terminal 430 and the source terminal 440 form a semiconductor structure through the insulating layer 200, and when the gate layer 100 is controlled, the drain terminal 430 and the source terminal 440 are electrically connected to each other, and a current flows from the drain terminal 430 to the source terminal 440.

As shown in fig. 1, in an embodiment of the present application, first medium end 310 and second medium end 320 have a first orthographic projection and a second orthographic projection, respectively, on insulating layer 200 along first direction X; along the first direction X, the source terminal 440 and the drain terminal 430 have a third orthographic projection and a fourth orthographic projection, respectively, on the insulating layer 200; the third orthographic projection is located in the first orthographic projection, and the fourth orthographic projection is located in the second orthographic projection. Specifically, the first dielectric terminal 310 and the second dielectric terminal 320 are located directly above the insulating layer 200 and are directly connected to the insulating layer 200, the drain terminal 430 is located directly above the first dielectric terminal 310 and is directly connected to the first dielectric terminal 310, and the source terminal 440 is located directly above the second dielectric terminal 320 and is directly connected to the second dielectric terminal 320. The partial structures of the drain terminal 430 and the source terminal 440 near one side of the current guiding layer 600 are etched away to expose the first dielectric terminal 310 and the second dielectric terminal 320, so that the first connection layer 610 can cover the first dielectric terminal 310 and the second dielectric terminal 320, thereby enhancing the connection relationship between the first connection layer 610 and the first dielectric terminal 310 and the second dielectric terminal 320, and further reducing the current loss between the drain terminal 430 and the source terminal 440.

As shown in fig. 1, in an embodiment of the present application, the semiconductor device further includes a protection layer 500, where the protection layer 500 covers the source terminal 440, the drain terminal 430, and the guiding layer 600. Specifically, after the formation of the conductive layer 600, in order to avoid the influence of foreign substances on the source terminal 440, the drain terminal 430 and the conductive layer 600, the protection layer 500 is further disposed on the source terminal 440, the drain terminal 430 and the conductive layer 600, thereby protecting the source terminal 440, the drain terminal 430 and the conductive layer 600.

As shown in fig. 1, in the embodiment of the present application, a first gap is formed between the guiding layer 600 and the source terminal 440, a second gap is formed between the guiding layer 600 and the drain terminal 430, the protection layer 500 is connected to the first medium terminal 310 after filling the first gap, and the protection layer 500 is connected to the second medium terminal 320 after filling the second gap. Specifically, since there is a larger resistance between the source terminal 440 and the drain terminal 430 and the guiding layer 600, in order to avoid current loss between the drain terminal 430 and the source terminal 440, the protection layer 500 is filled between the first gap and the second gap to act as an insulation function, thereby avoiding conduction between the drain terminal 430 and the source terminal 440 and the guiding layer 600.

In some other embodiments of the present application, the drain terminal 430 and the source terminal 440 may be directly connected to the guiding layer 600, i.e. there is no second gap between the drain terminal 430 and the guiding layer 600, and a first gap is provided between the source terminal 440 and the guiding layer 600. Accordingly, the current between the drain terminal 430 and the source terminal 440 may be directly conducted through the conductive layer 600.

As shown in fig. 1 to 7, an embodiment of the present application further provides a method for manufacturing a semiconductor device, where the method includes:

S1: a gate layer 100 is obtained.

Specifically, a substrate or a substrate capable of carrying a semiconductor device is first formed, a gate initial structure is obtained by deposition on the substrate or the substrate, and a part of the structure of the gate initial structure is removed by etching (e.g., dry etching or wet etching) to obtain the gate layer 100.

S2: a dielectric layer 300 and a metal layer 400 are sequentially deposited on the gate layer 100.

Specifically, before depositing the dielectric layer 300 and the metal layer 400, an isolation structure is first deposited on the gate layer 100 by a chemical vapor method or a physical vapor method, and the gate layer 100 is covered and wrapped by the isolation structure. Grinding a side plane, far away from the gate layer 100, of the isolation structure by a chemical mechanical grinding method to obtain an isolation layer 200, wherein the isolation layer 200 is made of silicon nitride or silicon oxide;

Sequentially depositing a dielectric layer 300 and a metal layer 400 on the isolation layer 200, wherein the metal layer 400 is connected with the dielectric layer 300, and the thickness of the metal layer 400 is larger than that of the dielectric layer 300; the material of the dielectric layer 300 includes amorphous silicon doped with phosphorus, and the material of the metal layer 400 includes tungsten and other metals.

S3: the metal layer 400 is etched to obtain a drain terminal 430 and a source terminal 440 separated from each other.

Specifically, the metal layer 400 is etched directly above the gate layer 100 to expose the dielectric layer 300 under the metal layer 400, thereby dividing the metal layer 400 into two portions, namely, a drain end 430 and a source end 440, which are disposed opposite to each other.

S4: dielectric layer 300 is etched to obtain first dielectric end 310 and second dielectric end 320 that are separated from each other.

Specifically, after the metal layer 400 is etched, etching is performed on the dielectric layer 300 to expose the isolation layer 200 under the dielectric layer 300, so as to divide the dielectric layer 300 into two portions, namely a first dielectric end 310 and a second dielectric end 320, which are oppositely disposed, wherein the first dielectric end 310 is located under the drain end 430, and the second dielectric end 320 is located under the source end 440.

It should be noted that, the metal layer 400 and the dielectric layer 300 may be etched at the same time to expose the isolation layer 200, and at this time, the metal layer 400 is divided into a first insulating layer 410 and a second insulating layer 420 that are disposed opposite to each other, the dielectric layer 300 obtains a first dielectric end 310 and a second dielectric end 320, and the etching is continued to etch opposite sides of the first insulating layer 410 and the second insulating layer 420 to expose the first dielectric end 310 and the second dielectric end 320, respectively.

S5: obtaining a current guiding layer 600 to connect the first medium end 310 and the second medium end 320, where the first medium end 310 and the second medium end 320 are respectively located at two sides of the current guiding layer 600; wherein the drain terminal 430, the guiding layer 600 and the source terminal 440 are arranged along the second direction Y; a first gap is provided between the drain terminal 430 and the drain terminal 600, respectively. Specifically, the flow guiding layer 600 includes a first connection layer 610 and a second connection layer 620, where the first connection layer 610 is formed by controlling parameters such as concentration of a reactant, temperature and pressure of a reaction environment, and both sides of the first connection layer 610 cover the first medium end 310 and the second medium end 320, respectively. The reaction conditions are changed, and a second connection layer 620 is formed on the first connection layer 610, and the second connection layer 620 is not connected to the first medium terminal 310 and the second medium terminal 320. Wherein, the first connection layer 610 and the second connection layer 620 have a second gap with the drain terminal 430 and a first gap with the source terminal 440. It should be noted that the reaction speed of the first connection layer 610 is slower than that of the second connection layer 620, and the film quality of the first connection layer 610 is higher than that of the second connection layer 620.

In the embodiment of the present application, after the second connection layer 620 is formed, the protection layer 500 is deposited on the drain terminal 430, the first dielectric terminal 310, the second connection layer 620, the second dielectric terminal 320, and the source terminal 440, wherein the protection layer 500 is further filled in the first gap and the second gap.

The embodiment of the application also provides a display panel, which comprises the semiconductor device provided by any one of the above, or the semiconductor device in the display panel is obtained by adopting the preparation method of the semiconductor device provided by the above.

The above description is provided for the detailed description of a semiconductor device, a manufacturing method and a display panel provided by the embodiments of the present application, and specific examples are applied to the description of the principles and the embodiments of the present application, where the description of the above examples is only for helping to understand the technical solution and the core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims (10)

1. A semiconductor device having a second direction (Y), characterized by comprising:

A gate layer (100);

A current guiding layer (600), wherein the current guiding layer (600) is positioned at one side of the grid layer (100);

A drain terminal (430) and a source terminal (440), the drain terminal (430) and the source terminal (440) being located on both sides of the guiding layer (600); and

A first medium end (310) and a second medium end (320), wherein the first medium end (310) and the second medium end (320) are respectively connected to two sides of the flow guiding layer (600), the first medium end (310) is connected with the drain end (430), and the second medium end (320) is connected with the source end (440);

wherein the drain terminal (430), the guiding layer (600) and the source terminal (440) are arranged along the second direction (Y); a first gap is provided between the current guiding layer (600) and the source terminal (440), and a second gap is provided between the current guiding layer (600) and the drain terminal (430).

2. The semiconductor device according to claim 1, wherein the flow guiding layer (600) comprises a first connection layer (610) and a second connection layer (620), the second connection layer (620) being located at a side of the first connection layer (610) remote from the gate layer (100);

wherein the first connection layer (610) is connected to the first medium end (310) and the second medium end (320), respectively.

3. The semiconductor device of claim 2, wherein the semiconductor device has a first direction (X) perpendicular to the second direction (Y), along which first direction (X) the first dielectric terminal (310) and the second dielectric terminal (320) have a first height, the first connection layer (610) having a second height, the second height being greater than or equal to the first height.

4. The semiconductor device of claim 2, wherein at least a portion of the structure of the first connection layer (610) covers the first dielectric end (310) and the second dielectric end (320).

5. The semiconductor device of claim 4, wherein an isolation layer (200) is disposed between the gate layer (100) and the conductive layer (600), and the isolation layer (200) covers the gate layer (100), the first dielectric terminal (310) and the second dielectric terminal (320) being connected to a side of the isolation layer (200) remote from the gate layer (100).

6. The semiconductor device of claim 5, wherein the semiconductor device has a first direction (X) perpendicular to the second direction (Y), along which first direction (X) the first dielectric end (310) and the second dielectric end (320) have a first orthographic projection and a second orthographic projection, respectively, on the insulating layer (200);

-along the first direction (X), the source end (440) and the drain end (430) have a third orthographic projection and a fourth orthographic projection, respectively, on the insulating layer (200);

Wherein the third orthographic projection is located in the first orthographic projection, and the fourth orthographic projection is located in the second orthographic projection.

7. The semiconductor device of claim 2, further comprising a protective layer (500), the protective layer (500) covering the source terminal (440), the drain terminal (430), and the conductive layer (600).

8. The semiconductor device of claim 7, wherein the protective layer (500) fills the first gap and is connected to the first dielectric terminal (310), and wherein the protective layer (500) fills the second gap and is connected to the second dielectric terminal (320).

9. A method of manufacturing a semiconductor device, the method comprising:

obtaining a gate layer (100);

sequentially depositing a dielectric layer (300) and a metal layer (400) on the gate layer (100);

Etching the metal layer (400) to obtain a drain terminal (430) and a source terminal (440) separated from each other;

Etching the dielectric layer (300) to obtain a first dielectric end (310) and a second dielectric end (320) separated from each other;

Obtaining a diversion layer (600) so as to connect the first medium end (310) and the second medium end (320), wherein the first medium end (310) and the second medium end (320) are respectively positioned at two sides of the diversion layer (600);

Wherein the drain terminal (430), the guiding layer (600) and the source terminal (440) are arranged along a second direction (Y); a first gap is provided between the current guiding layer (600) and the source terminal (440), and a second gap is provided between the current guiding layer (600) and the drain terminal (430).

10. A display panel, characterized in that the display panel comprises the semiconductor device according to any one of claims 1-8, or the semiconductor device in the display panel is obtained by the semiconductor device manufacturing method according to claim 9.