CN117976701A - Device containing semiconductor field plate and preparation method thereof - Google Patents
Device containing semiconductor field plate and preparation method thereof Download PDFInfo
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- CN117976701A CN117976701A CN202410028745.2A CN202410028745A CN117976701A CN 117976701 A CN117976701 A CN 117976701A CN 202410028745 A CN202410028745 A CN 202410028745A CN 117976701 A CN117976701 A CN 117976701A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 230000006911 nucleation Effects 0.000 claims description 7
- 238000010899 nucleation Methods 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 42
- 238000009826 distribution Methods 0.000 abstract description 14
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 12
- 229910002601 GaN Inorganic materials 0.000 description 13
- 230000008859 change Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a device containing a semiconductor field plate, which comprises a drain electrode, a source electrode, a gate electrode and a field plate, wherein two ends of the field plate are respectively connected with the source electrode and the drain electrode or the gate electrode and the drain electrode, and the field plate is made of a semiconductor material. The device containing the semiconductor field plate comprises the field plate made of semiconductor material, wherein one end of the field plate is connected with a drain electrode, and the other end of the field plate is connected with a gate electrode or a source electrode, so that uniform gradient potential is formed on the field plate when the device is turned off; the potential difference between the field plate and the two-dimensional electron gas below is effectively controlled, the electric field distribution is effectively improved, the problems that the dielectric layer breaks down and the reliability fails due to the high electric field and the dielectric layer traps charges due to the high electric field strength are solved, and meanwhile, the preparation process of the field plate is simpler.
Description
Technical Field
The invention relates in particular to a High Electron Mobility Transistor (HEMT) comprising a semiconductor field plate and a method of manufacturing the device.
Background
GaN is a third generation semiconductor material with significant advantages over first generation Si, second generation GaAs. The AlGaN/GaN HEMT has large energy band gap, high peak saturated electron velocity, high concentration two-dimensional electron gas and higher electron mobility, so that the AlGaN/GaN HEMT is widely applied to the fields of RF (radio frequency), microwaves, power switch power supplies and the like.
AlGaN/GaN HEMTs belong to planar channel field effect transistors. When a high voltage is applied to the drain electrode, a large electric field spike is generated on one side of the edge of the gate electrode, which is close to the drain electrode, so that a local dielectric layer is degraded, and the breakdown is caused with time, thereby seriously affecting the reliability of the device. In order to solve the serious electric field peak problem, the prior art generally adopts a gate electrode to place one or more field plates, so that the peak height is restrained, and the reliability of the device is improved.
The electric connection of the field plates in industry mainly comprises a gate field plate connected with a gate electrode and a source field plate connected with a source electrode, and the implementation mode mainly comprises a multi-step structure or an inclined structure. In the existing schemes, the capacitance is gradually reduced by gradually increasing the distance between the field plate and the two-dimensional electron gas, so that the turn-off voltage is gradually increased under the condition that the total charge quantity is unchanged, and finally, the electric field gradient is formed.
For example, the technical scheme disclosed in the chinese patent publication No. CN1938859B, entitled wide bandgap transistor device with field plate, is that the field plate structure commonly used in the industry at present forms field plates with multiple heights through multiple dielectric layers, and mainly has the following problems: 1. in order to form the gradient field plate, 2-5 steps are added, and the process is complex; 2. the dielectric layer bears high electric field intensity, which is easy to cause the reliability failure of the device; 3. the electric field intensity is high, which is easy to cause the charge trapping of the dielectric layer and the rise of the dynamic resistance; 4. because the electric potential of the field plate is fixed, the voltage of the drain terminal is above a certain value, the electric field intensity under the field plate is not changed any more, and only the electric field intensity between the tail end of the field plate and the drain electrode is increased along with the increase of the voltage of the drain terminal, so that the high voltage resistant range is limited.
Another example is chinese patent publication No. CN104332498B, entitled oblique field plate power device and method for manufacturing the same, in which the formation mode of the field plate is changed by tilting the field plate. The electric field distribution is optimized, the complex problem of the preparation process of the multi-field plate is solved, and the main problems are that: 1. the dielectric layer bears high electric field intensity, which is easy to cause the reliability failure of the device; 2. the electric field intensity causes the dielectric layer to capture charges so as to increase the dynamic resistance; 3. forming a slow inclination angle, the process is difficult to realize and has poor repeatability; 4. because the electric potential of the field plate is fixed, the voltage of the drain terminal is above a certain value, the electric field intensity under the field plate is not changed any more, and only the electric field intensity between the tail end of the field plate and the drain electrode is increased along with the increase of the voltage of the drain terminal, so that the high voltage resistant range is limited.
It can be seen that the introduction of the planar channel structure and the multi-field plate of the existing AlGaN/GaN HEMT causes a number of problems: in order for the device to withstand high voltages, multiple field plates are required to suppress voltage spikes; in order to realize the multi-field plate, 2 to 5 additional process steps are added, the process complexity and the processing cost are increased, and meanwhile, the hidden danger of introducing defects in the process is increased due to excessive process steps, so that the reliability of the device is not good; the field plates adopted in the industry at present are provided with a gate and a source field plate, but because the field plate potential is equal to the gate potential or the source potential, a large potential difference is formed between the field plate and two-dimensional electron gas below the field plate, and most of reasons for device failure are located, and the reliability failure of the device is easily caused mainly because the dielectric layer is subjected to high electric field strength; meanwhile, the high electric field intensity causes the dielectric layer to capture charges so as to increase the dynamic resistance; in addition, the potential of the field plate is fixed, so that when the voltage of the drain terminal is above a certain value, the electric field intensity under the field plate is not changed any more, and only the electric field intensity between the tail end of the field plate and the drain electrode is increased along with the increase of the voltage of the drain terminal, so that the high voltage resistant range is limited. Therefore, the preferred implementation of the field plate is a key issue to be addressed by AlGaN/GaN HEMTs.
Disclosure of Invention
In view of this, it is an object of the present invention to overcome the drawbacks of the prior art by providing an improved device structure comprising a semiconductor field plate structure connected between a source electrode and a drain electrode or between a gate electrode and a drain electrode.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
The device comprises a drain electrode, a source electrode, a gate electrode and a field plate, wherein two ends of the field plate are respectively connected with the source electrode and the drain electrode or the gate electrode and the drain electrode, and the field plate is made of a semiconductor material.
According to some preferred embodiments of the present invention, the semiconductor device comprises a substrate, a laminated structure and a first dielectric layer, wherein the substrate, the laminated structure and the first dielectric layer are sequentially arranged from bottom to top, the drain electrode and the source electrode are located in the laminated structure and the first dielectric layer, and the gate electrode is located in the first dielectric layer; the field plate is located above the first dielectric layer.
According to some preferred embodiments of the invention, the field plate connects the source and drain electrodes, the first dielectric layer or gate electrode is covered with a second dielectric layer, and the field plate is located above the second dielectric layer.
According to some preferred embodiments of the invention, the field plate is provided with a groove which is opened along the thickness direction of the field plate, and the depth of the groove is smaller than the thickness of the field plate.
According to some preferred embodiments of the present invention, the number of the grooves is 1-50, the pitch is 0.1-30um, and the depth of the grooves is 10% -90% of the thickness of the field plate.
According to some preferred embodiments of the invention, the field plate is prepared by the following method: and growing a semiconductor material on the first dielectric layer to form a semiconductor field plate, and simultaneously enabling two ends of the semiconductor field plate to be respectively connected with a drain electrode and a gate electrode or a drain electrode and a source electrode.
According to some preferred embodiments of the invention, the field plate has a thickness of 1-2000nm and a resistivity of 1e 2-1 e6 Ω.m.
According to some preferred embodiments of the present invention, the semiconductor material is silicon and/or germanium, and the amorphous silicon may be specifically formed into the semiconductor field plate by a silane thermal decomposition method or a siemens method.
The invention also provides a preparation method of the device, which comprises the following steps:
Performing nitride epitaxial growth on a substrate, and sequentially forming a nucleation layer, a buffer layer, a channel layer and a barrier layer, wherein the nucleation layer, the buffer layer, the channel layer and the barrier layer form a laminated structure;
Etching a source electrode hole and a drain electrode hole on the barrier layer;
Filling metal in the source electrode hole and the drain electrode hole, and annealing to form ohmic contact, so as to respectively form the source electrode and the drain electrode;
depositing a first dielectric layer above the barrier layer and etching a gate electrode hole;
Filling metal on the dielectric layer and etching redundant metal to form a gate electrode;
And growing a semiconductor material on the first dielectric layer to form a semiconductor field plate, and simultaneously enabling two ends of the semiconductor field plate to be respectively connected with a drain electrode, a gate electrode or a drain electrode and a source electrode to obtain the device.
According to some preferred embodiments of the present invention, the method further comprises the step of forming a recess in the semiconductor field plate: patterning is performed after the formation of the semiconductor field plate, and grooves are etched in the semiconductor field plate.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages: the device with the semiconductor field plate structure is made of semiconductor material and is connected between a source electrode and a drain electrode or between a gate electrode and a source electrode. By introducing a semiconductor field plate, one end of the semiconductor field plate is connected to the drain electrode and the other end is connected to the gate electrode or the source electrode, so that a uniform graded potential is formed on the field plate when the device is turned off. Through the uniform gradual change potential of the field plate, the electric field distribution is effectively improved, the potential difference between the field plate and the two-dimensional electron gas below is effectively controlled, and the problems that the dielectric layer breaks down and the reliability fails due to the high electric field and charges are trapped in the dielectric layer due to the high electric field strength are solved; and meanwhile, the process for forming the field plate is simpler.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a device according to a preferred embodiment of the present invention after forming a stacked structure;
fig. 2 is a schematic cross-sectional structure of a device according to a preferred embodiment of the present invention after forming drain and source holes;
FIG. 3 is a schematic cross-sectional view of a device according to a preferred embodiment of the present invention after forming drain and source electrodes;
fig. 4 is a schematic cross-sectional structure of a device according to a preferred embodiment of the present invention after a first dielectric layer is formed;
Fig. 5 is a schematic cross-sectional structure of a device according to a preferred embodiment of the present invention after forming a gate electrode hole;
fig. 6 is a schematic cross-sectional structure of a device according to a preferred embodiment of the present invention after forming a gate electrode;
FIG. 7 is a schematic cross-sectional view of a device according to a first embodiment of the present invention after a field plate is formed in a method for fabricating a device according to a preferred embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a device according to a second preferred embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a device in accordance with a third preferred embodiment of the present invention;
FIG. 10 is a schematic cross-sectional structure of a device according to a comparative example of the present invention;
FIG. 11 is a graph showing the electric field distribution of the device of the preferred embodiment 1 of the present invention and the device of the comparative example 1;
In the drawings, 1 substrate; 2a laminated structure; 20 nucleation layers; a 21 buffer layer; 22 channel layers; a 23 barrier layer; 231 drain electrode holes; 232 source electrode holes; 3 drain electrode; a4 source electrode; 5 a first dielectric layer; 6 gate electrode; 61 gate electrode holes; 7 a second dielectric layer; 8, a semiconductor field plate; 81 grooves; a 01 substrate; 02 a buffer layer; 03a channel layer; 04 a barrier layer; 05 a first dielectric layer; 06 a second dielectric layer; 07 a third dielectric layer; 08 a fourth dielectric layer; 09 gate electrode; 010 source electrode; 011 drain electrode.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The traditional D-mode GaN HEMT device has two structures, namely an active field plate and a grid field plate, and the field plates are characterized by fixed low voltage (grid negative voltage or source zero voltage) V 0. When the device is turned off by supplying negative voltage V 1 to the gate terminal, the two-dimensional electron gas under the gate is depleted, and the potential V 2 under the first field plate adjacent to the gate starts to rise. When V 2-V0＝ε0ε Dielectric layer /(S*d First field plate ) the two-dimensional electron gas under the first field plate is depleted and its potential no longer changes. The potential V 3 under field plate two adjacent to field plate one continues to rise, and likewise the potential under the second field plate no longer changes when V 3-V0＝ε0ε Dielectric layer /(S*d second field plate ). The method sequentially operates to form a plurality of electric field gradients, wherein the number of the electric field gradients is limited by the number of the field plates, and the number of the field plates of the traditional device is 1-4. Obviously, this approach is complex to machine and the electric field gradient is limited in several ways and the electric field is not uniformly distributed.
The basic principle of the invention is as follows: a D-mode GaN HEMT with a semiconductor field plate, which can be understood as the resistance connected between the gate drain or source drain, has a resistivity that falls within the semiconductor category. The low voltage end of the field plate (resistor) is also fixed with a low voltage (grid negative voltage or source zero voltage) V 0, and the high voltage end of the field plate (resistor) is connected with the drain electrode Vd. When the device is turned off by supplying negative pressure V 1 to the gate end, two-dimensional electron gas under the gate is exhausted, the voltage at the outer side of the gate and the voltage at the drain end are integrally increased, the semiconductor field plate generates uniform gradual change potential due to the high resistance characteristic of the semiconductor field plate, and the gradual change potential integrally floats up uniformly along with the increase of the voltage at the drain end. The voltage of the field plate (resistor) at any position between the gate and the drain is proportional to the voltage of the drain terminal and proportional to the distance from the drain terminal to the gate, the electric field of the two-dimensional electron gas below the field plate is clamped at Vy, vy-vx=epsilon 0ε Dielectric layer /(S*d A first dielectric layer ) at any point between the gate and the drain, and the Vy realizes the electric potential which is uniformly graded from the gate to the drain because the Vx is graded.
Therefore, the invention realizes ideal uniform gradient potential, solves the problem of dielectric layer breakdown reliability failure caused by high electric field and the problem of dielectric layer charge trapping caused by high electric field strength, and simultaneously has simpler preparation process of the field plate. See the following examples for specific schemes:
Example 1 device Structure
As shown in fig. 7, the device including a semiconductor field plate in this embodiment includes a drain electrode, a source electrode, a gate electrode, a field plate made of a semiconductor material, and a substrate, a stacked structure and a first dielectric layer sequentially disposed from bottom to top, where the drain electrode and the source electrode are disposed in the stacked structure and the first dielectric layer, and the gate electrode is disposed in the first dielectric layer; the field plate is positioned above the first dielectric layer, and two ends of the field plate are respectively connected with the gate electrode and the drain electrode.
The resistivity of the field plate is 1e 2-1 e6 omega.m. The semiconductor material is silicon and/or germanium.
The field plate is prepared by the following method: and growing a semiconductor material on the first dielectric layer to form a semiconductor field plate, and simultaneously enabling two ends of the semiconductor field plate to be respectively connected with a drain electrode and a gate electrode.
Example 2 device Structure
The device structure including the semiconductor field plate in this embodiment is substantially identical to that of embodiment 1, except that: the field plate in this embodiment has a groove formed along the thickness direction of the field plate, and the depth of the groove is smaller than the thickness of the field plate, i.e., the field plate has a groove which does not penetrate the thickness direction of the field plate, as shown in fig. 8.
The internal resistance of the field plate is high, the low-voltage end (source end or gate end) and the high-voltage drain end are connected, and the grooves are introduced, so that the distribution adjustment of the internal resistance of the field plate is realized, the potential distribution adjustment in the field plate is further realized, and the potential distribution adjustment of the two-dimensional electron gas below is further converted. The field plate at the groove is thinned, the resistance becomes larger, and the pressure difference at the two sides of the groove becomes larger.
The number, the spacing and the depth of the grooves can be adjusted according to practical conditions, the number is preferably 1-50, the spacing is 0.1-30um, and the depth of the grooves is 10% -90% of the total thickness of the field plate. And the electric field peak is further reduced through the condition optimization of the grooves, so that the electric field distribution optimization is realized. The number of grooves in this embodiment is 4.
Example 3 device Structure
The device structure including the semiconductor field plate in this embodiment is substantially identical to that of embodiment 1, except that: in this embodiment, two ends of the semiconductor field plate are respectively connected to the source electrode and the drain electrode. So that when the device is turned off, the semiconductor field plate produces a gradual change in potential from the source electrode potential to the drain electrode potential to tailor the electric field distribution between the gate and drain.
Specifically, in this embodiment, a second dielectric layer is covered over the first dielectric layer and the gate electrode, and the field plate is located on the second dielectric layer.
Example 4 preparation method of device
The embodiment provides a method for preparing the device in the embodiment 1, which specifically includes the following steps:
Step one, forming a laminated structure
As shown in fig. 1, nitride epitaxial growth is performed on a substrate 1, and a nucleation layer 20, a buffer layer 21, a channel layer 22, and a barrier layer 23 are sequentially formed, and the material is selected from group III nitride materials such as GaN, alGaN, alN, alGaNInN. The nucleation layer 20, the buffer layer 21, the channel layer 22 and the barrier layer 23 constitute a stacked structure 2, thereby constituting a complete semiconductor epitaxial layer structure, and being capable of forming a high-concentration two-dimensional electron gas at a heterojunction interface between the channel layer 22 and the barrier layer 23, generating a conductive channel.
The substrate 1 is one or more combinations selected from silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing group III nitride materials.
Step two, forming an electrode
A source electrode hole 232 and a drain electrode hole 231 are formed in the epitaxial layer barrier layer 23 by patterning etching, as shown in fig. 2. And filling metal in the source electrode hole 232 and the drain electrode hole 231, wherein the metal comprises one or more of Ti, al, tiN, au, alCu, alSiCu, the filling modes comprise injection, sputtering and the like, and annealing to form ohmic contacts, so as to respectively form a source electrode 4 and a drain electrode 3, as shown in fig. 3.
Step three, forming a first dielectric layer and a gate electrode
A first dielectric layer 5, shown in fig. 4, is formed by depositing one or more combinations of SiN, siO 2、SiON、Al2O3 over the barrier layer 23 and etching a gate electrode hole 61, shown in fig. 5. The first dielectric layer 5 is filled with a metal, which includes one or more combinations of Ti, al, tiN, au, alCu, alSiCu, by implantation, sputtering, or the like. And the excess metal is etched away by a patterning process to form a gate electrode 7, as shown in fig. 6.
Step four, forming a semiconductor field plate
As shown in fig. 7, a semiconductor material, including silicon, germanium, etc., is grown on the first dielectric layer 5 to form a semiconductor field plate. The method specifically refers to the existing method of preparing amorphous silicon by adopting a silane thermal decomposition method or a Siemens method, forming a semiconductor field plate on the first dielectric layer 5, enabling the resistivity of the semiconductor field plate to be 1e 2-1 e6 omega.m, and simultaneously connecting a drain electrode and a gate electrode at two ends. When the device is turned off, potential gradually changing from the potential of the gate electrode to the potential of the drain electrode is generated in the semiconductor field plate, and electric field distribution between the gate and the drain is regulated.
In some embodiments, such as embodiment 2, the semiconductor field plate 8 has grooves with a depth less than the thickness of the field plate, as shown in fig. 8. Then, after the semiconductor field plate is formed, a groove is etched on the semiconductor field plate to realize the change of the resistance value of the semiconductor field plate, so that the trend of gradual potential change from the potential of the gate electrode to the potential of the drain electrode generated by the semiconductor field plate is further regulated, and the electric field distribution between the gate and the drain is regulated.
Comparative example 1
The device structure in this comparative example is a conventional three electric field distribution, and the specific structure is shown in fig. 10, and includes a substrate 01, a buffer layer 02, a channel layer 03, a barrier layer 04, a first dielectric layer 05, a second dielectric layer 06, a third dielectric layer 07, a fourth dielectric layer 08, a gate electrode 09, a source electrode 010, and a drain electrode 011. The substrate 01, the buffer layer 02, the channel layer 03, the barrier layer 04, the first dielectric layer 05, the second dielectric layer 06, the third dielectric layer 07, and the fourth dielectric layer 08 are sequentially disposed from bottom to top, the source electrode 010 and the drain electrode 011 are disposed in the barrier layer 04, the first dielectric layer 05, the second dielectric layer 06, the third dielectric layer 07, and the fourth dielectric layer 08, and the gate electrode 09 is disposed in the first dielectric layer 05, the second dielectric layer 06, the third dielectric layer 07, and the fourth dielectric layer 08.
Testing and results
The electric field simulation was performed on the device in example 1 and the device in comparative example 1, and the results are shown in fig. 11. The results of fig. 11 show that embodiment 1 of the present invention can better improve electric field distribution, reduce electric field spikes, and improve the reliability of the device under high voltage.
The device with the semiconductor field plate structure comprises a field plate made of semiconductor material, wherein one end of the field plate is connected with a drain electrode, and the other end of the field plate is connected with a gate electrode or a source electrode, so that uniform gradient potential is formed on the field plate when the device is turned off; the potential difference between the field plate and the two-dimensional electron gas below is effectively controlled, the electric field distribution is effectively improved, the problems that the dielectric layer breaks down and the reliability fails due to the high electric field and the dielectric layer traps charges due to the high electric field strength are solved, and meanwhile, the preparation process of the field plate is simpler.
The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and are not intended to limit the scope of the present invention to those skilled in the art to understand the present invention and implement the same. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (10)
1. The device comprises a drain electrode, a source electrode, a gate electrode and a field plate, wherein two ends of the field plate are respectively connected with the source electrode and the drain electrode or the gate electrode and the drain electrode, and the field plate is made of a semiconductor material.
2. The device of claim 1, comprising a substrate, a stacked structure, and a first dielectric layer disposed in that order from bottom to top, wherein the drain electrode, the source electrode are disposed in the stacked structure and the first dielectric layer, and the gate electrode is disposed in the first dielectric layer; the field plate is located above the first dielectric layer.
3. The device of claim 2, wherein the field plate connects the source and drain electrodes, a second dielectric layer is covered over the first dielectric layer or gate electrode, and the field plate is located over the second dielectric layer.
4. The device of claim 1, wherein the field plate has a recess formed therein along a thickness direction of the field plate, and wherein a depth of the recess is smaller than a thickness of the field plate.
5. The device of claim 4, wherein the number of grooves is 1-50 and the pitch is 0.1-30um, and the depth of the grooves is 10% -90% of the thickness of the field plate.
6. The device of claim 1, wherein the field plate is prepared by the method of: and growing a semiconductor material on the first dielectric layer to form a semiconductor field plate, and simultaneously enabling two ends of the semiconductor field plate to be respectively connected with a drain electrode and a gate electrode or a drain electrode and a source electrode.
7. The device of claim 1, wherein the field plate has a thickness of 1-2000nm and a resistivity of 1e 2-1 e6 Ω.m.
8. The device of any of claims 1-7, wherein the semiconductor material is silicon and/or germanium.
9. A method of manufacturing a device as claimed in any one of claims 1 to 8, comprising the steps of:
Performing nitride epitaxial growth on a substrate, and sequentially forming a nucleation layer, a buffer layer, a channel layer and a barrier layer, wherein the nucleation layer, the buffer layer, the channel layer and the barrier layer form a laminated structure;
Etching a source electrode hole and a drain electrode hole on the barrier layer;
filling metal in the source electrode hole and the drain electrode hole, and annealing to form ohmic contact to form a source electrode and a drain electrode respectively;
depositing a first dielectric layer above the barrier layer and etching a gate electrode hole;
Filling metal on the dielectric layer and etching redundant metal to form a gate electrode;
And growing a semiconductor material on the first dielectric layer to form a semiconductor field plate, and simultaneously enabling two ends of the semiconductor field plate to be respectively connected with a drain electrode, a gate electrode or a drain electrode and a source electrode to obtain the device.
10. The method of manufacturing as claimed in claim 9, further comprising the step of providing a recess in the semiconductor field plate: patterning is performed after the formation of the semiconductor field plate, and grooves are etched in the semiconductor field plate.
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| CN202410028745.2A CN117976701A (en) | 2024-01-09 | 2024-01-09 | Device containing semiconductor field plate and preparation method thereof |
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| CN202410028745.2A CN117976701A (en) | 2024-01-09 | 2024-01-09 | Device containing semiconductor field plate and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102779858A (en) * | 2012-07-30 | 2012-11-14 | 江苏能华微电子科技发展有限公司 | Power diode device and preparation method thereof |
| US20130056753A1 (en) * | 2011-09-06 | 2013-03-07 | Grigory Simin | Semiconductor Device with Low-Conducting Field-controlling Element |
| US20150155358A1 (en) * | 2013-12-02 | 2015-06-04 | International Rectifier Corporation | Group III-V Transistor with Semiconductor Field Plate |
| US9761675B1 (en) * | 2015-01-08 | 2017-09-12 | National Technology & Engineering Solutions Of Sandia, Llc | Resistive field structures for semiconductor devices and uses therof |
| CN215869394U (en) * | 2021-12-31 | 2022-02-18 | 芯众享(成都)微电子有限公司 | Gallium nitride HEMT device with electric field regulation between source and drain |
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- 2024-01-09 CN CN202410028745.2A patent/CN117976701A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130056753A1 (en) * | 2011-09-06 | 2013-03-07 | Grigory Simin | Semiconductor Device with Low-Conducting Field-controlling Element |
| CN102779858A (en) * | 2012-07-30 | 2012-11-14 | 江苏能华微电子科技发展有限公司 | Power diode device and preparation method thereof |
| US20150155358A1 (en) * | 2013-12-02 | 2015-06-04 | International Rectifier Corporation | Group III-V Transistor with Semiconductor Field Plate |
| US9761675B1 (en) * | 2015-01-08 | 2017-09-12 | National Technology & Engineering Solutions Of Sandia, Llc | Resistive field structures for semiconductor devices and uses therof |
| CN215869394U (en) * | 2021-12-31 | 2022-02-18 | 芯众享(成都)微电子有限公司 | Gallium nitride HEMT device with electric field regulation between source and drain |
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