CN117976538A - Method for forming insulated gate bipolar transistor - Google Patents
Method for forming insulated gate bipolar transistor Download PDFInfo
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- CN117976538A CN117976538A CN202410084434.8A CN202410084434A CN117976538A CN 117976538 A CN117976538 A CN 117976538A CN 202410084434 A CN202410084434 A CN 202410084434A CN 117976538 A CN117976538 A CN 117976538A
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- oxide layer
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- forming
- insulated gate
- bipolar transistor
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 150000002500 ions Chemical class 0.000 claims abstract description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention provides a forming method of an insulated gate bipolar transistor, which comprises the following steps: forming a trench in the substrate; forming an oxide layer on the surface of the substrate and the inner wall of the groove, wherein the oxide layer seals the opening of the groove; forming a photoresist layer on the oxide layer; removing part of the photoresist layer and part of the oxide layer in sequence to expose the opening of the groove, and reserving an oxide layer with a certain thickness on the surface of the substrate at two sides of the groove; implanting ions into the substrate at the bottom of the trench through the opening of the trench to form an ion region; and removing the remaining photoresist layer and the remaining oxide layer. The invention forms a thick enough oxide layer to close the opening of the groove, and when part of the photoresist layer is removed to expose the opening of the groove, the substrate is still covered by part of thick oxide layer. Therefore, the invention only forms an ion region in the substrate at the bottom of the groove, thereby not causing the pollution of other parts of the insulated gate bipolar transistor by ions and improving the quality of the insulated gate bipolar transistor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of an insulated gate bipolar transistor.
Background
The insulated gate bipolar Transistor (Insulated Gate Bipolar Transistor, IGBT) is a composite fully controlled voltage driven power semiconductor device composed of bipolar Transistor (Bipolar Junction Transistor, BJT) and insulated gate field effect Transistor (Metal OxideSemiconductor, MOS), and has the advantages of both high input impedance of Metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT Transistor, MOSFET) and low turn-on voltage drop of power Transistor (Giant Transistor, GTR). The back side process of IGBT devices has undergone a development history from Non-Punch Through (NPT) to Punch Through (PT) to Field Stop (FS or SPT); the front-side process of IGBT devices goes from planar (planar) to trench gate (TRENCH GATE).
Some IGBT products need to be subjected to ion implantation at the bottom of a specific groove, so that the performance of the device is improved. In the prior art, the method for forming the IGBT comprises the following steps: referring to fig. 1, fig. 1 is a schematic view of a portion of an insulated gate bipolar transistor after forming a trench in the prior art, and a substrate 110 is provided first, where the substrate 110 may be a wafer. Next, the substrate 110 is etched to a partial thickness, and a trench 120 is formed in the substrate 110. Next, referring to fig. 2, fig. 2 is a schematic diagram of a portion of a structure of an insulated gate bipolar transistor after forming an oxide layer in the prior art, a thinner oxide layer 130 is formed in the trench 120, the oxide layer 130 covers the inner wall (including the sidewall and the bottom wall) of the trench 120 and the surface of the substrate 110, and the oxide layer 130 is formed as a thin layer along the inner wall in the trench 120. Next, a photoresist layer 140 is formed on the surface of the oxide layer 130, and the photoresist layer 140 is made to fill the trench 120. Next, referring to fig. 3, fig. 3 is a schematic diagram of a portion of a structure of an insulated gate bipolar transistor after forming an ion region in the prior art, wherein the photoresist layer 140 over the trench 120 and the photoresist layer 140 in the trench 120 to be implanted with ions are removed, and ions are implanted into the substrate 110 at the bottom of the trench 120 to form an ion region 150.
However, in the prior art method, when the photoresist layer 140 is removed, the photoresist layer 140 on the substrate 110 at both sides of the trench is removed, resulting in exposing the oxide layer 130 on the surface of part of the substrate 110. In the case of ion implantation, the entire surface of the device is implanted, and the oxide layer 130 on the substrate 110 on both sides of the trench 120 is relatively thin, so that the ions cannot be prevented from entering the underlying substrate 110. Thus, ions are implanted into the substrate 110 on both sides of the trench 120 and near the surface of the substrate 110. Finally, ion regions are formed where the ion regions should not be formed, resulting in ion contamination of other parts of the Insulated Gate Bipolar Transistor (IGBT). Quality problems may occur in Insulated Gate Bipolar Transistors (IGBTs), which degrade the quality of the Insulated Gate Bipolar Transistors (IGBTs).
Disclosure of Invention
The invention aims to provide a method for forming an insulated gate bipolar transistor, which can only form an ion region in a substrate at the bottom of a groove, and can not cause other parts of the insulated gate bipolar transistor to be polluted by ions, so that the quality of the insulated gate bipolar transistor can be improved.
In order to achieve the above object, the present invention provides a method for forming an insulated gate bipolar transistor, comprising:
Providing a substrate;
forming a trench in the substrate;
Forming an oxide layer on the surface of the substrate and the inner wall of the groove, wherein the oxide layer seals the opening of the groove;
Forming a photoresist layer on the oxide layer;
sequentially removing part of the photoresist layer and part of the oxide layer to expose the opening of the groove, and leaving a certain thickness of the oxide layer on the surface of the substrate at two sides of the groove;
implanting ions into the substrate at the bottom of the groove through the opening of the groove to form an ion region; and
And removing the residual photoresist layer and the residual oxide layer.
Optionally, in the method for forming an insulated gate bipolar transistor, the substrate includes a wafer.
Optionally, in the method for forming an insulated gate bipolar transistor, the oxide layer includes silicon dioxide.
Optionally, in the method for forming an insulated gate bipolar transistor, an oxide layer is formed on the surface of the substrate and the inner wall of the trench by adopting a PECVD method, and the oxide layer seals the opening of the trench.
Optionally, in the method for forming an insulated gate bipolar transistor, the method for sequentially removing a portion of the photoresist layer and a portion of the oxide layer includes: patterning the photoresist layer; and etching and removing part of the oxide layer by using the patterned photoresist layer.
Optionally, in the method for forming an insulated gate bipolar transistor, a part of the oxide layer is removed by wet etching with a patterned photoresist layer.
Optionally, in the method for forming an insulated gate bipolar transistor, ash is removed from the remaining photoresist layer.
Optionally, in the method for forming an insulated gate bipolar transistor, the remaining oxide layer is removed by wet etching.
Optionally, in the method for forming an insulated gate bipolar transistor, ions are implanted into the substrate perpendicular to the surface of the substrate and toward the bottom of the trench.
Optionally, in the method for forming an insulated gate bipolar transistor, the thickness of the oxide layer is 0.8 μm to 3 μm.
The method for forming the insulated gate bipolar transistor provided by the invention comprises the following steps: providing a substrate; forming a trench in the substrate; forming an oxide layer on the surface of the substrate and the inner wall of the groove, wherein the oxide layer seals the opening of the groove; forming a photoresist layer on the oxide layer; removing part of the photoresist layer and part of the oxide layer in sequence to expose the opening of the groove, and reserving an oxide layer with a certain thickness on the surface of the substrate at two sides of the groove; implanting ions into the substrate at the bottom of the trench through the opening of the trench to form an ion region; and removing the remaining photoresist layer and the remaining oxide layer. When ions are injected into the substrate at the bottom of the groove, a sufficiently thick oxide layer is formed to close the opening of the groove, and when part of photoresist layer is removed to expose the opening of the groove, the oxide layer on the substrate at two sides of the groove is etched, but the substrate is still covered by the partially thick oxide layer. Then, ions are implanted into the substrate at the bottom of the trench from the opening of the trench to form ion regions, and at this time, the substrates at the two sides of the trench are not implanted with ions due to the coverage of the oxide layer. Therefore, the invention only forms an ion region in the substrate at the bottom of the groove, and other parts of the insulated gate bipolar transistor are not polluted by ions, thereby improving the quality of the insulated gate bipolar transistor.
Drawings
Fig. 1 is a schematic view of a part of a prior art insulated gate bipolar transistor after forming a trench;
fig. 2 is a schematic diagram of a portion of a prior art insulated gate bipolar transistor after an oxide layer is formed;
fig. 3 is a schematic view of a part of the structure of an insulated gate bipolar transistor after forming an ion region according to the prior art;
fig. 4 is a flowchart of a method of forming an insulated gate bipolar transistor according to an embodiment of the present invention;
fig. 5 is a schematic view of a portion of an insulated gate bipolar transistor after forming a trench according to an embodiment of the present invention;
fig. 6 is a schematic view of a portion of an insulated gate bipolar transistor after forming an oxide layer according to an embodiment of the present invention;
fig. 7 is a schematic view of a part of an insulated gate bipolar transistor after opening a trench according to an embodiment of the present invention;
fig. 8 is a schematic view of a portion of an insulated gate bipolar transistor after forming an ion region according to an embodiment of the present invention;
Fig. 9 is a schematic diagram of a portion of an igbt after removing the remaining oxide layer according to an embodiment of the present invention;
In the figure: 110-substrate, 120-trench, 130-oxide, 140-photoresist, 150-ion region, 210-substrate, 220-trench, 230-oxide, 240-photoresist, 250-ion region.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Also, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.
Referring to fig. 4, the present invention provides a method for forming an insulated gate bipolar transistor, which includes:
s11: providing a substrate;
s12: forming a trench in the substrate;
S13: forming an oxide layer on the surface of the substrate and the inner wall of the groove, wherein the oxide layer seals the opening of the groove;
S14: forming a photoresist layer on the oxide layer;
s15: removing part of the photoresist layer and part of the oxide layer in sequence to expose the opening of the groove, and reserving an oxide layer with a certain thickness on the surface of the substrate at two sides of the groove;
s16: implanting ions into the substrate at the bottom of the trench through the opening of the trench to form an ion region; and
S17: and removing the residual photoresist layer and the residual oxide layer.
Referring to fig. 5, fig. 5 is a schematic view of a portion of an insulated gate bipolar transistor after forming a trench according to an embodiment of the present invention, first, a substrate 210 is provided, and a material selected for the substrate 210 may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors, the substrate 200 may also be a multilayer structure of these semiconductor materials or be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeO), or the like. The embodiment of the invention can select a silicon substrate, such as a wafer. Next, the substrate 210 is etched to a partial thickness toward the inside of the substrate 210 perpendicularly to the surface of the substrate 210, thereby forming a plurality of trenches 220 in the substrate 210, and the etching method may be a dry etching method.
Next, referring to fig. 6, fig. 6 is a schematic diagram illustrating a portion of an igbt after an oxide layer is formed according to an embodiment of the invention. An oxide layer 230 is formed on the inner wall of the trench 220 and the surface of the substrate 210, the oxide layer 230 comprises silicon oxide, and the oxide layer 230 of the embodiment of the present invention may be silicon dioxide. The thickness of the oxide layer 230 is 0.8 μm to 3 μm, for example, the oxide layer 230 of the embodiment of the present invention may be 1 μm, and in other embodiments of the present invention, the oxide layer 230 may be of other thicknesses. In the embodiment of the present invention, the oxide layer 230 is formed on the surface of the substrate 210 and the inner wall of the trench 220 by adopting a plasma chemical vapor deposition (PECVD) method, the oxide layer 230 closes the opening of the trench 220, and in other embodiments of the present invention, other methods may be adopted to form the oxide layer 230. At this time, the trench 220 is not filled with the oxide layer 230, and the thickness of the oxide layer 230 at the closed portion of the trench 220 is smaller than the thickness of the oxide layer 230 on the substrate 210 at both sides of the trench 220 due to the space of the trench 220.
Next, referring to fig. 7, fig. 7 is a schematic diagram of a portion of an igbt after opening a trench according to an embodiment of the invention. A photoresist layer 240 is formed on the surface of the oxide layer 230, and a photoresist layer 240 may be formed on the surface of the oxide layer 230 by depositing a photoresist. Next, the photoresist layer 240 is patterned in an exposed form such that the photoresist layer 240 over the trenches 220 where the ion regions are to be formed is removed to form a patterned photoresist layer. Next, a portion of the oxide layer 230 is removed by etching with the patterned photoresist layer. Specifically, the patterned photoresist layer is wet etched to remove a portion of the oxide layer 230. The oxide layer 230 is removed so long as an opening is present over the trench 220 through which ions can be implanted. Since the thickness of the oxide layer 230 at the closed opening is smaller than the thickness of the oxide layer 230 on the substrate 210 at both sides of the trench 220, after the oxide layer 230 at the opening is removed, the oxide layer 230 on the substrate 210 at both sides of the trench 220 still remains with a certain thickness of the oxide layer 230.
Next, referring to fig. 8, fig. 8 is a schematic diagram illustrating a portion of an igbt after forming an ion region according to an embodiment of the invention. Ions are implanted into the substrate 210 at the bottom of the trench 220 to form an ion region 250 in the substrate 210 at the bottom of the trench 220. Ions are implanted into the substrate 210 at the bottom of the trench 220 perpendicular to the surface of the substrate 210. Thus, ion implantation is performed over the entire surface of the device at this time. Since the other places except the trench 220 where the ion region is to be formed are covered by the photoresist layer 240 and the oxide layer 230, ions do not enter the other substrate 210 except the trench 220 where the ion region is to be formed. For example, the oxide layer 230 is left on the substrate 210 on both sides of the trench 220 with sufficient thickness so that ions are prevented from entering the substrate 210 therein.
Next, referring to fig. 9, fig. 9 is a schematic diagram of a portion of an igbt after removing a remaining oxide layer according to an embodiment of the invention. The remaining photoresist layer 240 is removed, and the remaining photoresist layer 240 may be removed using an ash process, i.e., the ash removed patterned photoresist layer. Next, the wet etch removes the remaining oxide layer 230, and it is found that eventually ion regions 250 are formed only in the substrate 210 at the bottom of the trenches 220 and adjacent to the trenches 220. Finally, other structures of the insulated gate bipolar transistor, such as insulated gate formation, may be performed. The method for forming the subsequent structure is the prior art, and will not be described here in detail.
In summary, in the method for forming an insulated gate bipolar transistor provided in the embodiment of the present invention, the method includes: providing a substrate; forming a trench in the substrate; forming an oxide layer on the surface of the substrate and the inner wall of the groove, wherein the oxide layer seals the opening of the groove; forming a photoresist layer on the oxide layer; removing part of the photoresist layer and part of the oxide layer in sequence to expose the opening of the groove, and reserving an oxide layer with a certain thickness on the surface of the substrate at two sides of the groove; implanting ions into the substrate at the bottom of the trench through the opening of the trench to form an ion region; and removing the remaining photoresist layer and the remaining oxide layer. When ions are injected into the substrate at the bottom of the groove, a sufficiently thick oxide layer is formed to close the opening of the groove, and when part of photoresist layer is removed to expose the opening of the groove, the oxide layer on the substrate at two sides of the groove is etched, but the substrate is still covered by the partially thick oxide layer. Then, ions are implanted into the substrate at the bottom of the trench from the opening of the trench to form ion regions, and at this time, the substrates at the two sides of the trench are not implanted with ions due to the coverage of the oxide layer. Therefore, the invention only forms an ion region in the substrate at the bottom of the groove, and other parts of the insulated gate bipolar transistor are not polluted by ions, thereby improving the quality of the insulated gate bipolar transistor.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method for forming an insulated gate bipolar transistor, comprising:
Providing a substrate;
forming a trench in the substrate;
Forming an oxide layer on the surface of the substrate and the inner wall of the groove, wherein the oxide layer seals the opening of the groove;
Forming a photoresist layer on the oxide layer;
Sequentially removing part of the photoresist layer and part of the oxide layer to expose the opening of the groove, and leaving a certain thickness of the oxide layer on the surface of the substrate at two sides of the groove;
implanting ions into the substrate at the bottom of the groove through the opening of the groove to form an ion region; and
And removing the residual photoresist layer and the residual oxide layer.
2. The method of forming an insulated gate bipolar transistor of claim 1, wherein said substrate comprises a wafer.
3. The method of forming an insulated gate bipolar transistor of claim 1 wherein said oxide layer comprises silicon dioxide.
4. The method of forming an insulated gate bipolar transistor according to claim 1, wherein an oxide layer is formed on a surface of the substrate and an inner wall of the trench by a PECVD method, the oxide layer closing an opening of the trench.
5. The method of forming an insulated gate bipolar transistor according to claim 1, wherein the method of sequentially removing a portion of the photoresist layer and a portion of the oxide layer comprises:
Patterning the photoresist layer; and
And etching and removing part of the oxide layer by using the patterned photoresist layer.
6. The method of forming an igbt of claim 5 wherein the patterned photoresist layer is wet etched to remove a portion of the oxide layer.
7. The method of forming an insulated gate bipolar transistor of claim 1, wherein ash removes the remaining photoresist layer.
8. The method of forming an insulated gate bipolar transistor of claim 1, wherein wet etching removes the remaining oxide layer.
9. The method of forming an insulated gate bipolar transistor according to claim 1, wherein ions are implanted into the substrate at the bottom of the trench perpendicular to the surface of the substrate.
10. The method of forming an insulated gate bipolar transistor according to claim 1, wherein the oxide layer has a thickness of 0.8 μm to 3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410084434.8A CN117976538A (en) | 2024-01-19 | 2024-01-19 | Method for forming insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410084434.8A CN117976538A (en) | 2024-01-19 | 2024-01-19 | Method for forming insulated gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117976538A true CN117976538A (en) | 2024-05-03 |
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ID=90854752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410084434.8A Pending CN117976538A (en) | 2024-01-19 | 2024-01-19 | Method for forming insulated gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117976538A (en) |
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2024
- 2024-01-19 CN CN202410084434.8A patent/CN117976538A/en active Pending
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