CN116864396A - Method for manufacturing medium voltage device - Google Patents
Method for manufacturing medium voltage device Download PDFInfo
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- CN116864396A CN116864396A CN202310946084.7A CN202310946084A CN116864396A CN 116864396 A CN116864396 A CN 116864396A CN 202310946084 A CN202310946084 A CN 202310946084A CN 116864396 A CN116864396 A CN 116864396A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 58
- 150000004767 nitrides Chemical class 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000003475 lamination Methods 0.000 claims abstract description 23
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 10
- 230000008859 change Effects 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a manufacturing method of medium voltage devices, which comprises the steps of providing a substrate, forming STI (shallow trench isolation) on the substrate to define active areas of low voltage, medium voltage and high voltage device areas, and forming a gate oxide layer on the active areas of the low voltage, medium voltage and high voltage device areas; forming a lamination covering a gate oxide layer on a substrate, wherein the lamination consists of a gate polysilicon layer, a first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer which are sequentially stacked from bottom to top, and using photoetching and etching to enable part of the lamination and the gate oxide layer below the lamination to remain on an active region of a medium-voltage and high-voltage device to form a gate structure, and the other part of the lamination to remain on an active region of a low-voltage device and a part of the area of the STI adjacent to the active region of the low-voltage device; a first sidewall material layer is formed over the substrate overlying the remaining stack. The light doped drain ion implantation of the input/output region is a self-aligned process, so that the influence of the key size and superposition change of the light doped drain ion implantation on the device can be solved, and the uniformity of the device can be effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a medium-voltage device.
Background
The high-voltage device technology is mainly applied to a screen driving chip and mainly comprises low-voltage, medium-voltage and high-voltage parts, wherein the medium-voltage (8V) is mainly applied to source electrode driving of a screen light emitting unit, the proportion of the chip is large, the power consumption of the chip has great influence on the power consumption of the whole chip, and each high-voltage device technology platform takes the electric leakage of a medium-voltage device as a main challenge. In the technology of the 28nm technology node of the prior art, the electric leakage of the device is optimized mainly by increasing and thickness. The distance between the source region, the drain region and the silicide and the grid electrode can be effectively increased through the increase of the thickness of the side wall, and the method is a classical method for reducing the electric leakage of the device GIDL.
In the prior art, before the formation of the grid oxide layer of the medium-voltage device, the lightly doped drain of the input/output region is required to be injected, the channel part is blocked by photoresist, a photomask is arranged before the formation of the first side wall to block the first side wall of the grid region in the high-voltage device, the oxide layer is additionally arranged in the second side wall deposition, and meanwhile, a double-layer side wall photomask is additionally arranged, so that the side wall thickening of the medium-voltage device is realized through photoetching and etching. A gate oxide layer photoetching and etching process is arranged at the back of the substrate to remove the redundant oxide layer in the medium-voltage device area, but the process is complex, and the uniformity of the obtained device structure is poor.
In order to solve the above problems, a new method for manufacturing a medium voltage device needs to be proposed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a medium voltage device, which is used for solving the problems of complex manufacturing process and poor uniformity of the obtained device structure in the prior art.
To achieve the above and other related objects, the present invention provides a method of manufacturing a medium voltage device, comprising:
providing a substrate, wherein STI is formed on the substrate to define an active region of a low-voltage, medium-voltage and high-voltage device region, and a gate oxide layer is formed on the active region of the low-voltage, medium-voltage and high-voltage device region;
forming a lamination layer covering the gate oxide layer on the substrate, wherein the lamination layer consists of a gate polysilicon layer, a first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer which are stacked in sequence from bottom to top, and part of the lamination layer and the gate oxide layer below the lamination layer are reserved on an active area of the medium-voltage and high-voltage device to form a gate structure by photoetching and etching, and the other part of the lamination layer is reserved on the active area of the low-voltage device and a part of the area of the low-voltage device, which is close to the active area, on the STI;
forming a first side wall material layer covering the rest of the laminated layers on the substrate, forming a first photoresist layer on the first side wall material layer, photoetching and opening the first photoresist layer to define a lightly doped drain region of the input/output region of the medium voltage device, and doping the lightly doped drain region by utilizing ion implantation;
removing the first photoresist layer, forming an etching barrier layer covering the first side wall material layer, etching the etching barrier layer and the first side wall material layer below the etching barrier layer to the second nitride layer so that part of the first side wall material layer is exposed, removing the exposed first side wall material layer and the second oxide layer below the first side wall material layer, and removing the rest etching barrier layer;
forming a third oxide layer on the second nitride layer and the etching barrier layer, and then etching back the third oxide layer to form a second side wall structure on the etched laminated side wall;
removing the second side wall structures in the low-voltage device region and the high-voltage device region by means of photoetching and etching, and then etching back the second nitride layer and the first side wall material layer to remove the second nitride layer, wherein the first side wall material layer is formed into a first side wall structure;
removing the first side wall structure and the rest lamination layers on two side parts on the low-voltage device region by utilizing photoetching and etching to form a grid structure positioned on the low-voltage device region;
and step eight, forming a third side wall structure on the rest of the laminated side walls of the low-voltage device region and the high-voltage device region and the second side wall in the medium-voltage device region by utilizing deposition and etching.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, in the second step, the first and second oxide layers are made of silicon dioxide, and the first and second nitride layers are made of silicon nitride.
Preferably, the etching method in the second step is dry etching.
Preferably, the material of the first sidewall material layer in the third step is silicon nitride.
Preferably, the material of the etching barrier layer in the fourth step is photoresist or advanced film.
Preferably, in the fourth step, the etching barrier layer and the first sidewall material layer below the etching barrier layer are etched by using a wet etching method, so that part of the first sidewall material layer is exposed above the second nitride layer.
Preferably, in the fourth step, the exposed first sidewall material layer and the second oxide layer below the first sidewall material layer are removed by using a wet etching method.
Preferably, the etching back method in the fifth step is dry etching.
Preferably, in the sixth step, the second side wall structures in the low-voltage device region and the high-voltage device region are etched and removed by using a wet etching method.
Preferably, the method of etching back in the step six is dry etching.
Preferably, the etching method in the seventh step is dry etching.
Preferably, the method for forming a third sidewall structure on the remaining stacked sidewalls of the low-voltage device region, the high-voltage device region, and the second sidewall in the medium-voltage device region by deposition and etching in the eighth step includes: forming a third nitride layer covering the low-voltage, medium-voltage and high-voltage device regions on the substrate, and then etching back the third nitride layer to remain on the rest of the laminated side walls of the low-voltage device region and the high-voltage device region and the second side wall of the medium-voltage device region; depositing a fourth oxide layer, and etching back the fourth oxide layer to keep the fourth oxide layer on the side wall of the third nitride layer; and depositing a fourth nitride layer, and then etching the third nitride layer back to keep the third nitride layer on the side wall of the fourth oxide layer.
As described above, the method for manufacturing a medium voltage device of the present invention has the following advantageous effects:
the light doped drain ion implantation of the input/output region is a self-aligned process, so that the influence of the key size and superposition change of the light doped drain ion implantation on the device can be solved, and the uniformity of the device can be effectively improved. The process of the invention increases the grid etching of a medium voltage device region, but can reduce the grid oxide etching and side wall photoetching process, can effectively reduce the photomask, and has fewer steps. The added second side wall structure is arranged on the inner side of the third side wall structure, so that the width of the side wall can be effectively increased, and the electric leakage of the device GIDL is optimized.
Drawings
FIG. 1 is a schematic illustration of the process flow of the present invention;
FIG. 2 is a schematic view of a formed stack of the present invention;
FIG. 3 is a schematic diagram of an etch stack according to the present invention;
FIG. 4 is a schematic view of a first side wall material layer according to the present invention;
FIG. 5 is a schematic view of an implantation region defining a lightly doped drain according to the present invention;
FIG. 6 is a schematic diagram of forming an etch stop layer according to the present invention;
FIG. 7 is a schematic diagram of an etched barrier layer according to the present invention;
FIG. 8 is a schematic diagram illustrating formation of a third oxide layer according to the present invention;
FIG. 9 is a schematic diagram showing the formation of a second sidewall structure according to the present invention;
FIG. 10 is a schematic view of a second sidewall structure of the present invention with low-voltage regions and high-voltage regions removed;
FIG. 11 is a schematic diagram of a gate structure for forming a low voltage region and a high voltage region according to the present invention;
FIG. 12 is a schematic view illustrating formation of a third nitride layer according to the present invention;
fig. 13 is a schematic view illustrating formation of a third sidewall structure according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a method for manufacturing a medium voltage device, including:
referring to fig. 2, a substrate 100 is provided, STI 101 is formed on the substrate 100 to define active areas (not shown in the high-voltage device area diagram) of low-voltage, medium-voltage and high-voltage device areas, and a gate oxide layer 102 is formed on the active areas of the low-voltage, medium-voltage and high-voltage device areas, wherein the gate oxide layer 102 may be generally formed by a thermal oxidation method;
in an alternative embodiment, the substrate 100 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
Step two, forming a lamination covering the gate oxide layer 102 on the substrate 100, wherein the lamination consists of a gate polysilicon layer 103, a first nitride layer 104, a first oxide layer 105, a second nitride layer 106 and a second oxide layer 107 which are sequentially stacked from bottom to top, and forming a gate structure by using photoetching and etching so that part of the lamination and the gate oxide layer 102 below the lamination remain on an active area of a medium-voltage and high-voltage device, and the other part of the lamination remain on the active area of the low-voltage device and a part of the area of the STI 101 adjacent to the active area of the low-voltage device, so as to form a structure shown in fig. 3; specifically, a photoresist layer is formed on the second oxide layer 107, and then the photoresist layer is opened by photolithography, so that only etching areas in low-voltage, medium-voltage and high-voltage device areas are defined, the stack layer remained on the low-voltage device area covers the whole area of the low-voltage device area, and meanwhile, the redundant part of the gate oxide layer 102 in the medium-voltage device area can be removed, and then the second gate oxide layer 102 of the redundant part is not required to be removed by etching, so that one photomask can be saved.
In an alternative embodiment, the material of the first and second oxide layers in the second step is silicon dioxide, and the material of the first and second nitride layers is silicon nitride.
In an alternative embodiment, the etching in step two is performed by dry etching.
Step three, forming a first side wall material layer 108 covering the rest of the stack layer on the substrate 100 to form a structure shown in fig. 4, forming a first photoresist layer 109 on the first side wall material layer 108, opening the first photoresist layer 109 by photoetching to define a region of a low-doped drain of an input/output region of the medium-voltage device to form the structure shown in fig. 5, doping the structure by utilizing ion implantation to form the low-doped drain, and implanting the low-doped drain through self-alignment after a grid electrode is formed, so that the performance and uniformity of the device are ensured;
in an alternative embodiment, the material of the first sidewall material layer 108 in the third step is silicon nitride, which may be formed by atomic layer deposition or chemical vapor deposition.
Step four, removing the first photoresist layer 109, typically removing the remaining first photoresist layer 109 by ashing and wet cleaning, forming an etching barrier layer 110 covering the first sidewall material layer 108, forming a structure as shown in fig. 6, etching the etching barrier layer 110 to protect the active region and STI 101 under the etching barrier layer 110 and the first sidewall material layer 108 under the etching barrier layer to the second nitride layer 106 (for example, at a position in a height consistent with the second nitride layer 106 or above and below the second nitride layer 106) so that a portion of the first sidewall material layer 108 is exposed, removing the exposed first sidewall material layer 108 and the second oxide layer 107 under the first sidewall material layer, and removing the remaining etching barrier layer 110 to form a structure as shown in fig. 7;
in an alternative embodiment, the material of the etching stopper layer 110 in the fourth step is photoresist or advanced film (APF), and the remaining etching stopper layer 110 is removed by ashing and wet cleaning.
In an alternative embodiment, in the fourth step, the etching barrier layer 110 and the first sidewall material layer 108 below the etching barrier layer are etched by using a wet etching method to reach above the second nitride layer 106, so that a portion of the first sidewall material layer 108 is exposed.
In an alternative embodiment, the exposed first sidewall material layer 108 and the second oxide layer 107 thereunder are removed in step four by wet etching.
Step five, forming a third oxide layer on the second nitride layer 106 and the etching barrier layer 110 to form a structure shown in fig. 8, and then etching back the third oxide layer to form a second side wall structure 111 on the etched laminated side wall to form a structure shown in fig. 9, wherein the second side wall structure 111 is a side wall thickness increased in the medium-voltage device region, and the specific thickness is controlled by the thickness of the third oxide layer and the etching degree of the third oxide layer;
in an alternative embodiment, the method of etching back in the fifth step is dry etching.
Step six, removing the second side wall structure 111 in the low-voltage device region and the high-voltage device region by utilizing photoetching and etching, and then etching back the second nitride layer 106 and the first side wall material layer 108, so that the second nitride layer 106 is removed, and the first side wall material layer 108 is formed into a first side wall structure 112, and the structure shown in fig. 10 is formed; i.e., a photoresist layer is formed covering the entire substrate 100, then the low voltage device region and the high voltage device region are opened by photolithography, the exposed first sidewall structure 112 is removed by wet etching, then the photoresist layer is removed, and the second nitride layer 106 on the low voltage device region, the medium voltage device region and the high voltage device region is removed by dry etching.
In an alternative embodiment, in the sixth step, the second sidewall structure 111 located in the low-voltage device region and the high-voltage device region is etched and removed by using a wet etching method.
In an alternative embodiment, the method of etching back in step six is dry etching.
Step seven, removing the first side wall structure 112 and the rest lamination of two side parts on the low-voltage device region by utilizing photoetching and etching to form a grid structure positioned on the low-voltage device region, and forming a structure shown in fig. 11;
in an alternative embodiment, the method of etching in step seven is dry etching.
And step eight, forming a third side wall structure on the rest laminated side walls of the low-voltage device region and the high-voltage device region and the second side wall in the medium-voltage device region by utilizing deposition and etching.
In an alternative embodiment, the method for forming the third sidewall structure on the remaining stacked sidewalls of the low-voltage device region and the high-voltage device region and the second sidewall in the medium-voltage device region by deposition and etching in the eighth step includes: forming a third nitride layer 113 covering the low-voltage, medium-voltage and high-voltage device regions on the substrate, forming a structure as shown in fig. 12, and then etching back the third nitride layer 113 to remain on the remaining laminated side walls of the low-voltage device region and the high-voltage device region and on the second side wall in the medium-voltage device region; depositing a fourth oxide layer 114, and etching back the fourth oxide layer 114 to remain on the side wall of the third nitride layer 113; the fourth nitride layer 115 is deposited, and then the third nitride layer 113 is etched back to remain on the sidewall of the fourth oxide layer 114, so as to form a structure as shown in fig. 13, wherein the materials of the third nitride layer and the fourth nitride layer are silicon nitride, the material of the fourth oxide layer 114 is silicon dioxide, and the etching back methods are all dry etching methods.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the lightly doped drain ion implantation in the input/output region is a self-aligned process, which can solve the problem of the influence of the critical dimension and the superposition variation of the lightly doped drain ion implantation on the device, and can effectively improve the uniformity of the device. The process of the invention increases the grid etching of a medium voltage device region, but can reduce the grid oxide etching and side wall photoetching process, can effectively reduce the photomask, and has fewer steps. The added second side wall structure is arranged on the inner side of the third side wall structure, so that the width of the side wall can be effectively increased, and the electric leakage of the device GIDL is optimized. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A method of manufacturing a medium voltage device, comprising at least:
providing a substrate, wherein STI is formed on the substrate to define an active region of a low-voltage, medium-voltage and high-voltage device region, and a gate oxide layer is formed on the active region of the low-voltage, medium-voltage and high-voltage device region;
forming a lamination layer covering the gate oxide layer on the substrate, wherein the lamination layer consists of a gate polysilicon layer, a first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer which are stacked in sequence from bottom to top, and part of the lamination layer and the gate oxide layer below the lamination layer are reserved on an active area of the medium-voltage and high-voltage device to form a gate structure by photoetching and etching, and the other part of the lamination layer is reserved on the active area of the low-voltage device and a part of the area of the low-voltage device, which is close to the active area, on the STI;
forming a first side wall material layer covering the rest of the laminated layers on the substrate, forming a first photoresist layer on the first side wall material layer, photoetching and opening the first photoresist layer to define a lightly doped drain region of the input/output region of the medium voltage device, and doping the lightly doped drain region by utilizing ion implantation;
removing the first photoresist layer, forming an etching barrier layer covering the first side wall material layer, etching the etching barrier layer and the first side wall material layer below the etching barrier layer to the second nitride layer so that part of the first side wall material layer is exposed, removing the exposed first side wall material layer and the second oxide layer below the first side wall material layer, and removing the rest etching barrier layer;
forming a third oxide layer on the second nitride layer and the etching barrier layer, and then etching back the third oxide layer to form a second side wall structure on the etched laminated side wall;
removing the second side wall structures in the low-voltage device region and the high-voltage device region by means of photoetching and etching, and then etching back the second nitride layer and the first side wall material layer to remove the second nitride layer, wherein the first side wall material layer is formed into a first side wall structure;
removing the first side wall structure and the rest lamination layers on two side parts on the low-voltage device region by utilizing photoetching and etching to form a grid structure positioned on the low-voltage device region;
and step eight, forming a third side wall structure on the rest of the laminated side walls of the low-voltage device region and the high-voltage device region and the second side wall in the medium-voltage device region by utilizing deposition and etching.
2. The method of manufacturing a medium voltage device according to claim 1, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method of manufacturing a medium voltage device according to claim 1, wherein: in the second step, the materials of the first and second oxide layers are silicon dioxide, and the materials of the first and second nitride layers are silicon nitride.
4. The method of manufacturing a medium voltage device according to claim 1, wherein: and step two, the etching method is dry etching.
5. The method of manufacturing a medium voltage device according to claim 1, wherein: and in the third step, the material of the first side wall material layer is silicon nitride.
6. The method of manufacturing a medium voltage device according to claim 1, wherein: and in the fourth step, the material of the etching barrier layer is photoresist or advanced film.
7. The method of manufacturing a medium voltage device according to claim 1, wherein: and step four, etching the etching barrier layer and the first side wall material layer below the etching barrier layer to the position above the second nitride layer by using a wet etching method so that part of the first side wall material layer is exposed.
8. The method of manufacturing a medium voltage device according to claim 1, wherein: and step four, removing the exposed first side wall material layer and the second oxide layer below the first side wall material layer by utilizing a wet etching method.
9. The method of manufacturing a medium voltage device according to claim 1, wherein: and step five, the etching back method is dry etching.
10. The method of manufacturing a medium voltage device according to claim 1, wherein: and step six, etching and removing the second side wall structures in the low-voltage device region and the high-voltage device region by using a wet etching method.
11. The method of manufacturing a medium voltage device according to claim 1, wherein: and step six, the etching back method is dry etching.
12. The method of manufacturing a medium voltage device according to claim 1, wherein: and step seven, the etching method is dry etching.
13. The method of manufacturing a medium voltage device according to claim 1, wherein: in the eighth step, the method for forming a third sidewall structure on the remaining stacked sidewalls of the low-voltage device region and the high-voltage device region and the second sidewall in the medium-voltage device region by deposition and etching includes: forming a third nitride layer covering the low-voltage, medium-voltage and high-voltage device regions on the substrate, and then etching back the third nitride layer to remain on the rest of the laminated side walls of the low-voltage device region and the high-voltage device region and the second side wall of the medium-voltage device region; depositing a fourth oxide layer, and etching back the fourth oxide layer to keep the fourth oxide layer on the side wall of the third nitride layer; and depositing a fourth nitride layer, and then etching the third nitride layer back to keep the third nitride layer on the side wall of the fourth oxide layer.
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