CN118073191A - Etching process integration method for polysilicon gate of SONOS memory - Google Patents
Etching process integration method for polysilicon gate of SONOS memory Download PDFInfo
- Publication number
- CN118073191A CN118073191A CN202410224397.6A CN202410224397A CN118073191A CN 118073191 A CN118073191 A CN 118073191A CN 202410224397 A CN202410224397 A CN 202410224397A CN 118073191 A CN118073191 A CN 118073191A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- polysilicon
- layer
- area
- mask layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 73
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 60
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 57
- 238000005530 etching Methods 0.000 title claims abstract description 33
- 230000008569 process Effects 0.000 title claims abstract description 33
- 230000010354 integration Effects 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000002093 peripheral effect Effects 0.000 claims abstract description 17
- 238000010405 reoxidation reaction Methods 0.000 claims abstract description 14
- 230000008439 repair process Effects 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention provides an etching process integration method of a polysilicon gate of a SONOS memory, which comprises a substrate, wherein the substrate at least comprises a SONOS memory area, a selection area and a peripheral logic area, a first gate dielectric layer is formed on the selection area and the peripheral logic area, and a first gate polysilicon layer is formed on the first gate dielectric layer on the SONOS memory area; forming a second gate dielectric layer covering the SONOS storage area, the selective area and the peripheral logic area on the substrate; forming a second grid polycrystalline silicon layer on the second grid dielectric layer by deposition and grinding, and sequentially forming a first hard mask layer and a second hard mask layer on the second polycrystalline layer; patterning the first hard mask layer, the second hard mask layer and the second grid polysilicon layer below the first hard mask layer by photoetching and etching to form grid structures positioned on the SONOS storage area, the selective area and the peripheral logic area; and performing first polysilicon reoxidation repair on the substrate. The invention avoids the influence of high-energy lightly doped drain ion implantation under the condition of not influencing polysilicon gate etching.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an etching process integration method of a polysilicon gate of a SONOS memory.
Background
Along with the continuous improvement of the integration level requirements of the Flash memory device in the market, the contradiction between the reliability of the data storage of the traditional Flash memory device and the working speed, the power consumption, the size and the like of the device is increasingly highlighted. The SONOS memory has the characteristics of small cell size, low operation voltage, compatibility with CMOS technology and the like, and the continuous improvement of the SONOS technology promotes the development of the semiconductor memory to the directions of miniaturization, high performance, large capacity, low cost and the like.
As technology advances, it further reduces technology nodes to increase competitiveness. SONOS NOR products of 28nm technology node technology are one-step in the development process to further improve competitiveness, polysilicon gate etch non-LELE (photo-etch=photo-etch). In this case, the polysilicon gate etch is redeveloped. In theory, the one-step oxide hard mask layer process is simplest, but the process has a certain problem that, firstly, if the oxide thickness is thin, the subsequent LDD (lightly doped drain) is implanted into high energy, which will have the risk of IMP duration (ion implantation penetration); secondly, if we increase the oxide thickness, the oxide will remain after the sidewall process, and at this time, although the dosage of the S/D (source drain) implantation is high, the energy is very low, the oxide residue at the top of the polysilicon gate will block the S/D implantation in the polysilicon gate, even affect the formation of the subsequent metal silicide, which will affect the device performance, and increasing the wet etching amount after the sidewall process will affect the step height and the critical dimension of the sidewall.
In order to solve the above problems, a new integration method of etching process of polysilicon gate of SONOS memory is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an integration method for etching process of a polysilicon gate of a SONOS memory, which is used for solving the problem that the prior art lacks a polysilicon gate etching process of a SONOS memory that does not affect the performance of the device.
To achieve the above and other related objects, the present invention provides an integrated method for etching a polysilicon gate of a SONOS memory, comprising:
Providing a substrate, wherein the substrate at least comprises a SONOS storage area, a selection area and a peripheral logic area, a first gate dielectric layer is formed on the selection area and the peripheral logic area, and a first gate polysilicon layer is formed on the first gate dielectric layer on the SONOS storage area;
forming a second gate dielectric layer covering the SONOS storage area, the selective area and the peripheral logic area on the substrate;
forming a second grid polycrystalline silicon layer on the second grid dielectric layer by deposition and grinding, and sequentially forming a first hard mask layer and a second hard mask layer on the second polycrystalline layer;
Patterning the first hard mask layer, the second hard mask layer and the second grid polysilicon layer below the first hard mask layer by utilizing photoetching and etching to form grid structures positioned on the SONOS storage area, the selective area and the peripheral logic area;
Fifthly, performing first polysilicon reoxidation repair on the substrate;
Step six, forming lightly doped drain by utilizing ion implantation;
step seven, performing secondary polysilicon reoxidation repair on the substrate;
and step eight, removing the second hard mask layer.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the material of the first gate dielectric layer in the first step is silicon dioxide.
Preferably, the material of the first gate dielectric layer in the second step is silicon dioxide.
Preferably, the material of the first hard mask layer in the third step is silicon dioxide.
Preferably, the material of the second hard mask layer in the third step is silicon nitride.
Preferably, the polishing method in the third step is chemical mechanical planarization polishing.
Preferably, in the fifth step, the first polysilicon reoxidation repair is performed by using a thermal oxidation method.
Preferably, in the seventh step, the second polysilicon reoxidation repair is performed by using a thermal oxidation method.
Preferably, in the eighth step, the second hard mask layer is removed by using a wet etching method.
As described above, the integration method of the etching process of the polysilicon gate of the SONOS memory has the following beneficial effects:
The invention avoids the influence of high-energy lightly doped drain ion implantation under the condition of not influencing polysilicon gate etching; the second hard mask layer is directly removed by wet etching after the high-energy lightly doped drain ion implantation, so that the blocking of the subsequent high-dose S/D implantation is avoided, and the performance of the device is ensured; by flexibly adjusting the thickness ratio of the first hard mask layer and the second hard mask layer, the influence on the step height and the side wall is accurately controlled under the condition of non-LELE (lithography-etching=lithography-etching) process.
Drawings
FIG. 1 is a schematic illustration of the process flow of the present invention;
FIG. 2 is a schematic diagram illustrating the formation of a second gate dielectric layer according to the present invention;
FIG. 3 is a schematic diagram of forming a second gate polysilicon layer and first and second hard mask layers according to the present invention;
FIG. 4 is a schematic diagram of a gate structure according to the present invention;
FIG. 5 is a schematic diagram showing a first polysilicon reoxidation repair performed in accordance with the present invention;
FIG. 6 is a schematic diagram illustrating the removal of a second hard mask layer according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides an integration method of etching process of a polysilicon gate of a SONOS memory, comprising:
Step one, referring to fig. 2, a substrate (not shown) is provided, the substrate includes at least a SONOS memory area, a selection area and a peripheral logic area, the SONOS memory area, the selection area and the peripheral logic area are formed with a first gate dielectric layer 101, and the first gate dielectric layer 101 on the SONOS memory area is formed with a first gate polysilicon layer 102; the SONOS storage area has a step height compared with the selective area and the peripheral logic area;
In an alternative embodiment, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In an alternative embodiment, the material of the first gate dielectric layer 101 in the first step is silicon dioxide.
Step two, forming a second gate dielectric layer 103 covering the SONOS storage area, the selective area and the peripheral logic area on the substrate;
In an alternative embodiment, the material of the first gate dielectric layer 101 in the second step is silicon dioxide.
Forming a second gate polysilicon layer 104 on the second gate dielectric layer 103 by deposition and grinding to form a structure shown in fig. 3, and sequentially forming a first hard mask layer and a second hard mask layer on the second polysilicon layer; the thickness ratio of the first hard mask layer and the second hard mask layer can be flexibly adjusted, and the influence on the step height and the side wall is accurately controlled under the condition of non-LELE technology.
In an alternative embodiment, the material of the first hard mask layer 105 in the third step is silicon dioxide, which may be formed by chemical vapor deposition or other known methods.
In an alternative embodiment, the material of the second hard mask layer 106 in the third step is silicon nitride, and may be formed by chemical vapor deposition or other known methods.
In an alternative embodiment, the polishing in step three is chemical mechanical planarization polishing.
Patterning the first hard mask layer, the second hard mask layer and the second gate polysilicon layer 104 below the first hard mask layer by utilizing photoetching and etching to form gate structures positioned on the SONOS storage area, the selective area and the peripheral logic area to form a structure shown in figure 4; the etching method is dry etching, and the etching needs to be stopped above the first gate polysilicon layer 102, so that the first gate polysilicon layer 102 is prevented from being damaged;
Fifthly, performing first polysilicon reoxidation repair on the substrate, and forming an oxide layer on the surface of the polysilicon to form a structure shown in fig. 5;
In an alternative embodiment, the first polysilicon reoxidation repair is performed in step five by a thermal oxidation process, i.e., heating under an oxygen gas atmosphere.
Step six, forming lightly doped drain by utilizing ion implantation, wherein the oxide combined with the second hard mask layer 106 can avoid high-energy ion implantation penetrating through the polysilicon gate, so that the performance of the device can meet the requirements;
Step seven, performing secondary polysilicon reoxidation repair on the substrate;
in an alternative embodiment, the second polysilicon reoxidation repair is performed in step seven using a thermal oxidation process.
Step eight, removing the second hard mask layer 106 to form the structure shown in fig. 6. The second hard mask layer 106 can be removed after the lightly doped drain is implanted, the sidewall process is the same as the reference process in the prior art, no redevelopment is needed, and the removal of the second hard mask layer 106 can not affect the subsequent high-dose S/D implantation of the polysilicon gate, so that the WF (work function) is ensured to be the same as the reference process, and the device performance is not required to be readjusted.
In an alternative embodiment, the second hard mask layer 106 is removed in step eight by a wet etching method. For example, the second hard mask layer 106 of silicon nitride may be removed using a phosphoric acid wet etch process.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the invention avoids the influence of the ion implantation of the high-energy lightly doped drain under the condition of not influencing the etching of the polysilicon gate; the second hard mask layer is directly removed by wet etching after the high-energy lightly doped drain ion implantation, so that the blocking of the subsequent high-dose S/D implantation is avoided, and the performance of the device is ensured; by flexibly adjusting the thickness ratio of the first hard mask layer and the second hard mask layer, the influence on the step height and the side wall is accurately controlled under the condition of non-LELE (lithography-etching=lithography-etching) process. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. An etching process integration method of a polysilicon gate of a SONOS memory is characterized by at least comprising the following steps:
Providing a substrate, wherein the substrate at least comprises a SONOS storage area, a selection area and a peripheral logic area, a first gate dielectric layer is formed on the selection area and the peripheral logic area, and a first gate polysilicon layer is formed on the first gate dielectric layer on the SONOS storage area;
forming a second gate dielectric layer covering the SONOS storage area, the selective area and the peripheral logic area on the substrate;
forming a second grid polycrystalline silicon layer on the second grid dielectric layer by deposition and grinding, and sequentially forming a first hard mask layer and a second hard mask layer on the second polycrystalline layer;
Patterning the first hard mask layer, the second hard mask layer and the second grid polysilicon layer below the first hard mask layer by utilizing photoetching and etching to form grid structures positioned on the SONOS storage area, the selective area and the peripheral logic area;
Fifthly, performing first polysilicon reoxidation repair on the substrate;
Step six, forming lightly doped drain by utilizing ion implantation;
step seven, performing secondary polysilicon reoxidation repair on the substrate;
and step eight, removing the second hard mask layer.
2. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and in the first step, the material of the first gate dielectric layer is silicon dioxide.
4. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and in the second step, the material of the first gate dielectric layer is silicon dioxide.
5. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and in the third step, the material of the first hard mask layer is silicon dioxide.
6. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and in the third step, the material of the second hard mask layer is silicon nitride.
7. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: the polishing method in the third step is chemical mechanical planarization polishing.
8. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and fifthly, performing the first polysilicon reoxidation repair by using a thermal oxidation method.
9. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and step seven, performing secondary polysilicon reoxidation repair by using a thermal oxidation method.
10. The method for integrating the etching process of the polysilicon gate of the SONOS memory according to claim 1, wherein the method comprises the following steps: and step eight, removing the second hard mask layer by using a wet etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410224397.6A CN118073191A (en) | 2024-02-28 | 2024-02-28 | Etching process integration method for polysilicon gate of SONOS memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410224397.6A CN118073191A (en) | 2024-02-28 | 2024-02-28 | Etching process integration method for polysilicon gate of SONOS memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118073191A true CN118073191A (en) | 2024-05-24 |
Family
ID=91108797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410224397.6A Pending CN118073191A (en) | 2024-02-28 | 2024-02-28 | Etching process integration method for polysilicon gate of SONOS memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118073191A (en) |
-
2024
- 2024-02-28 CN CN202410224397.6A patent/CN118073191A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7763928B2 (en) | Multi-time programmable memory | |
| US7297598B2 (en) | Process for erase improvement in a non-volatile memory device | |
| US8652887B2 (en) | Multi-layer structures and process for fabricating semiconductor devices | |
| US5470776A (en) | Method for fabricating stacked dynamic random access memory cell | |
| CN1531066B (en) | Manufacture and structure of semiconductor on insulating layer with concave resistance | |
| CN108122973B (en) | Semiconductor structure, forming method thereof and SRAM | |
| US7391098B2 (en) | Semiconductor substrate, semiconductor device and method of manufacturing the same | |
| CN104916639A (en) | Semi-floating gate memory structure and manufacturing method thereof | |
| US20210193529A1 (en) | Method for manufacturing semiconductor device and semiconductor device thereby formed | |
| CN101207026B (en) | Method for forming semiconductor device grids | |
| US10164073B2 (en) | Apparatus and method for memory device | |
| CN111508961A (en) | High-tunneling-efficiency semi-floating gate memory and preparation method thereof | |
| CN118073191A (en) | Etching process integration method for polysilicon gate of SONOS memory | |
| US8536041B2 (en) | Method for fabricating transistor with high-K dielectric sidewall spacer | |
| US20050064716A1 (en) | Plasma removal of high k metal oxide | |
| CN111508896B (en) | Semiconductor structure and forming method thereof | |
| US20210057286A1 (en) | Structure and formation method of semiconductor device with fin structures | |
| CN111540741A (en) | Semi-floating gate memory based on floating gate and control gate connecting channel and preparation method thereof | |
| CN100555586C (en) | Minimizing produces the method in multi-crystal silicification metal cavity when the nitrogen ion injects | |
| CN117998853A (en) | Method for reducing resistance of embedded flash memory control gate | |
| CN110581172B (en) | Semiconductor structure and forming method thereof | |
| CN111477626B (en) | Semi-floating gate memory and preparation method thereof | |
| CN111564443B (en) | High-integration-density semi-floating gate memory and preparation method thereof | |
| US20230352488A1 (en) | Gate stack dipole compensation for threshold voltage definition in transistors | |
| CN111477590B (en) | Grid manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |