CN116867279A - Source-drain ion implantation method for charge trapping nonvolatile memory - Google Patents

Source-drain ion implantation method for charge trapping nonvolatile memory Download PDF

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Publication number
CN116867279A
CN116867279A CN202310768754.0A CN202310768754A CN116867279A CN 116867279 A CN116867279 A CN 116867279A CN 202310768754 A CN202310768754 A CN 202310768754A CN 116867279 A CN116867279 A CN 116867279A
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layer
forming
ion implantation
source
oxide layer
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李妍
辻直樹
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202310768754.0A priority Critical patent/CN116867279A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention provides a source-drain ion implantation method of a charge trapping nonvolatile memory, which comprises the steps of providing a substrate, and forming a first oxide layer, a nitride layer, a second oxide layer, a first polysilicon layer, a third oxide layer and a hard mask layer which are stacked in sequence from bottom to top on the substrate; forming a first side wall on the side wall of the first grid electrode, removing the residual first photoresist layer, etching to remove the exposed first oxide layer, nitride layer and second oxide layer, and forming a grid oxide layer on the substrate; and forming a second polysilicon layer of the array structure covering the first grid electrode, and then etching the second polysilicon layer to form second side walls on two sides of the first grid electrode, so that the array structure of the second grid electrode is formed, and an active area between two adjacent second polysilicon layers is covered by the second side walls. The invention effectively reduces the photoetching process difficulty in the source-drain electrode ion implantation of the nonvolatile memory, reduces the generation probability of particle defects, and brings certain help to the improvement of the yield.

Description

Source-drain ion implantation method for charge trapping nonvolatile memory
Technical Field
The invention relates to the technical field of semiconductors, in particular to a source-drain ion implantation method of a charge trapping nonvolatile memory.
Background
In a typical nonvolatile memory in the prior art, when different ion implantation morphologies are needed for a source electrode and a drain electrode, the typical nonvolatile memory is usually realized in two steps of photoetching steps, photoresist covers the drain electrode during source electrode ion implantation, the photoresist covers the source electrode during drain electrode ion implantation, and a dense array structure of storage areas of the nonvolatile memory and smaller storage unit size put certain difficulty requirements on resolution and alignment windows of photoetching processes.
In order to solve the above-mentioned problems, a new source/drain ion implantation method for a charge trapping nonvolatile memory is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a source-drain ion implantation method for a charge trapping nonvolatile memory, which is used to solve the problem that when source and drain electrodes of the nonvolatile memory need to use different ion implantation morphologies, the ion implantation of source electrode is usually implemented in two steps, the photoresist covers the drain electrode during ion implantation of source electrode, the photoresist covers the source electrode during ion implantation of drain electrode, and the array structure with dense memory areas and smaller memory cell size of the nonvolatile memory put certain difficulty requirements on the resolution and alignment window of the photolithography process.
To achieve the above and other related objects, the present invention provides a source-drain ion implantation method of a charge trapping nonvolatile memory, comprising:
providing a substrate, wherein a first oxide layer, a nitride layer, a second oxide layer, a first polysilicon layer, a third oxide layer and a hard mask layer which are stacked in sequence from bottom to top are formed on the substrate;
step two, forming a first photoresist layer on the hard mask layer, photoetching and opening the first photoresist layer to define a forming area of a first grid electrode, and etching the exposed hard mask layer, the third oxide layer and the first polysilicon layer to the upper part of the second oxide layer by taking the reserved first photoresist layer as a mask, so as to form an array structure of the first grid electrode;
forming a first side wall on the side wall of the first grid electrode, removing the residual first photoresist layer, etching to remove the exposed first oxide layer, the exposed nitride layer and the exposed second oxide layer, and forming a grid oxide layer on the substrate;
forming a second polysilicon layer covering the array structure of the first grid electrode, and then etching the second polysilicon layer to form second side walls on two sides of the first grid electrode, so that the array structure of the second grid electrode is formed, and an active area between two adjacent second polysilicon layers is covered by the second side walls;
step five, forming a first type ion doping area on the active area at one side of the second side wall by utilizing ion implantation;
removing the hard mask layer to form a second photoresist layer covering the array structure of the first grid electrode and the second grid electrode, opening the second photoresist layer by photoetching to open the area between two adjacent first grid electrodes, exposing the second side wall between two adjacent first grid electrodes, and etching to remove the exposed second side wall;
and seventh, forming a second ion doped region on the active region by utilizing ion implantation, thereby forming an asymmetric source-drain electrode ion implantation morphology.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the thickness of the first polysilicon layer in the first step is 1000 to 1500 angstroms.
Preferably, the material of the hard mask layer in the first step is silicon nitride.
Preferably, the thickness of the hard mask layer in the first step is 500 to 1000 angstroms.
Preferably, the etching method in the second step is dry etching.
Preferably, the material of the first side wall in the third step includes at least one of silicon dioxide, silicon nitride and silicon carbonitride.
Preferably, the etching method in the third step is wet etching.
Preferably, the longitudinal diffusion depth of the ion implantation in the second gate in the fifth step is smaller than the height of the second gate between the two nearest first gates.
Preferably, in the sixth step, the hard mask layer is removed by using a wet etching method.
Preferably, in the seventh step, a second type ion doped region is formed on the active region by ion implantation, so as to form an asymmetric source-drain ion implantation morphology, which comprises: removing the remaining second photoresist layer; and forming the second ion doped region on the active region on one side of the second side wall and the active region between the first grid electrodes by utilizing ion implantation.
Preferably, in the seventh step, a second type ion doped region is formed on the active region by ion implantation, so as to form an asymmetric source-drain ion implantation morphology, which comprises: forming the second ion doped region on the active region between the first gates by ion implantation; and then removing the remaining second photoresist layer.
As described above, the source-drain ion implantation method of the charge trapping nonvolatile memory of the present invention has the following beneficial effects:
the invention effectively reduces the photoetching process difficulty in the source-drain electrode ion implantation of the nonvolatile memory, reduces the generation probability of particle defects, brings certain help to the improvement of the yield, and simultaneously can possibly reduce the use of a layer of photomask according to different requirements of a peripheral circuit region.
Drawings
FIG. 1 is a schematic illustration of the process flow of the present invention;
FIG. 2 is a schematic view of a substrate and a stacked structure thereon according to the present invention;
FIG. 3 is a schematic diagram of a first photoresist layer opened by photolithography according to the present invention;
FIG. 4 is a schematic diagram of an array structure of a first gate formed by etching a stacked structure according to the present invention;
FIG. 5 is a schematic view of the invention for removing the exposed ONO layer;
FIG. 6 is a schematic diagram of a gate oxide layer formed according to the present invention;
FIG. 7 is a schematic diagram of forming a second polysilicon layer according to the present invention;
FIG. 8 is a schematic diagram showing the etching of a second polysilicon layer to form a second sidewall according to the present invention;
FIG. 9 is a schematic view of forming a first ion-doped region according to the present invention;
FIG. 10 is a schematic diagram of a hard mask layer removal process according to the present invention;
FIG. 11 is a schematic diagram of a photolithographic opening of a second photoresist layer according to the present invention;
FIG. 12 is a schematic view of the invention for removing the second sidewall between two adjacent first gates;
FIG. 13 is a schematic diagram illustrating removal of a second photoresist layer in an embodiment of the present invention;
FIG. 14 is a schematic view of forming a second ion-doped region according to an embodiment of the present invention;
FIG. 15 is a schematic view illustrating formation of a second ion-doped region according to another embodiment of the present invention;
FIG. 16 is a schematic diagram illustrating removal of a second photoresist layer according to another embodiment of the invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a source-drain ion implantation method of a charge trapping nonvolatile memory, comprising:
step one, referring to fig. 2, a substrate 100 is provided, and a first oxide layer 101, a nitride layer 102, a second oxide layer 103, a first polysilicon layer 104, a third oxide layer 105, and a hard mask layer 106 are sequentially stacked from bottom to top on the substrate 100; the first oxide layer 101, the nitride layer 102 and the second oxide layer 103 are ONO layers, the materials of the first oxide layer and the second oxide layer are typically silicon dioxide, and the material of the nitride layer 102 is typically silicon nitride;
in an alternative embodiment, the substrate 100 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In an alternative embodiment, the thickness of the first polysilicon layer 104 in the first step is 1000 to 1500 a, and it should be noted that the thickness of the first polysilicon layer 104 may be adjusted to other thicknesses according to actual process requirements, which is not specifically limited herein.
In an alternative embodiment, the material of the hard mask layer 106 in the first step is silicon nitride, and it should be noted that the thickness of the hard mask layer 106 herein may be adjusted to other materials known to those skilled in the art according to actual process requirements, which is not specifically limited herein. .
In an alternative embodiment, the thickness of the hard mask layer 106 in the first step is 500 to 1000 angstroms, and it should be noted that the thickness of the hard mask layer 106 may be adjusted to other thicknesses according to actual process requirements, which is not specifically limited herein.
Step two, forming a first photoresist layer 107 on the hard mask layer 106, opening the first photoresist layer 107 by photolithography (exposing, developing, erecting a film, baking, etc.) to define a formation region of a first gate electrode in a storage region, forming a structure as shown in fig. 3, and etching the exposed hard mask layer 106, the third oxide layer 105, the first polysilicon layer 104 to the upper portion of the second oxide layer 103 by using the remaining first photoresist layer 107 as a mask, thereby forming an array structure of the first gate electrode, wherein the first gate electrode is a selection gate and is usually present in pairs on the storage region of a transistor;
in an alternative embodiment, the etching method in the second step is dry etching.
Step three, forming a first sidewall 109 on the sidewall of the first gate, forming the structure shown in fig. 4, removing the remaining first photoresist layer 107, removing the first photoresist layer 107 by ashing and wet cleaning, etching to remove the exposed first oxide layer 101, nitride layer 102 and second oxide layer 103, forming the structure shown in fig. 5, forming a gate oxide layer 110 on the substrate 100, forming the structure shown in fig. 6, and forming the gate oxide layer 110 on the silicon substrate 100 by thermal oxidation;
in an alternative embodiment, the material of the first sidewall 109 in the third step includes at least one of silicon dioxide, silicon nitride, and silicon carbonitride, and the first sidewall 109 may be formed by a deposition and etching back method. It should be noted that the material of the first sidewall 109 may be replaced by other materials known to those skilled in the art, which is not specifically limited herein.
In an alternative embodiment, the method of etching in step three is wet etching.
Step four, forming a second polysilicon layer 111 covering the array structure of the first grid electrode, forming a structure as shown in fig. 7, etching the second polysilicon layer 111 to form second side walls 112 on two sides of the first grid electrode, immediately etching the second polysilicon layer 111 to expose the hard mask layer 106, thereby forming the array structure of the second grid electrode, wherein the second grid electrode is a selection grid in the form of a side wall, so that an active area between two adjacent second polysilicon layers 111 is covered by the second side walls 112, and forming the structure as shown in fig. 8, namely, for two nearest first grid electrodes, forming side wall type second grid electrodes on one side of each first grid electrode, connecting the two side wall type second grid electrodes on the other side due to the fact that the distance between the two first grid electrodes is relatively close, and the polysilicon is still covered on the surface of the active area;
and fifthly, coating and developing photoresist, fully opening the photoresist in the storage area, and selecting photoresist layer covering conditions according to requirements in the peripheral circuit area, so that the active area of the peripheral circuit is fully covered with polysilicon, omitting the photoetching step under the condition that the grid resistance of the peripheral area is acceptable, and then forming a first ion doping area 113 on the active area on one side of the second side wall 112 by utilizing ion implantation to form a structure as shown in fig. 9, wherein the active area between two nearest first grids is protected from first ion doping due to polysilicon, and an ion doping area is formed in the active area on the outer side of the side wall type second grid on the outer side of the two nearest first grids. The photoresist is fully opened only in terms of the storage area, so that the technical difficulty of photoetching is greatly reduced, and meanwhile, the generation probability of particle defects is reduced;
in an alternative embodiment, the depth of the longitudinal diffusion of the ion implantation in the second gate in the fifth step is smaller than the height of the second gate between the two nearest first gates.
Step six, removing the hard mask layer 106 to form a structure shown in fig. 10, forming a second photoresist layer 114 covering the array structure of the first grid electrode and the second grid electrode, opening the second photoresist layer 114 by photoetching to open the area between the two adjacent first grid electrodes, exposing the second side wall 112 between the two adjacent first grid electrodes to form a structure shown in fig. 11, etching to remove the exposed second side wall 112, and forming a structure shown in fig. 12;
in an alternative embodiment, the hard mask layer 106 is removed in step six by wet etching.
And step seven, forming a second ion doped region 115 on the active region by utilizing ion implantation, thereby forming an asymmetric source-drain ion implantation morphology.
In an alternative embodiment, the method for forming the second type ion doped region 115 on the active region by ion implantation in the seventh step, thereby forming an asymmetric source drain ion implantation profile includes: removing the remaining second photoresist layer 114 to form the structure shown in fig. 13; ion implantation is used to form a second ion doped region 115 on the active region on the second sidewall 112 side and between the first gate electrode, resulting in the structure shown in fig. 14.
In an alternative embodiment, the method for forming the second type ion doped region 115 on the active region by ion implantation in the seventh step, thereby forming an asymmetric source drain ion implantation profile includes: forming a second ion-doped region 115 on the active region between the first gates using ion implantation, forming a structure as shown in fig. 15; the remaining second photoresist layer 114 is then removed to form the structure shown in fig. 16, i.e., the polysilicon removal and the second type ion implantation steps are completed in the same photolithographic level.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the invention effectively reduces the difficulty of photolithography in the source/drain ion implantation of the nonvolatile memory, reduces the probability of particle defects, and helps to improve the yield, and reduces the use of a photomask according to different requirements of the peripheral circuit region. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (12)

1. A source-drain ion implantation method of a charge trapping nonvolatile memory is characterized by at least comprising the following steps:
providing a substrate, wherein a first oxide layer, a nitride layer, a second oxide layer, a first polysilicon layer, a third oxide layer and a hard mask layer which are stacked in sequence from bottom to top are formed on the substrate;
step two, forming a first photoresist layer on the hard mask layer, photoetching and opening the first photoresist layer to define a forming area of a first grid electrode, and etching the exposed hard mask layer, the third oxide layer and the first polysilicon layer to the upper part of the second oxide layer by taking the reserved first photoresist layer as a mask, so as to form an array structure of the first grid electrode;
forming a first side wall on the side wall of the first grid electrode, removing the residual first photoresist layer, etching to remove the exposed first oxide layer, the exposed nitride layer and the exposed second oxide layer, and forming a grid oxide layer on the substrate;
forming a second polysilicon layer covering the array structure of the first grid electrode, and then etching the second polysilicon layer to form second side walls on two sides of the first grid electrode, so that the array structure of the second grid electrode is formed, and an active area between two adjacent second polysilicon layers is covered by the second side walls;
step five, forming a first type ion doping area on the active area at one side of the second side wall by utilizing ion implantation;
removing the hard mask layer to form a second photoresist layer covering the array structure of the first grid electrode and the second grid electrode, opening the second photoresist layer by photoetching to open the area between two adjacent first grid electrodes, exposing the second side wall between two adjacent first grid electrodes, and etching to remove the exposed second side wall;
and seventh, forming a second ion doped region on the active region by utilizing ion implantation, thereby forming an asymmetric source-drain electrode ion implantation morphology.
2. The method of claim 1, wherein the step of implanting source and drain ions comprises: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method of claim 1, wherein the step of implanting source and drain ions comprises: the thickness of the first polysilicon layer in the first step is 1000 to 1500 angstroms.
4. The method of claim 1, wherein the step of implanting source and drain ions comprises: the material of the hard mask layer in the first step is silicon nitride.
5. The method of claim 1, wherein the step of implanting source and drain ions comprises: the thickness of the hard mask layer in the first step is 500 to 1000 angstroms.
6. The method of claim 1, wherein the step of implanting source and drain ions comprises: and step two, the etching method is dry etching.
7. The method of claim 1, wherein the step of implanting source and drain ions comprises: and in the third step, the material of the first side wall comprises at least one of silicon dioxide, silicon nitride and silicon carbonitride.
8. The method of claim 1, wherein the step of implanting source and drain ions comprises: and step three, the etching method is wet etching.
9. The method of claim 1, wherein the step of implanting source and drain ions comprises: and step five, the longitudinal diffusion depth of the ion implantation in the second grid electrode is smaller than the height of the second grid electrode between the two nearest first grid electrodes.
10. The method of claim 1, wherein the step of implanting source and drain ions comprises: and step six, removing the hard mask layer by using a wet etching method.
11. The method of claim 1, wherein the step of implanting source and drain ions comprises: in the seventh step, a second type ion doped region is formed on the active region by utilizing ion implantation, so that the method for forming the asymmetric source-drain electrode ion implantation morphology comprises the following steps: removing the remaining second photoresist layer; and forming the second ion doped region on the active region on one side of the second side wall and the active region between the first grid electrodes by utilizing ion implantation.
12. The method of claim 1, wherein the step of implanting source and drain ions comprises: in the seventh step, a second type ion doped region is formed on the active region by utilizing ion implantation, so that the method for forming the asymmetric source-drain electrode ion implantation morphology comprises the following steps: forming the second ion doped region on the active region between the first gates by ion implantation; and then removing the remaining second photoresist layer.
CN202310768754.0A 2023-06-27 2023-06-27 Source-drain ion implantation method for charge trapping nonvolatile memory Pending CN116867279A (en)

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CN202310768754.0A CN116867279A (en) 2023-06-27 2023-06-27 Source-drain ion implantation method for charge trapping nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310768754.0A CN116867279A (en) 2023-06-27 2023-06-27 Source-drain ion implantation method for charge trapping nonvolatile memory

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