CN116936479A - Method for reducing silicon oxide loss of shallow trench isolation region in epitaxial layer trench etching - Google Patents

Method for reducing silicon oxide loss of shallow trench isolation region in epitaxial layer trench etching Download PDF

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Publication number
CN116936479A
CN116936479A CN202310960964.XA CN202310960964A CN116936479A CN 116936479 A CN116936479 A CN 116936479A CN 202310960964 A CN202310960964 A CN 202310960964A CN 116936479 A CN116936479 A CN 116936479A
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etching
layer
epitaxial layer
silicon oxide
barrier layer
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CN202310960964.XA
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姜林鹏
安苏阳
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202310960964.XA priority Critical patent/CN116936479A/en
Publication of CN116936479A publication Critical patent/CN116936479A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

The invention provides a method for reducing the defect of silicon oxide in a shallow trench isolation region in epitaxial layer trench etching, which comprises the steps of providing a substrate, forming STI (shallow trench isolation) on the substrate to define an active region, and forming a plurality of grid laminated structures and corresponding source and drain regions on the active region; forming a first etching barrier layer covering the STI and the grid electrode lamination structure on the substrate, and then etching the etching barrier layer to enable part of the etching barrier layer to remain above the STI; forming a groove on the source region and the drain region by utilizing photoetching and etching; and forming an epitaxial layer at the bottom of the groove, and then forming an interlayer dielectric layer covering the gate stack. According to the invention, a layer of first etching barrier layer is deposited before exposure, then part of the first etching barrier layer is removed through wet etching or dry etching, part of the first etching barrier layer is remained at the shallow trench, the silicon oxide loss of a shallow trench isolation region is reduced when a trench is formed on a fin during etching, and enough process window is reserved for interlayer dielectric layer deposition and chemical mechanical polishing.

Description

Method for reducing silicon oxide loss of shallow trench isolation region in epitaxial layer trench etching
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing the loss of silicon oxide in a shallow trench isolation region in epitaxial layer trench etching.
Background
With the development of CMOS technology, a larger drive current is required to increase the speed of the circuit, and stressing the channel has become an important method to improve the performance of the field effect transistor. In the advanced process, the P-type source/drain region needs to form a trench in advance on the fin after the gate is formed to form an embedded sige structure by crystal epitaxy, but in the process of forming the trench on the fin, as shown in fig. 2, the shallow trench isolation region also has a loss of silicon oxide to form the trench because of the protection of no mask, which brings process challenges to the filling of the subsequent interlayer dielectric layer and chemical mechanical polishing, as shown in fig. 3. To reduce the loss of silicon oxide in the shallow trench isolation region while ensuring the formation of the trench on the fin, a method for solving the problem of silicon germanium etching and reducing the loss of silicon oxide in the shallow trench isolation region is proposed.
In order to solve the above problems, a new method for reducing the silicon oxide loss in the shallow trench isolation region in the epitaxial layer trench etching needs to be proposed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a method for reducing the defect of silicon oxide in a shallow trench isolation region in epitaxial layer trench etching, which is used for solving the problem that in the prior art, in the process of forming a trench on a fin, the shallow trench isolation region will have silicon oxide loss to form a trench because of the protection of no mask, and the process challenges are brought to the filling of a subsequent interlayer dielectric layer and chemical mechanical polishing.
To achieve the above and other objects, the present invention provides a method for reducing silicon oxide loss in shallow trench isolation regions in epitaxial layer trench etching, comprising:
providing a substrate, wherein STI is formed on the substrate to define an active region, and a plurality of grid stack structures and corresponding source and drain regions are formed on the active region;
forming a first etching barrier layer covering the STI and the grid laminated structure on the substrate, and then etching the etching barrier layer to enable part of the etching barrier layer to remain above the STI;
forming a groove on the source region and the drain region by utilizing photoetching and etching;
and fourthly, forming an epitaxial layer at the bottom of the groove, and then forming an interlayer dielectric layer covering the grid electrode lamination.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the gate stack structure in the first step is composed of a stack layer and a second etching barrier layer located on the stack layer, and the stack layer is composed of a polysilicon layer, a nitride layer and an oxide layer which are stacked in sequence from bottom to top.
Preferably, the material of the second etching barrier layer in the first step includes at least one of silicon dioxide, silicon nitride or doped silicon nitride.
Preferably, the material of the first etching barrier layer in the second step is polysilicon, silicon dioxide, spin-on carbon, photoresist layer or bottom anti-reflection coating.
Preferably, in the second step, the first etching barrier layer is etched back by using a wet etching method so that part of the first etching barrier layer remains above the STI.
Preferably, in the second step, the first etching barrier layer is etched by using a photoetching and dry etching method so that part of the first etching barrier layer remains above the STI.
Preferably, in the second step, the thickness of the etching barrier layer remaining above the STI is 50 to 100 nm.
Preferably, the method for forming the trench on the source region and the drain region by using photolithography and etching in the third step includes: forming a spin-on carbon hard mask covering the gate stack structure on the substrate, and then sequentially forming a bottom anti-reflection coating and a photoresist layer on the spin-on carbon hard mask; photoetching and opening the photoresist layer above the grid laminated structure; and etching the photoetching opened area by using a dry etching method, and forming the grooves on the source region and the drain region.
Preferably, the substrate in the first step is formed with NMOS and PMOS.
Preferably, the epitaxial layer in the fourth step is formed on the source and drain regions of the PMOS.
Preferably, the epitaxial layer in the fourth step is an embedded germanium-silicon epitaxial layer.
As described above, the method for reducing the loss of silicon oxide in the shallow trench isolation region in the epitaxial layer trench etching has the following beneficial effects:
according to the invention, a layer of first etching barrier layer is deposited before exposure, then part of the first etching barrier layer is removed through wet etching or dry etching, and part of the first etching barrier layer is reserved at the shallow trench and used as an etching barrier medium, so that the silicon oxide loss of a shallow trench isolation region is reduced while forming a trench on a fin during etching, and enough process windows are reserved for interlayer dielectric layer deposition and chemical mechanical polishing.
Drawings
FIG. 1 is a schematic diagram of a prior art lithography;
FIG. 2 is a schematic diagram of a prior art trench formed in a source drain region;
FIG. 3 is a schematic diagram of an interlayer dielectric layer formed according to the present invention;
FIG. 4 is a schematic illustration of the process flow of the present invention;
FIG. 5 is a schematic view illustrating the formation of a first etch stop layer according to the present invention;
FIG. 6 is a schematic diagram of a reserved portion of a first etch stop layer over an STI according to the present invention;
FIG. 7 is a schematic diagram of the lithography of the present invention;
FIG. 8 is a schematic diagram of forming a trench in a source drain region in accordance with the present invention;
fig. 9 is a schematic diagram of forming an interlayer dielectric layer according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 4, the present invention provides a method for reducing silicon oxide loss in a shallow trench isolation region in epitaxial layer trench etching, comprising:
step one, providing a substrate 201, wherein an STI 202 is formed on the substrate 201 to define an active region, a plurality of gate stack structures 203 and corresponding source and drain regions are formed on the active region, and the gate stack structures 203 are fin structures;
in an alternative embodiment, the substrate 201 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In an alternative embodiment, the gate stack 203 in the first step is composed of a stack and a second etching stop layer on the stack, and the stack is composed of a polysilicon layer, a nitride layer, and an oxide layer stacked sequentially from bottom to top.
In an alternative embodiment, the material of the second etch stop layer in step one comprises at least one of silicon dioxide, silicon nitride or doped silicon nitride, for example, by forming an oxide layer on the stack, and then forming a silicon nitride layer on the oxide layer as a second etch stop layer for protecting the sidewalls of the stack during the subsequent etching to form the trench.
In an alternative embodiment, the substrate 201 in step one is formed with NMOS and PMOS.
Step two, forming a first etching barrier layer 204 covering the STI 202 and the gate stack structure 203 on the substrate 201 to form a structure as shown in FIG. 5, and then etching the etching barrier layer to enable part of the etching barrier layer to remain above the STI 202, wherein the remaining part of the etching barrier layer can protect the STI 202 when a trench is formed by etching later, so that etching loss of the STI 202 is reduced or avoided, and the structure as shown in FIG. 6 is formed;
in an alternative embodiment, the material of the first etching stopper 204 in the second step is polysilicon, silicon dioxide, spin-on carbon, photoresist layer, or bottom anti-reflective coating, which is preferably polysilicon.
In an alternative embodiment, the first barrier layer 202 is etched back in step two by wet etching so that a portion thereof remains over the STI 202.
In an alternative embodiment, the first etch stop layer 204 is etched in step two using photolithography and dry etching to partially remain over the STI 202.
In an alternative embodiment, the thickness of the etch stop layer remaining over the STI 202 in step two is 50 to 100 nanometers.
Step three, forming grooves on the source region and the drain region by utilizing photoetching and etching to form a structure shown in fig. 8, and reserving enough process windows for depositing an interlayer dielectric layer 206 and chemical mechanical polishing;
in an alternative embodiment, the method for forming the grooves on the source region and the drain region in the third step by using photolithography and etching comprises the following steps: forming a spin-on carbon hard mask 205 overlying the gate stack structure 203 on the substrate 201 to form the structure shown in fig. 7, followed by sequentially forming a bottom anti-reflective coating and a photoresist layer (not shown) on the spin-on carbon hard mask 205; photoetching and opening a photoresist layer above the gate stack structure 203; and etching the photoetching opened area by using a dry etching method, and forming grooves on the source region and the drain region.
Step four, an epitaxial layer is formed at the bottom of the trench, and then an interlayer dielectric layer 206 covering the gate stack is formed, where the material of the interlayer dielectric layer 206 is typically silicon dioxide, so as to form the structure shown in fig. 9.
In an alternative embodiment, the epitaxial layer in step four is formed on the source and drain regions of the PMOS.
In an alternative embodiment, the epitaxial layer in step four is an embedded sige epitaxial layer.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, according to the invention, a layer of first etching barrier layer is deposited before exposure, then part of the first etching barrier layer is removed through wet etching or dry etching, and part of the first etching barrier layer is left at the shallow trench as an etching barrier medium, so that the formation of a groove on the fin is realized during etching, the loss of silicon oxide in the isolation region of the shallow trench is reduced, and enough process window is reserved for the deposition of an interlayer dielectric layer and chemical mechanical polishing. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (12)

1. A method for reducing silicon oxide loss in shallow trench isolation regions in epitaxial layer trench etching, comprising:
providing a substrate, wherein STI is formed on the substrate to define an active region, and a plurality of grid stack structures and corresponding source and drain regions are formed on the active region;
forming a first etching barrier layer covering the STI and the grid laminated structure on the substrate, and then etching the etching barrier layer to enable part of the etching barrier layer to remain above the STI;
forming a groove on the source region and the drain region by utilizing photoetching and etching;
and fourthly, forming an epitaxial layer at the bottom of the groove, and then forming an interlayer dielectric layer covering the grid electrode lamination.
2. The method for reducing the loss of silicon oxide in a shallow trench isolation region in a trench etch of an epitaxial layer of claim 1, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method for reducing the loss of silicon oxide in a shallow trench isolation region in a trench etch of an epitaxial layer of claim 1, wherein: the grid electrode laminated structure in the first step consists of a laminated layer and a second etching barrier layer positioned on the laminated layer, wherein the laminated layer consists of a polycrystalline silicon layer, a nitride layer and an oxide layer which are sequentially stacked from bottom to top.
4. A method for reducing shallow trench isolation region silicon oxide loss in epitaxial layer trench etching as set forth in claim 3 wherein: the material of the second etching barrier layer in the first step includes at least one of silicon dioxide, silicon nitride or doped silicon nitride.
5. The method for reducing the loss of silicon oxide in a shallow trench isolation region in a trench etch of an epitaxial layer of claim 1, wherein: and in the second step, the material of the first etching barrier layer is polysilicon, silicon dioxide, spin-coated carbon, a photoresist layer or a bottom anti-reflection coating.
6. The method for reducing shallow trench isolation region silicon oxide loss in epitaxial layer trench etching of claim 5, wherein: and step two, etching the first etching barrier layer back by utilizing a wet etching method so that part of the first etching barrier layer remains above the STI.
7. The method for reducing shallow trench isolation region silicon oxide loss in epitaxial layer trench etching of claim 5, wherein: and step two, etching the first etching barrier layer by using photoetching and dry etching methods to enable part of the first etching barrier layer to remain above the STI.
8. The method for reducing the loss of silicon oxide in a shallow trench isolation region in a trench etch of an epitaxial layer of claim 1, wherein: and in the second step, the thickness of the etching barrier layer remained above the STI is 50-100 nanometers.
9. A method for reducing shallow trench isolation region silicon oxide loss in epitaxial layer trench etch according to claim 1 or 3, characterized by: the method for forming the grooves on the source region and the drain region by utilizing photoetching and etching in the third step comprises the following steps: forming a spin-on carbon hard mask covering the gate stack structure on the substrate, and then sequentially forming a bottom anti-reflection coating and a photoresist layer on the spin-on carbon hard mask; photoetching and opening the photoresist layer above the grid laminated structure; and etching the photoetching opened area by using a dry etching method, and forming the grooves on the source region and the drain region.
10. The method for reducing the loss of silicon oxide in a shallow trench isolation region in a trench etch of an epitaxial layer of claim 1, wherein: and in the first step, NMOS and PMOS are formed on the substrate.
11. The method of reducing shallow trench isolation region silicon oxide loss in epitaxial layer trench etching of claim 10, wherein: and step four, the epitaxial layer is formed on the source region and the drain region of the PMOS.
12. The method of reducing shallow trench isolation region silicon oxide loss in epitaxial layer trench etching of claim 11, wherein: and step four, the epitaxial layer is an embedded germanium-silicon epitaxial layer.
CN202310960964.XA 2023-08-01 2023-08-01 Method for reducing silicon oxide loss of shallow trench isolation region in epitaxial layer trench etching Pending CN116936479A (en)

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