CN117955341A - Control circuit and method of voltage conversion circuit and adapter - Google Patents
Control circuit and method of voltage conversion circuit and adapter Download PDFInfo
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- CN117955341A CN117955341A CN202211279694.8A CN202211279694A CN117955341A CN 117955341 A CN117955341 A CN 117955341A CN 202211279694 A CN202211279694 A CN 202211279694A CN 117955341 A CN117955341 A CN 117955341A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The present disclosure relates to the technical field of power converters, and in particular, to a voltage conversion circuit control circuit, a voltage conversion circuit control method, and an adapter, where the control circuit includes: the sampling resistor, the sampling capacitor and the adjusting resistor are connected in series and then connected in parallel with the sampling resistor, and the sampling module is used for collecting current information at two ends of the filtering inductor; the reverse amplification module is used for reversely amplifying the voltages at two ends of the sampling capacitor to obtain an intermediate voltage signal; the clock generation module is used for generating a first clock signal and a second clock signal with preset phase differences, the comparison module is used for determining the second signal according to the first signal and negative reference current required by the soft switch, and the control module is used for determining a target control signal based on the second signal and the second clock signal so as to control the conduction of the third switching tube and the fourth switching tube. The control precision of the voltage conversion circuit is improved.
Description
Technical Field
The disclosure relates to the technical field of power converters, and in particular relates to a control circuit of a voltage conversion circuit, a control method of the voltage conversion circuit and an adapter.
Background
With the continuous development of power electronics technology, power electronic converters are widely used in a variety of situations. The four-tube voltage conversion circuit has the advantages of identical input and output voltage polarity, fewer passive devices and relatively lower voltage stress of power devices, and can realize soft switching of all switching tubes.
However, when the voltage conversion circuit in the related art is used for controlling all the switching tube soft switches, the sampling effect on the filter inductance current in the voltage conversion circuit is poor, and the phenomenon that two bridge arms have the same frequency can occur in a high-frequency occasion.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure aims to provide a control circuit of a voltage conversion circuit, a control method of the voltage conversion circuit and an adapter, so that the sampling precision of a filter inductance current in the voltage conversion circuit is improved at least to a certain extent when soft switching is realized, and the control precision of the voltage conversion circuit is improved.
According to a first aspect of the present disclosure, there is provided a control circuit of a voltage conversion circuit including a first switching tube, a second switching tube, a third switching tube, and a fourth switching tube and a filter inductance; the first switching tube and the second switching tube which are positioned on the same bridge arm are complementarily conducted, and the third switching tube and the fourth switching tube which are positioned on the same bridge arm are complementarily conducted; one end of the filter inductor is connected with the middle point of the bridge arm of the first switching tube and the second switching tube, and the other end of the filter inductor is connected with the middle point of the third switching tube and the fourth switching tube; the control circuit includes: the sampling module comprises a sampling resistor, a sampling capacitor and an adjusting resistor, wherein the sampling resistor is connected with the filtering inductor in series, and the sampling capacitor is connected with the adjusting resistor in parallel after being connected with the sampling resistor in series; the sampling module is used for collecting current information at two ends of the filter inductor. The reverse amplification module is connected with the sampling module and is used for reversely amplifying the voltages at two ends of the sampling capacitor to obtain an intermediate voltage signal; the clock generation module is used for generating a first clock signal and a second clock signal with preset phase differences, and the first clock signal is used for controlling the conduction of the first switching tube and the conduction of the second switching tube; the output end of the comparison module is connected with the reverse amplification module and the clock generation module and is used for determining a second signal according to a first signal and a negative reference current required by the soft switch, wherein the first signal is obtained by superposing the intermediate voltage signal and the first clock signal; the control module is connected with the clock generation module and the comparison module, the output end of the control module is connected with the third switching tube and used for determining a target control signal based on the second signal and the second clock signal, and the target control signal is used for controlling the third switching tube to be conducted and the fourth switching tube to be conducted.
According to a second aspect of the present disclosure, there is provided a control method of a voltage conversion circuit including a first switching tube, a second switching tube, a third switching tube, and a fourth switching tube and a filter inductance; the first switching tube and the second switching tube which are positioned on the same bridge arm are complementarily conducted, and the third switching tube and the fourth switching tube which are positioned on the same bridge arm are complementarily conducted; one end of the filter inductor is connected with the middle point of the bridge arm of the first switching tube and the second switching tube, and the other end of the filter inductor is connected with the middle point of the third switching tube and the fourth switching tube; the voltage conversion circuit further comprises a sampling module, the sampling module comprises a sampling resistor, a sampling capacitor and an adjusting resistor, the sampling resistor is connected with the filter inductor in series, and the sampling capacitor is connected with the adjusting resistor in parallel after being connected with the sampling resistor in series; the sampling module is used for collecting current information at two ends of the filter inductor; the control method comprises the following steps: acquiring initial voltage signals at two ends of the sampling capacitor; reversely amplifying the initial voltage signal to obtain an intermediate voltage signal; acquiring a first clock signal and a second clock signal with preset phase differences, wherein the first clock signal is used for controlling the conduction of the first switching tube and the second switching tube; superposing the intermediate voltage signal and the first clock signal to obtain a first signal, and determining a second signal according to the first signal and a negative reference current required by a soft switch; and determining the target control signal based on the second signal and the second clock signal to enable the third switching tube and the fourth switching tube.
According to a third aspect of the present disclosure, there is provided an adapter including the control circuit of the voltage conversion circuit described above and the voltage conversion circuit.
According to the control circuit of the voltage conversion circuit, the sampling resistor is connected with the filter inductor in series, the sampling capacitor is connected with the adjusting resistor in parallel after being connected with the sampling resistor in series, namely, the current value of the sampling resistor is identical to the current value of the filter inductor, the sampling resistor is connected with the adjusting resistor in parallel after being connected with the sampling resistor in series, namely, the voltage at two ends of the sampling resistor is equal to the sum of the voltage of the sampling capacitor and the voltage of the adjusting resistor, and the parasitic inductance of the resistor compensator is adjusted to enable the voltage at two ends of the sampling resistor to be equal to the voltage at two ends of the sampling capacitor, the voltage signals at two ends of the sampling capacitor are used for representing the current information of the filter inductor, so that the sampling precision is higher, and the precision of the obtained current information of the filter inductor is higher. On the other hand, the voltage signal obtained by sampling is amplified and then is overlapped with a first clock signal to obtain a first signal, a second signal is determined based on the first signal and a negative reference current required by the soft switch, the target control signal is determined based on the second signal and the second clock signal, and the obtained control signal is used for controlling the third switching tube.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort. In the drawings:
Fig. 1 schematically illustrates a block diagram of a control circuit of a voltage conversion circuit in an exemplary embodiment of the present disclosure;
FIG. 2 schematically illustrates a circuit topology of a voltage conversion circuit in an exemplary embodiment of the present disclosure;
FIG. 3 schematically illustrates an optimal switching sequence diagram of a switching tube in an exemplary embodiment of the present disclosure;
FIG. 4 schematically illustrates an optimal switching sequence diagram of another switching tube in an exemplary embodiment of the present disclosure;
FIG. 5 schematically illustrates a graph of current change for different loads in an exemplary embodiment of the present disclosure;
FIG. 6 schematically illustrates a current change plot at different loads in an exemplary embodiment of the present disclosure;
Fig. 7 schematically illustrates a circuit topology diagram of a control circuit of a voltage conversion circuit in an exemplary embodiment of the present disclosure;
Fig. 8 schematically illustrates a circuit topology structure diagram of a control circuit of another voltage conversion circuit in an exemplary embodiment of the present disclosure;
fig. 9 schematically illustrates a circuit topology structure diagram of a control circuit of still another voltage conversion circuit in an exemplary embodiment of the present disclosure;
Fig. 10 schematically illustrates a circuit topology structure diagram of a control circuit of a further voltage conversion circuit in an exemplary embodiment of the present disclosure;
FIG. 11 schematically illustrates a circuit topology diagram of a control circuit of a voltage conversion circuit in an exemplary embodiment of the present disclosure as applied to a full-bridge LLC circuit;
Fig. 12 schematically illustrates a circuit topology structure diagram of a circuit of a control circuit of a voltage conversion circuit in an exemplary embodiment of the present disclosure applied to full-bridge inversion;
Fig. 13 schematically illustrates a flowchart of a control method of a voltage conversion circuit in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
In the related art, power electronic converters are widely used in various applications. For the case where the input voltage variation range is wide and the output voltage is between the input voltage ranges, such as an intermediate bus converter in a distributed power system, an anode power supply in a power processing unit in a spacecraft electric propulsion system, and a two-stage active power factor corrector, a DC-DC converter with buck-boost characteristics needs to be used.
The voltage conversion circuit has the advantages of identical input and output voltage polarity, fewer passive devices and relatively low voltage stress of the power device, and is suitable for application occasions with wider input voltage range and output voltage between the input voltages, but the voltage conversion circuit in the related technology has poor sampling effect on the filter inductance current in the voltage conversion circuit when realizing control of all switching tube soft switches, and can generate the phenomenon of the same frequency of two bridge arms in high-frequency occasions.
Referring to fig. 1, the present disclosure first provides a control circuit of a voltage conversion circuit, wherein the voltage conversion circuit control circuit may include a first switching tube Q 1, a second switching tube Q 2, a third switching tube Q 3, and a fourth switching tube Q 4 and a filter inductor L C; the first switching tube and the second switching tube which are positioned on the same bridge arm are complementarily conducted, and the third switching tube and the fourth switching tube which are positioned on the same bridge arm are complementarily conducted; one end of the filter inductor is connected with the middle point of the bridge arm of the first switching tube and the second switching tube, and the other end of the filter inductor is connected with the middle point of the third switching tube and the fourth switching tube.
The control circuit 11 comprises a sampling module 11, an inverting amplification module 12, a comparison module 13, a control module 14 and a clock generation module 15. The sampling module 11 includes a sampling resistor R S, a sampling capacitor C com, and an adjusting resistor R com, where the sampling resistor is connected in series with the filter inductor, and the sampling capacitor is connected in parallel with the sampling resistor after being connected in series with the adjusting resistor.
The reverse amplification module 12 is connected to the sampling module 11, and is configured to reversely amplify the capacitors at two ends of the sampling capacitor C com to obtain an intermediate voltage signal. The clock generation module 15 is configured to generate a first clock signal and a second clock signal with a preset phase difference, where the first clock signal is used to control the first switch tube Q 1 to be turned on. The output end of the comparing module 13 is connected to the inverting amplifying module 12 and the clock generating module 15, and is used for determining a second signal according to a first signal and a negative reference current required by the soft switch, wherein the first signal is obtained by overlapping the intermediate voltage signal and the first clock signal.
The control module 14 is connected to the clock generation module 15 and the comparison module 13, and an output end of the control module is connected to the third switching tube Q 3, and is configured to determine a target control signal based on the second signal and the second clock signal, where the target control signal is used to control the third switching tube Q 3 to be turned on.
The sampling resistor R S is arranged in series with the filter inductor, the sampling capacitor is connected in series with the adjusting resistor, and then is arranged in parallel with the sampling resistor, namely the current value on the sampling resistor R S is the same as the current value of the filter inductor L C, the sampling resistor is arranged in parallel after the sampling resistor is connected in series with the adjusting resistor, namely the voltage at two ends of the sampling resistor R S is equal to the sum of the voltage of the sampling capacitor C com and the voltage of the adjusting resistor R com, and the parasitic inductance is compensated by the adjusting resistor R com due to the parasitic inductance of the sampling resistor, so that the voltage at two ends of the sampling resistor R S is equal to the voltage at two ends of the sampling capacitor C com, the voltage signals at two ends of the sampling capacitor C com are used for representing the current information of the filter inductor L C, the sampling precision is higher, and the precision of the obtained current information of the filter inductor L C is higher. On the other hand, the voltage signal obtained by sampling is amplified and then is overlapped with a first clock signal to obtain a first signal, a second signal is determined based on the first signal and a negative reference current required by the soft switch, the target control signal is determined based on the second signal and the second clock signal, the obtained control signal is utilized to control the third switching tube Q 3, and the third switching tube Q 3 and the fourth switching tube Q 4 are complementarily conducted, so that the target control signal simultaneously controls the third switching tube Q 3 and the fourth switching tube Q 4, the problem that two bridge arms cannot be in the same frequency can be avoided, and the control precision of the voltage conversion circuit when realizing soft switch of all the switching tubes is improved.
The following describes each of the above structures in detail.
In the present exemplary embodiment, the voltage conversion circuit may be a Buck-boost converter, a full-bridge LLC circuit, a full-bridge inverter+resonant network+full-bridge rectifier network, or the like, and may be another DC-DC or DC-AC circuit, and is not particularly limited in the present exemplary embodiment.
The control circuit is described in detail below by taking the voltage conversion circuit as a Buck-boost converter as an example.
In the present exemplary embodiment, referring to fig. 2, when the voltage converter circuit is a Buck-boost converter, a first end of the first switching tube Q 1 is connected to the input power V in, and a second end is connected to the second switching tube Q 2; the first end of the second switching tube Q 2 is connected to the second end of the first switching tube Q 1, and the second end is connected to the input power supply V in; the first end of the third switching tube Q 3 is connected with a load, and the second end of the third switching tube Q 4 is connected with the fourth switching tube; the first end of the fourth switching tube Q 4 is connected to the first end of the third switching tube Q 3, and the second end is connected to a load; the filter transistor is connected between the first end of the second switching tube Q 2 and the first end of the fourth switching tube Q 4, and a first diode D 1 and a first capacitor C 1 may be arranged in parallel at two ends of the first switching tube Q 1, where the forward conduction direction of the first diode D 1 is opposite to that of the first switching tube Q 1; a second diode D 2 and a second capacitor C 2 can be arranged at two ends of the second switching tube Q 2 in parallel, and the forward conduction direction of the second diode D 2 is opposite to that of the second switching tube Q 2; a third diode D 3 and a third capacitor C 3 can be arranged at two ends of the third switching tube Q 3 in parallel, and the forward conduction direction of the third diode D 3 is opposite to that of the third switching tube Q 3; a fourth diode D 4 and a fourth capacitor C 4 may be disposed in parallel at two ends of the fourth switching tube Q 4, and a forward conduction direction of the fourth diode D 4 is opposite to that of the fourth switching tube Q 4.
In addition, referring to fig. 2, when the voltage converter circuit is a Buck-boost converter, the second end of the first switching tube and the second end of the third switching tube are in an off state.
Wherein, Q 1 and Q 4 are master control pipes. If the inductance is intentionally reduced such that its current ripple increases, i Lc will be able to flow in reverse through Q 2 or Q 3. Then, when Q 2 or Q 3 is turned off, i Lc discharges the junction capacitance of Q 1 or Q 4 in the direction from B to a, which provides for ZVS to be achieved for Q 1 or Q 4. The same applies to switching tube Q 2 or Q 3 to achieve ZVS inductor current i Lc, which is required to satisfy inductor current flow from a to B. The inductor current value that is required to meet ZVS to achieve Q 1 or Q 4 at this point is defined as I ZVS. Where i Lc is the current flowing through the filter inductance L C. The point A is the midpoint of the bridge arm of the first switching tube and the second switching tube Q 2, and the point B is the midpoint of the bridge arm of the third switching tube Q 3 and the fourth switching tube Q4.
In this exemplary embodiment, referring to fig. 3 and 4, fig. 3 shows the conduction condition of the four switching tubes when the input voltage of the Buck-boost is smaller than the output voltage, and fig. 4 shows the conduction condition of the four switching tubes when the input voltage is greater than the output voltage, if the four switching tubes in the voltage conversion circuit are all enabled to realize soft switching, the optimal switching time sequence of the four switching tubes is Q 1, Q 3 should be turned off before Q 3, Q 3 should be turned off before Q 2, Q 2 should be turned off before Q 4, and Q 4 should be turned off before Q 1. where-I ZVS represents the negative reference current required for soft switching.
Further, referring to fig. 5 and 6, fig. 5 and 6 show main waveforms of the voltage conversion circuit when the load gradually decreases, respectively. Wherein I o is the load current, and I Lc is the inductor current. It can be seen that the duty cycles of switching transistors Q 1 and Q 2 vary, the duty cycles of switching transistors Q 3 and Q 4 also vary, and the phases of the drive signals of Q 3 and Q 4 vary relative to the drive signals of Q 1 and Q 2 at different input voltages and load currents.
In the present exemplary embodiment, based on the availability, the on time of Q 1, that is, the time when the current of the filter inductor L C is at the negative reference current-I zvs required for soft switching, the time when I Lc drops to-I ZVS is the off time of Q 3.
In the present exemplary embodiment, referring to fig. 7, the sampling module 11 may include a sampling resistor R S, a sampling capacitor C com, and a regulating resistor R com. The sampling resistor R S is connected between the second end of the second switching tube Q 2 and the second end of the fourth switching tube Q 4, and the sampling capacitor C com and the adjusting resistor R com are connected in series between the second end of the second switching tube Q 2 and the second end of the fourth switching tube Q 4.
When the voltage conversion circuit is a Buck-boost converter, the sampling resistor is connected with the filter inductor in series through a fourth switching tube, the first end of the regulating resistor is connected with the first end of the sampling resistor, and the second end of the regulating resistor is connected with the first end of the sampling capacitor; the second end of the sampling capacitor is connected to the second end of the sampling resistor. Specifically, a first end of the adjusting resistor is connected to a second end of the fourth switching tube, and the second end of the adjusting resistor is connected to a first end of the sampling capacitor; the second end of the sampling capacitor is connected to the second end of the second switch tube.
In this exemplary embodiment, referring to fig. 8, the parasitic inductance L s of the sampling resistor R S may be equivalent to one inductance element, and the parasitic inductance L s is disposed in series with the sampling resistor R S, and the sampling capacitor C com may be deduced based on the following formula, where the following conditions are satisfied by the adjusting resistor R com:
After the above-mentioned derivation, it can be obtained, I.e. the ratio of the inductance value of the parasitic inductance L s of the sampling resistor R S to the resistance value of the sampling resistor R S is equal to the product of the capacitance value of the sampling capacitor C com and the resistance value of the regulating resistor R com within a threshold range.
In this exemplary embodiment, the values of the capacitance and resistance specifically adopted by the foregoing C com and R S may be customized according to the user requirement, and in this exemplary embodiment, without being limited to any specific limitation, L s may be obtained by measuring the foregoing R S, and R com is calculated based on the foregoing preset condition.
In the present exemplary embodiment, the inverting amplification module 12 includes an operational amplifier EA. The first resistor R 1, the second resistor R 2, and the third resistor R 3. The inverting input end of the operational amplifier EA is connected to the first end of the sampling capacitor C com through a first resistor R 1, and the forward input end of the operational amplifier EA is connected to the second end of the sampling capacitor C com through a second resistor R 2; the third resistor R 3 is connected to the inverting input terminal of the operational amplifier EA and the output terminal of the operational amplifier EA. Wherein the gain of the direction amplifying module isFor example, if R 3 is 20 kiloohms and R 1 is 10 kiloohms, the gain of the direction amplifying module is a= -2. In this exemplary embodiment, the magnitudes of the first resistor R 1, the second resistor R 2, and the third resistor R 3 may be customized according to the user's requirement, which is not specifically limited in this exemplary embodiment.
It should be noted that the operational amplifier may also be connected to a forward bias voltage V bias, which is connected to the positive input terminal of the comparator through a protection resistor. The bias power V bias may be 2V, or may be customized according to a user requirement, which is not specifically limited in this exemplary embodiment, and is used to raise all positive and negative half cycles of the ac power to a positive voltage range, so as to prevent the operational amplifier from not working normally in the negative half cycle of the ac voltage.
In the present exemplary embodiment, the above-described clock generation module 15 is configured to generate the first clock signal CLK1 and the second clock signal CLK2 having a preset phase difference. Wherein the predetermined phase difference between the first clock signal CLK1 and the second clock signal CLK2 may beAnd the customization can be performed according to the user requirements. The clock generation module 15 may include a first output terminal for outputting the first clock signal and a second output terminal for outputting the second clock signal.
In an exemplary embodiment of the present disclosure, referring to fig. 9, the comparing module 13 includes a calculating module, a comparator, wherein the calculating module is configured to determine a negative reference voltage required by the soft switch based on the negative reference current-I zvs required by the soft switch, the sampling capacitor C com, and the gain of the inverting amplifying module 12; in particular, -V ZVS＝-IZVSARS. The comparator has its positive input connected to the calculation module and its negative input connected to the output of the inverting amplifier module 12 and to the first output of the clock generation module 15.
In this exemplary embodiment, the control circuit 1 may further include a first protection resistor and a second protection resistor, where the first protection resistor is connected between the first output terminal of the clock generation module 15 and the inverting input terminal of the comparator; and the second protection resistor is connected between the output end of the reverse amplifying module 12 and the reverse input end of the comparator.
In another exemplary embodiment of the present disclosure, referring to fig. 10, the comparing module 13 includes a calculating module and a comparator, wherein an input end of the calculating module is connected to an output end of the inverting amplifying module 12, and is used for determining a target current signal based on an intermediate voltage signal, the sampling capacitor C com and a gain of the inverting amplifying module 12; in particular, the method comprises the steps of,The positive input of the comparator inputs the negative reference current-I zvs required by the soft switch, and the negative input is connected to the output of the calculation module and to the input first output of the above-mentioned clock generation module 15.
In an exemplary embodiment of the disclosure, the control module 14 may include an RS flip-flop, where the RS flip-flop includes a reset terminal and a set 1 terminal, and the reset terminal is connected to the output terminal of the comparing module 13, and the set 1 terminal is connected to the second clock signal CLK2, that is, the set 1 terminal is connected to the second output terminal of the clock generating module 15. The forward output end of the RS flip-flop is connected to the driving end of the third switching tube Q 3, and the reverse output end of the RS flip-flop is connected to the driving end of the fourth switching tube Q 4. For transmitting the target control signal to the third switching tube Q 3 and the fourth switching tube Q 4.
In an exemplary embodiment of the present disclosure, a connection method when the voltage conversion circuit is a full-bridge LLC circuit will be described in detail with reference to fig. 11.
In this exemplary embodiment, the full-bridge LLC circuit may include the first switching tube Q 1, the second switching tube Q 2, the third switching tube Q 3, and the fourth switching tube Q 4, the filter inductor L C, the fifth capacitor C 5, the first primary winding, the first secondary winding, the second secondary winding, the first transistor module, and the second transistor module, wherein the connection manners of the first switching tube Q 1, the second switching tube Q 2, the third switching tube Q 3, and the fourth switching tube Q 4 are already defined in detail, and thus, will not be repeated herein.
The first end of the fifth capacitor C 5 is connected to the second end of the second switch tube Q 2; the first end of the filter inductor is connected to the first end of the fifth capacitor C 5, the second end of the filter inductor L C is connected to the first end of the touch winding, the first end of the first primary winding is connected to the filter inductor L C, the second end of the first primary winding is connected to the first end of the sampling resistor RS, the second end of the sampling resistor R S is connected to the second end of the fourth switching tube Q 4, the first end of the first secondary winding is connected to the first node P 1, and the second end is connected to the first end of the first transistor module; the first end of the second secondary winding is connected to the first node P 1, and the second end is connected to the second end of the second transistor module; a second end of the first transistor module is connected to a second node P 2, and a second end of the second transistor winding is connected to a second node P 2; the voltage between the first node P 1 and the second node P 2 is the output voltage of the full-bridge LLC circuit.
The first transistor module comprises a fifth diode, wherein the positive electrode of the fifth diode D 5 is connected with the second end of the first secondary winding, and the negative electrode of the fifth diode D 5 is connected with the second node P 2; the second transistor module includes a sixth diode D 6, whose anode is connected to the second end of the second secondary winding and whose cathode is connected to the second node P 2. In another exemplary embodiment of the disclosure, the first transistor module further includes a first transistor, and the first transistor is disposed in parallel with the fifth diode D 5; the second transistor module further comprises a second triode, and the second triode is arranged in parallel with the sixth diode D 6.
The specific connection manner and operation principle of the reverse amplifying module 12, the comparing module 13, the control module 14 and the clock generating module 15 are already defined in detail, and thus are not limited here.
In an exemplary embodiment of the present disclosure, a connection method when the voltage conversion circuit is a full-bridge inverter+resonant network+full-bridge rectifier network will be described in detail with reference to fig. 12.
In this exemplary embodiment, the voltage conversion circuit may include the first switching tube Q 1, the second switching tube Q 2, the third switching tube Q 3, and the fourth switching tube Q 4, the filter inductor L C, the sixth capacitor C 6, the first resonant capacitor C f1, the second resonant capacitor C f2, the second primary winding, the third secondary winding, the seventh capacitor C 7, the secondary filter inductor L f, the first resistor R 1, and the AC/DC module, wherein the connection manners of the first switching tube Q 1, the second switching tube Q 2, the third switching tube Q 3, and the fourth switching tube Q 4 are already defined in detail, and thus, the description thereof will not be repeated herein.
The first end of the filter inductor Lc is connected to the middle points of the bridge arms of the first switching tube Q 1 and the second switching tube Q 2, the second end of the filter inductor Lc is connected to the first end of the sixth capacitor C 6, the second end of the sixth capacitor C 6 is connected to the first end of the second primary winding, the second end of the primary winding is connected to the first end of the sampling capacitor, the second section of the sampling capacitor is connected to the middle points of the bridge arms of the third switching tube Q 3 and the fourth switching tube Q 4, the first end of the first resonant capacitor C f1 is connected to the second end of the filter short rod, and the second end of the first resonant capacitor C f1 is connected to the second end of the sampling electric group.
In this exemplary embodiment, the third secondary winding is coupled to the second primary winding, the first end of the third secondary winding is connected to the first end of the seventh capacitor, the second end of the third secondary winding is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resonant capacitor C f2, the second end of the second resonant capacitor C f2 is connected to the second end of the seventh capacitor, the first end of the secondary filter inductor L f is connected to the second end of the seventh capacitor, the second end of the secondary filter inductor L f is connected to the third node, and the second end of the first resistor is connected to the fourth node, wherein the third node and the fourth node are input terminals of the AC/DC module.
In this example embodiment, the AC/DC module may include a seventh diode D 7, an eighth diode D 8, a ninth diode D 9, and a twelfth diode D 10, wherein an anode of the seventh diode D 7 is connected to the third node P 3, and a cathode is connected to a cathode of the eighth diode D 8; the anode of the eighth diode D 8 is connected to the fourth node P 4; the positive electrode of the ninth diode D 9 is connected with the positive electrode of the twelfth diode, and the negative electrode of the ninth diode D 9 is connected with the third node; the negative electrode of the twelfth diode D 10 is connected to the fourth node P 4.
In this exemplary embodiment, a first end of the sampling capacitor C com of the sampling module is connected to the midpoint B of the bridge arms of the third switching tube Q 3 and the fourth switching tube Q 4, a second end is connected to a first end of the adjusting resistor R com, and a second end of the adjusting resistor R com is connected to a second end of the second primary winding.
The specific connection manner and operation principle of the reverse amplifying module 12, the comparing module 13, the control module 14 and the clock generating module 15 are already defined in detail, and thus are not limited here.
Referring to fig. 11 and 12, when the voltage conversion circuit is a full-bridge LLC circuit and a full-bridge inverter+resonant network+full-bridge rectifier network, the second ends of the first and third switching transistors are connected.
The sampling resistor R S is arranged in series with the filter inductor, the sampling capacitor is connected in series with the adjusting resistor, and then is arranged in parallel with the sampling resistor, namely the current value on the sampling resistor R S is the same as the current value of the filter inductor L C, the sampling resistor is arranged in parallel after the sampling resistor is connected in series with the adjusting resistor, namely the voltage at two ends of the sampling resistor R S is equal to the sum of the voltage of the sampling capacitor C com and the voltage of the adjusting resistor R com, and the parasitic inductance is compensated by the adjusting resistor R com due to the parasitic inductance of the sampling resistor, so that the voltage at two ends of the sampling resistor R S is equal to the voltage at two ends of the sampling capacitor C com, the voltage signals at two ends of the sampling capacitor C com are used for representing the current information of the filter inductor L C, the sampling precision is higher, and the precision of the obtained current information of the filter inductor L C is higher. On the other hand, the voltage signal obtained by sampling is amplified and then is overlapped with a first clock signal to obtain a first signal, a second signal is determined based on the first signal and a negative reference current required by the soft switch, the target control signal is determined based on the second signal and the second clock signal, the obtained control signal is utilized to control the third switching tube Q 3, and the third switching tube Q 3 and the fourth switching tube Q 4 are complementarily conducted, so that the target control signal simultaneously controls the third switching tube Q 3 and the fourth switching tube Q 4, the problem that two bridge arms cannot be in the same frequency can be avoided, and the control precision of the voltage conversion circuit when realizing soft switch of all the switching tubes is improved. Meanwhile, ZVS of the switching tube can be realized in the whole input voltage and load variation range, and the fluctuation and effective value of the inductance current i Lc are minimum.
Further, the present disclosure also provides a control method of a voltage conversion circuit, where the voltage conversion circuit includes a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and a filter inductor; the first switching tube and the second switching tube which are positioned on the same bridge arm are complementarily conducted, and the third switching tube and the fourth switching tube which are positioned on the same bridge arm are complementarily conducted; one end of the filter inductor is connected with the middle point of the bridge arm of the first switching tube and the second switching tube, and the other end of the filter inductor is connected with the middle point of the third switching tube and the fourth switching tube; the voltage conversion circuit further comprises a sampling module, the sampling module comprises a sampling resistor, a sampling capacitor and an adjusting resistor, the sampling resistor is connected with the filter inductor in series, and the sampling capacitor is connected with the adjusting resistor in parallel after being connected with the sampling resistor in series; the sampling module is configured to collect current information at two ends of the filter inductor, as shown in fig. 13, and the control method may include the following steps:
step S1310, obtaining initial voltage signals at two ends of the sampling capacitor;
step S1320, carrying out reverse amplification on the initial voltage signal to obtain an intermediate voltage signal;
Step S1330, a first clock signal and a second clock signal with a preset phase difference are obtained, where the first clock signal is used to control the conduction of the first switching tube and the second switching tube;
step S1340, superposing the intermediate voltage signal and the first clock signal to obtain a first signal;
step S1350, determining a second signal according to the first signal and the negative reference current required by the soft switch;
step S1360 determines the target control signal based on the second signal and the second clock signal to control the third switching tube and the fourth switching tube.
In this exemplary embodiment, the sampling resistor R S includes a parasitic inductance, the parasitic inductance L s of the sampling resistor R S may be equivalent to an inductance element, and the parasitic inductance L s is disposed in series with the sampling resistor R S, and the sampling capacitor C com may be deduced based on the following formula, where the following conditions are to be satisfied by the adjusting resistor R com:
After the above-mentioned derivation, it can be obtained, I.e. the ratio of the inductance value of the parasitic inductance Ls of the sampling resistor RS to the resistance value of the sampling resistor RS is equal to the product of the capacitance value of the sampling capacitor Ccom and the resistance value of the regulating resistor Rcom within a threshold range.
In this exemplary embodiment, the values of the capacitance and resistance specifically adopted by the foregoing C com and R S may be customized according to the user requirement, and in this exemplary embodiment, without being limited to any specific limitation, L s may be obtained by measuring the foregoing R S, and R com is calculated based on the foregoing preset condition.
In this example embodiment, an initial voltage signal at two ends of the sampling capacitor may be obtained by a sampling module, and the initial voltage signal may be reversely amplified by a reverse amplifying module to obtain an intermediate voltage signal; and acquiring a first clock signal and a second clock signal with preset phase differences through a clock generation module, wherein the first clock signal is used for controlling the conduction of the first switching tube and the second switching tube.
In this exemplary embodiment, a comparison module is used to superimpose the intermediate voltage signal and the first clock signal to obtain a first signal, determine a second signal according to the first signal and a negative reference current required by the soft switch, and then determine the target control signal based on the second signal and the second clock signal by using a control module to control the third switching tube and the fourth switching tube.
It should be noted that, the specific details of the sampling module, the inverting amplifying module, the comparing module, the control module and the clock generating module may refer to the description of the control circuit of the voltage converting circuit, and will not be described herein.
Still further, the present disclosure also provides an adapter that may include the control circuit and the voltage conversion circuit of the voltage conversion circuit described above. The voltage conversion circuit control circuit and the voltage conversion circuit have been described in detail above, and thus, will not be described here again.
In this example embodiment, the adapter may be an adapter for charging a terminal device, where the terminal device may be a mobile phone, a tablet computer, a smart watch, etc., and the adapter may charge the terminal device in a wired manner or may charge the terminal device in a wireless manner, and in this example embodiment, the adapter is not specifically limited.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (11)
1. The control circuit of the voltage conversion circuit is characterized by comprising a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and a filter inductor;
The first switching tube and the second switching tube which are positioned on the same bridge arm are complementarily conducted, and the third switching tube and the fourth switching tube which are positioned on the same bridge arm are complementarily conducted;
One end of the filter inductor is connected with the middle point of the bridge arm of the first switching tube and the second switching tube, and the other end of the filter inductor is connected with the middle point of the third switching tube and the fourth switching tube;
The control circuit includes:
The sampling module comprises a sampling resistor, a sampling capacitor and an adjusting resistor, wherein the sampling resistor is connected with the filtering inductor in series, the sampling capacitor is connected with the adjusting resistor in series and then connected with the sampling resistor in parallel, and the sampling module is used for collecting current information at two ends of the filtering inductor;
The reverse amplification module is connected with the sampling module and is used for reversely amplifying the voltages at two ends of the sampling capacitor to obtain an intermediate voltage signal;
The clock generation module is used for generating a first clock signal and a second clock signal with preset phase differences, and the first clock signal is used for controlling the conduction of the first switching tube and the second switching tube;
The output end of the comparison module is connected with the reverse amplification module and the clock generation module and is used for determining a second signal according to a first signal and a negative reference current required by the soft switch, wherein the first signal is obtained by superposing the intermediate voltage signal and the first clock signal;
The control module is connected with the clock generation module and the comparison module, the output end of the control module is connected with the third switching tube and used for determining a target control signal based on the second signal and the second clock signal, and the target control signal is used for controlling the conduction of the third switching tube and the fourth switching tube.
2. The control circuit according to claim 1, wherein the sampling resistor is connected in series with the filter inductor through the fourth switching tube, a first end of the adjusting resistor is connected to the first end of the sampling resistor, and a second end of the adjusting resistor is connected to the first end of the sampling capacitor;
the second end of the sampling capacitor is connected with the second end of the sampling resistor.
3. The control circuit of claim 2, wherein the inverting amplification module comprises:
The operational amplifier is characterized in that a reverse input end is connected with a first end of the sampling capacitor through a first resistor, and a forward input end is connected with a second end of the sampling capacitor through a second resistor;
And the third resistor is connected with the inverting input end of the operational amplifier and the output end of the operational amplifier.
4. The control circuit of claim 1, wherein the comparison module comprises:
A calculation module for determining a negative reference voltage required by the soft switch based on the negative reference current required by the soft switch, the sampling capacitance, and the gain of the inverting amplification module;
The positive input end of the comparator is connected with the calculation module, and the reverse input end of the comparator is connected with the output end of the reverse amplification module;
The clock generation module comprises a first output end which is used for outputting the first clock signal and is connected with the reverse input end of the comparator.
5. The control circuit of claim 4, wherein the control circuit further comprises:
the first protection resistor is connected between the first output end of the clock generation module and the reverse input end of the comparator;
and the second protection resistor is connected between the output end of the reverse amplification module and the reverse input end of the comparator.
6. The control circuit of claim 1, wherein the comparison module comprises:
The input end of the calculation module is connected with the output end of the reverse amplification module and is used for determining a target current signal based on the intermediate voltage signal, the sampling capacitor and the gain of the reverse amplification module;
The positive input end of the comparator inputs the negative reference current required by the soft switch, and the reverse input end of the comparator is connected with the output end of the calculation module;
The clock generation module comprises a first output end which is used for outputting the first clock signal and is connected with the reverse input end of the comparator.
7. The control circuit of claim 1, wherein the control module comprises:
The reset end of the RS trigger is connected with the output end of the comparison module, and the 1-set end of the RS trigger is connected with the second clock signal;
The clock generation module comprises a second output end which is used for outputting the second clock signal and is connected with the 1-setting end;
The forward output end of the RS trigger is connected to the driving end of the third switching tube, and the reverse output end of the RS trigger is connected to the driving end of the fourth switching tube.
8. The control circuit of claim 1, wherein a ratio of an inductance value of a parasitic inductance of the sampling resistor to a resistance value of the sampling resistor is equal to a product of a capacitance value of the sampling capacitor and a resistance value of the adjustment resistor within a threshold range.
9. The control method of the voltage conversion circuit is characterized in that the voltage conversion circuit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and a filter inductor;
The first switching tube and the second switching tube which are positioned on the same bridge arm are complementarily conducted, and the third switching tube and the fourth switching tube which are positioned on the same bridge arm are complementarily conducted;
One end of the filter inductor is connected with the middle point of the bridge arm of the first switching tube and the second switching tube, and the other end of the filter inductor is connected with the middle point of the third switching tube and the fourth switching tube;
The voltage conversion circuit further comprises a sampling module, the sampling module comprises a sampling resistor, a sampling capacitor and an adjusting resistor, the sampling resistor is connected with the filter inductor in series, and the sampling capacitor is connected with the adjusting resistor in parallel after being connected with the sampling resistor in series; the sampling module is used for collecting current information at two ends of the filter inductor; the control method comprises the following steps:
acquiring initial voltage signals at two ends of the sampling capacitor;
reversely amplifying the initial voltage signal to obtain an intermediate voltage signal;
Acquiring a first clock signal and a second clock signal with preset phase differences, wherein the first clock signal is used for controlling the conduction of the first switching tube and the second switching tube;
Superposing the intermediate voltage signal and the first clock signal to obtain a first signal;
determining a second signal according to the first signal and a negative reference current required by the soft switch;
The target control signal is determined based on the second signal and the second clock signal to control the third switching tube and the fourth switching tube.
10. The control method according to claim 9, characterized in that a ratio of an inductance value of a parasitic inductance of the sampling resistor to a resistance value of the sampling resistor is equal to a product of a capacitance value of the sampling capacitor and a resistance value of the adjusting resistor within a threshold value.
11. An adapter, comprising:
A control circuit of a voltage conversion circuit as claimed in any one of claims 1 to 8 and the voltage conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211279694.8A CN117955341A (en) | 2022-10-19 | 2022-10-19 | Control circuit and method of voltage conversion circuit and adapter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211279694.8A CN117955341A (en) | 2022-10-19 | 2022-10-19 | Control circuit and method of voltage conversion circuit and adapter |
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| Publication Number | Publication Date |
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| CN117955341A true CN117955341A (en) | 2024-04-30 |
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| CN202211279694.8A Pending CN117955341A (en) | 2022-10-19 | 2022-10-19 | Control circuit and method of voltage conversion circuit and adapter |
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| Country | Link |
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| CN (1) | CN117955341A (en) |
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2022
- 2022-10-19 CN CN202211279694.8A patent/CN117955341A/en active Pending
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