CN117955047B - Leakage current suppression method in relay self-test - Google Patents

Abstract

The invention discloses a leakage current suppression method in relay self-checking, which is applied to a grid-connected process of an inverter system, wherein the output end of a DC/AC unit of the inverter system is connected with a power grid through a relay group; the relay group comprises a positive relay group and a negative relay group, wherein the positive relay group comprises at least two relays connected in series with a positive bus, and the negative relay group comprises at least two relays connected in series with a negative bus; a bidirectional switch unit is also connected between the positive end and the negative end of the output of the DC/AC unit; when the forward relay group is closed, the inverter system forms a suppression loop for generating a voltage suppressing leakage current by controlling the DC/AC unit and the bidirectional switch unit. The problem of tripping of the leakage protector caused by overlarge leakage current generated in the relay self-checking process is effectively solved, and the whole implementation mode is simple and easy to implement.

Description

Leakage current suppression method in relay self-test

Technical Field

The invention relates to the technical field of power generation, in particular to a leakage current suppression method in relay self-inspection.

Background

As shown in fig. 1, a typical topology structure of a photovoltaic system is known, and the pre-stage is a DC/DC unit 110, where a Boost topology may be used, but is not limited thereto; the latter stage is a DC/AC unit 120, where a Heric topology may be employed, but is not limited thereto; the output end of the DC/AC unit 120 is connected to the power grid through the relay group 130, and then grid connection of the photovoltaic system is achieved through closing of the relay group 130.

However, in the actual grid-connected process, it is found that, in the relay self-checking stage and the relay full-closing stage, when the relay T ₁、T₃ in fig. 1 is closed, but before the DC/AC unit 120 does not emit waves, the leakage current i _g0 is distorted, if the output leakage current i _g0 is excessively distorted, the component of non-50 Hz is increased, and the leakage protector is sensitive to the component of non-50 Hz, so that the leakage current i _g0 easily causes the tripping of the leakage protector, thereby affecting the normal grid-connected process of the photovoltaic system. Therefore, it is necessary to suppress leakage current generated during grid connection of the photovoltaic system.

Disclosure of Invention

An object of the present invention is to provide a leakage current suppressing method in relay self-test capable of solving at least one of the above-mentioned drawbacks in the related art.

In order to achieve the above purpose, the invention adopts the following technical scheme: the leakage current suppression method in the relay self-inspection is applied to the grid-connected process of an inverter system, and the output end of a DC/AC unit of the inverter system is connected with a power grid through a relay group; the relay group comprises a positive relay group and a negative relay group, the positive relay group comprises at least two relays connected in series with a positive bus, and the negative relay group comprises at least two relays connected in series with a negative bus; a bidirectional switch unit is also connected between the positive output terminal and the negative output terminal of the DC/AC unit; when the forward relay group is closed, the inverter system forms a suppression loop for generating a voltage suppressing leakage current by controlling the DC/AC unit and the bidirectional switch unit.

As one preferable aspect, the DC/AC unit includes switching tubes S _a1、S_a4、S_b1 and S _b4 connected in a bridge type, wherein the switching tubes S _a1 and S _a4 are connected to each other to form a first branch, and the switching tubes S _b1 and S _b4 are connected to each other to form a second branch; the first branch and the second branch are connected in parallel with positive and negative buses, and the switching tubes S _a1 and S _b4 are close to the positive buses; when the forward relay group is closed, the suppression loop is formed by controlling the switching tube S _a1、S_a4、S_b1、S_b4 and the bidirectional switching unit.

Preferably, when the forward relay group is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to the power grid through the on switch tubes S _a4 and S _b4, so that the DC/AC unit outputs a differential mode direct current voltage to form a suppression loop.

Preferably, when the forward relay group is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to the power grid through the on switch tubes S _a1 and S _b1, so that the DC/AC unit outputs a differential mode direct current voltage to form a suppression loop.

Preferably, when the positive relay is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to the power grid through the on switch tube S _a1, so that the live wire clamp of the power grid is located on the positive bus to form a suppression loop.

Preferably, when the positive relay is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to the power grid through the on switch tube S _a4, so that the live wire clamp of the power grid is located on the negative bus to form a suppression loop.

As one preferable, the bidirectional switching unit includes switching transistors S ₂ and S ₃ connected in anti-series, and when the positive relay combination is closed, the switching transistors S ₂ and S ₃ are both in a conductive state and form a suppression loop with the switching transistor S _a1 or the switching transistor S _a4 that are conductive in the DC/AC unit.

As one preferable aspect, the withstand voltage value of the positive capacitance to ground of the inverter system is greater than (V _g+V_dc), and the withstand voltage value of the negative capacitance to ground is greater than V _g, where V _dc is a bus voltage and V _g is a grid voltage.

As one preferable aspect, the withstand voltage value of the positive capacitance to ground of the inverter system is greater than V _g, and the withstand voltage value of the negative capacitance to ground is greater than (V _g-V_dc), where V _dc is a bus voltage and V _g is a grid voltage.

Preferably, the positive relay group includes relays T ₁ and T ₃, and the negative relay group includes relays T ₂ and T ₄, and the operation condition of the relay group is determined by detecting the port voltage v _IO.

Compared with the prior art, the invention has the beneficial effects that:

In the relay self-checking process, when the positive relay is closed, the inverter system controls the suppression loop formed by the DC/AC unit and the bidirectional switch unit, the suppression loop can generate voltage for suppressing leakage current, the problem of tripping of the leakage protector caused by overlarge leakage current generated in the relay self-checking process is effectively solved, and the whole implementation mode is simple and easy to implement.

Drawings

Fig. 1 is a schematic diagram of a distribution structure of capacitance to ground of a conventional inverter system.

Fig. 2 is a timing chart of a conventional inverter system.

Fig. 3 is a simulated waveform diagram of a conventional inverter system.

Fig. 4 is a waveform diagram of a conventional inverter system.

Fig. 5 is a schematic diagram of a conventional inverter system with a distributed capacitance to ground in the first process shown in fig. 4.

Fig. 6 is a schematic diagram of a distribution structure of capacitance to ground of the conventional inverter system in the second process shown in fig. 4.

Fig. 7 is a schematic diagram of a distribution structure of capacitance to ground of the conventional inverter system in the process three shown in fig. 4.

Fig. 8 is a schematic diagram of a distribution structure of capacitance to ground of the conventional inverter system in the fourth process shown in fig. 4.

Fig. 9 is a timing diagram of the inverter system of the present invention.

Fig. 10 is a timing chart of an inverter system according to a first embodiment of the present invention.

Fig. 11 is a schematic diagram of a ground capacitance distribution structure of an inverter system forming a suppression loop according to a first embodiment of the invention.

Fig. 12 is an equivalent circuit diagram of the structural diagram shown in fig. 11 according to the present invention.

Fig. 13 is a simplified circuit schematic of the equivalent circuit schematic of fig. 12 according to the present invention.

Fig. 14 is a timing chart of an inverter system according to a second embodiment of the present invention.

Fig. 15 is a schematic diagram of a ground capacitance distribution structure of an inverter system forming a suppression loop according to a second embodiment of the present invention.

Fig. 16 is an equivalent circuit diagram of the structural diagram of fig. 15 according to the present invention.

Fig. 17 is a simplified circuit schematic of the equivalent circuit schematic of fig. 16 according to the present invention.

Fig. 18 is a timing chart of an inverter system according to a third embodiment of the present invention.

Fig. 19 is a schematic diagram of a ground capacitance distribution structure of an inverter system forming a suppression loop according to a third embodiment of the present invention.

Fig. 20 is an equivalent circuit diagram of the structural diagram of fig. 19 according to the present invention.

Fig. 21 is a simplified circuit schematic of the equivalent circuit schematic of fig. 20 of the present invention.

Fig. 22 is a timing chart of an inverter system according to a fourth embodiment of the present invention.

Fig. 23 is a schematic diagram showing a distribution structure of capacitance to ground of an inverter system forming a suppression loop according to a fourth embodiment of the present invention.

Fig. 24 is an equivalent circuit diagram of the structural diagram of fig. 23 according to the present invention.

Fig. 25 is a simplified circuit schematic of the equivalent circuit schematic of fig. 24 of the present invention.

Fig. 26 is a timing chart of an inverter system according to a fifth embodiment of the present invention.

Fig. 27 is a schematic diagram of a ground capacitance distribution structure of an inverter system forming a suppression loop according to a fifth embodiment of the present invention.

Fig. 28 is an equivalent circuit diagram of the structural diagram of fig. 27 according to the present invention.

Fig. 29 is a simplified circuit schematic of the equivalent circuit schematic of fig. 28 of the present invention.

In the figure: 110. a DC/DC unit; 120. a DC/AC unit; 130. a relay group; 131. a positive relay group; 132. a negative relay group; 140. and a bidirectional switch unit.

Detailed Description

The present invention will be further described with reference to the following specific embodiments, and it should be noted that, on the premise of no conflict, new embodiments may be formed by any combination of the embodiments or technical features described below.

In the description of the present invention, it should be noted that, for the azimuth words such as terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., the azimuth and positional relationships are based on the azimuth or positional relationships shown in the drawings, it is merely for convenience of describing the present invention and simplifying the description, and it is not to be construed as limiting the specific scope of protection of the present invention that the device or element referred to must have a specific azimuth configuration and operation.

It should be noted that the terms "first," "second," and the like in the description and in the claims are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The terms "comprises" and "comprising," along with any variations thereof, in the description and claims, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As shown in fig. 1, the existing inverter system includes a DC/DC unit 110 and a DC/AC unit 120 which are sequentially connected, a bidirectional switch unit 140 is connected in parallel between the DC/AC unit 120 and a relay group 130, an output end of the relay group 130 is connected to a power grid, and the inverter system can be connected to the power grid after the relay group 130 is closed. Further, the input of the inverter system may be connected to the photovoltaic module PV or to other power generation devices, and the relay set 130 includes a relay T ₁~T₄, where relays T ₁ and T ₃ are connected in series to the positive bus and relays T ₂ and T ₄ are connected in series to the negative bus.

Typically, the operation of the inverter system mainly includes the following four phases. The first stage: the bus voltage V _dc of the inverter system is established and the DC/DC unit 110 is started to boost. And a second stage: the relays T ₁~T₄ are operated respectively to perform relay self-test. And a third stage: relay T ₁~T₄ is fully closed. Fourth stage: the DC/AC unit 120 performs PWM modulation (Pulse Width Modulatio, pulse width modulation) to perform grid-connected power generation.

Specifically, as shown in fig. 2, in the second stage, the relay T ₃ is opened and the rest of the relays are closed in sequence; opening the relay T ₁ and closing the rest relays; opening the relay T ₂ and closing the rest relays; opening the relay T ₄ and closing the rest relays; and whether the relay T ₁~T₄ is normal is judged by detecting whether the port voltage v _IO is the power grid voltage.

In conjunction with fig. 3, when the relays T ₂ or T ₄ are self-tested, the relays T ₁ and T ₃ are in the closed state, at this time, the leakage current i _g0 will be distorted before the DC/AC unit 120 does not wave, if the output leakage current i _g0 is distorted too much, the component of non-50 Hz will increase, and the leakage protector is sensitive to the component of non-50 Hz, so the leakage current i _g0 easily causes the leakage protector to trip.

To facilitate understanding of the scheme of the present application, the leakage current i _g0 caused in the self-test of the relay set 130 may be first analyzed. When the relays T ₁ and T ₃ are in the closed state and the DC/AC unit 120 is not generating waves, the waveform of the grid voltage V _g is shown in fig. 4, dividing one cycle into four processes for analysis.

In a first process, i.e. the period of [ t ₀, pi/2ω ] shown in fig. 4, as can be appreciated in connection with fig. 5, from time t ₀, the voltage of the power grid is greater than the voltage v _dc+ of the positive capacitance to ground, at which time the switching tube S _a1 of the DC/AC unit 120 is turned on, and the power grid charges the negative capacitance to ground through the switching tube S _a1 until the voltage of the power grid reaches the positive peak value at time pi/2ω.

In a second process, i.e. the [ pi/2ω, pi/ω+t ₀ ] period shown in fig. 4, it can be appreciated in connection with fig. 6 that the grid voltage decreases from the positive peak starting from the pi/2ω moment, at which time the DC/AC unit 120 is disconnected and the voltage of the negative capacitance to ground remains unchanged until the grid reaches 0 at the pi/2ω moment.

In a third process, i.e. the [ pi/ω+t ₀, 3 pi/2ω ] period shown in fig. 4, it can be understood from fig. 7 that, starting from the moment pi/ω+t ₀, the voltage v _dc- of the negative capacitance to ground is greater than the voltage of the power grid, at this time the switching tube S _a2 of the DC/AC unit 120 is turned on, and the negative capacitance to ground discharges to the power grid through the switching tube S _a1 until the moment 3 pi/2ω, and the power grid reaches a negative peak.

In a fourth process, i.e. the [ 3pi/2ω, 2pi/ω+t ₀ ] period shown in fig. 4, it can be appreciated in connection with fig. 8 that starting from time 3pi/2ω, the grid voltage rises from the negative peak, at which time the DC/AC unit 120 is disconnected, the voltage of the negative capacitance to ground remains unchanged until time pi/2ω, the grid reaches 0.

As can be understood from the above-mentioned first to fourth processes, when the DC/AC unit 120 does not emit the wave, the switching transistors S _a1 and S _a2 are alternately switched at intervals, so that the leakage current i _g0 is nonlinear, and further causes distortion, and if the output leakage current i _g0 is excessively distorted, the normal grid-connected process of the inverter system is affected. Therefore, as shown in fig. 9, in the relay self-test stage, it is necessary to make the DC/AC unit 120 wave to output a DC voltage or an AC voltage, and further make the state of the leakage current i _g0 nearly sinusoidal.

Example 1

As shown in fig. 10-13, a leakage current suppression method in relay self-test is applied to a grid-connected process of an inverter system, and an output end of a DC/AC unit 120 of the inverter system is connected with a power grid through a relay group 130; the relay group 130 includes a positive relay group 131 and a negative relay group 132, the positive relay group 131 includes at least two relays connected in series with a positive bus, and the negative relay group 132 includes at least two relays connected in series with a negative bus; a bidirectional switch unit 140 is also connected between the positive and negative output terminals of the DC/AC unit 120; when the forward relay group 131 is closed, the inverter system forms a suppression loop for generating a voltage suppressing leakage current by controlling the DC/AC unit 120 and the bidirectional switch unit 140.

As shown in fig. 11, the DC/AC unit 120 includes switching tubes S _a1、S_a4、S_b1 and S _b4 connected in a bridge type, wherein the switching tubes S _a1 and S _a4 are connected to each other to form a first branch, and the switching tubes S _b1 and S _b4 are connected to each other to form a second branch; the first branch and the second branch are connected in parallel with the positive bus and the negative bus, and the switching tubes S _a1 and S _b4 are close to the positive bus, and the input end of the bidirectional switching unit 140 is connected with the midpoints of the first branch and the second branch respectively; the bidirectional switch unit 140 includes switch tubes S ₂ and S ₃ connected in anti-series; when the relays T ₁ and T ₃ are closed, a suppression circuit is formed by controlling the switching transistors S _a1、S_a4、S_b1、S_b4、S₂ and S ₃. The specific structures of the switching transistors S _a1、S_a4、S_b1、S_b4、S₂ and S ₃ are various, such as a field effect transistor and a thyristor, and in this embodiment, a field effect transistor is preferably used.

Specifically, as shown in fig. 10 and 11, when the forward relay group 131 is closed, the bidirectional switch unit 140 is in an open state, and the DC/AC unit 120 is connected to the power grid through the on switch tubes S _a4 and S _b4, so that the DC/AC unit 120 outputs a differential mode direct current voltage to form a suppression loop, and the voltage value generated by the suppression loop is-V _dc/2, where V _dc is the bus voltage.

It is to be understood that the positive relay group 131 in the present embodiment includes the relays T ₁ and T ₃, and the negative relay group 132 includes the relays T ₂ and T ₄, but in other embodiments, the positive relay group 131 and the negative relay group 132 may include three or more relays, respectively, and the present application is not limited thereto.

According to fig. 11, the impedance circuit for the grid connection of the inverter system can be equivalent, and an equivalent circuit diagram as shown in fig. 12 can be obtained. The output side positive and negative capacitances C _PV+ and C _PV- of the photovoltaic module PV, and the positive and negative bus capacitances C _dc+ and C _dc-, generally, C _PV+=C_PV-=C_PV,C_dc+=C_dc-=Cdc,V_PV=V_dc, of the inverter system mainly consider the ground impedance during grid connection, and the equivalent circuit shown in fig. 12 is simplified, so that a simplified circuit schematic shown in fig. 13 can be obtained.

As shown in fig. 13, the ac component of the leakage current i _g0 is: i _g0=-jω(2C_PV+2C_dc)v_g, it can be known that the leakage current i _g0 is determined by the capacitance to ground of the power grid side and the capacitance to the positive and negative buses, the frequency of the photovoltaic module PV and the power grid is 50Hz, and the alternating current component of the leakage current i _g0 is 50Hz, so that the waveform of the leakage current i _g0 is prevented from being distorted, and the leakage protector is prevented from tripping.

Further, the voltage from the point O to the ground in fig. 13 is v _g+V_dc/2, and as can be obtained in combination with fig. 11, the voltages of the capacitors to the ground of the positive and negative buses are respectively: v _dc+=v_g+V_dc;v_dc-=v_g. Therefore, the withstand voltage value of the capacitance to ground of the positive bus should be greater than (v _g+V_dc), and the withstand voltage value of the capacitance to ground of the negative bus should be greater than v _g.

Further, it is determined whether the relay set 130 is normal by detecting the port voltage v _IO. Specifically, when the port voltage V _IO is dc-V _dc, the relay is normal; when the port voltage v _IO is ac v _g, the relay is stuck.

Example two

Compared to the first embodiment, the present embodiment is different in that: as shown in fig. 14 and 15, when the forward relay group 131 is closed, the bidirectional switch unit 140 is in an open state, and the DC/AC unit 120 is connected to the power grid through the on switch tubes S _a1 and S _b1, so that the DC/AC unit 120 outputs a differential mode direct current voltage to form a suppression loop, and the voltage value generated by the suppression loop is-V _dc/2.

It is to be understood that the positive relay group 131 in the present embodiment includes the relays T ₁ and T ₃, and the negative relay group 132 includes the relays T ₂ and T ₄, but in other embodiments, the positive relay group 131 and the negative relay group 132 may include three or more relays, respectively, and the present application is not limited thereto.

According to fig. 15, the impedance circuit for the grid connection of the inverter system can be equivalent, and an equivalent circuit diagram as shown in fig. 16 can be obtained. The output side positive and negative capacitances C _PV+ and C _PV- of the photovoltaic module PV, and the positive and negative bus capacitances C _dc+ and C _dc-, generally, C _PV+=C_PV-=C_PV,C_dc+=C_dc-=C_dc,V_PV=V_dc, of the inverter system mainly consider the ground impedance during grid connection, and the equivalent circuit shown in fig. 16 is simplified, so that a simplified circuit schematic shown in fig. 17 can be obtained.

As shown in fig. 17, the ac component of the leakage current i _g0 is: i _g0=-jω(2C_PV+2C_dc)v_g, it can be known that the leakage current i _g0 is determined by the capacitance to ground of the power grid side and the capacitance to the positive and negative buses, the frequency of the photovoltaic module PV and the power grid is 50Hz, and the alternating current component of the leakage current i _g0 is 50Hz, so that the waveform of the leakage current i _g0 is prevented from being distorted, and the leakage protector is prevented from tripping.

Further, the voltage from the point O to the ground in fig. 17 is v _g+V_dc/2, and as can be obtained in combination with fig. 15, the voltages of the capacitors to the ground of the positive and negative buses are respectively: v _dc+=v_g;v_dc-=v_g-V_dc. Therefore, the withstand voltage value of the capacitance to ground of the positive bus should be greater than v _g, and the withstand voltage value of the capacitance to ground of the negative bus should be greater than (v _g-V_dc).

Further, it is determined whether the relay set 130 is normal by detecting the port voltage v _IO. Specifically, when the port voltage V _IO is the direct current V _dc, the relay is normal; when the port voltage v _IO is ac v _g, the relay is stuck.

Example III

Compared to the first embodiment, the present embodiment is different in that: as shown in fig. 18 and 19, when the forward relay set 131 is closed, the bidirectional switch unit 140 is in an open state, and the DC/AC unit 120 is connected to the power grid through the on switch tube S _a1, so that the live wire clamp of the power grid is located on the positive bus to form a suppression loop, so as to change the flow path of the common mode current, further avoid the common mode current flowing through the diode of the switch tube S _a1, and prevent the waveform of the leakage current i _g0 from being distorted.

It is to be understood that the positive relay group 131 in the present embodiment includes the relays T ₁ and T ₃, and the negative relay group 132 includes the relays T ₂ and T ₄, but in other embodiments, the positive relay group 131 and the negative relay group 132 may include three or more relays, respectively, and the present application is not limited thereto.

According to fig. 19, the impedance circuit for the inverter system to be connected to the grid can be equivalent, and an equivalent circuit diagram as shown in fig. 20 can be obtained. Wherein the differential mode voltage generated by the DC/AC unit 120 itself is V _dc/2. The output side positive and negative capacitances C _PV+ and C _PV- of the photovoltaic module PV, and the positive and negative bus capacitances C _dc+ and C _dc-, generally, C _PV+=C_PV-=CPV,C_dc+=C_dc-=C_dc,V_PV=V_dc, of the inverter system mainly consider the ground impedance during grid connection, and the equivalent circuit shown in fig. 20 is simplified, so that a simplified circuit schematic shown in fig. 21 can be obtained.

As shown in fig. 21, the ac component of the leakage current i _g0 is: i _g0=-jω(2C_PV+2C_dc)v_g, it can be known that the leakage current i _g0 is determined by the capacitance to ground of the power grid side and the capacitance to the positive and negative buses, the frequency of the photovoltaic module PV and the power grid is 50Hz, and the alternating current component of the leakage current i _g0 is 50Hz, so that the waveform of the leakage current i _g0 is prevented from being distorted, and the leakage protector is prevented from tripping.

Further, the voltage from the point O to the ground in fig. 21 is v _g+V_dc/2, and as can be obtained in combination with fig. 19, the voltages of the capacitors to the ground of the positive and negative buses are respectively: v _dc+=v_g;v_dc-=v_g-V_dc. Therefore, the withstand voltage value of the capacitance to ground of the positive bus should be greater than v _g, and the withstand voltage value of the capacitance to ground of the negative bus should be greater than (v _g-V_dc).

Further, it is determined whether the relay set 130 is normal by detecting the port voltage v _IO. Specifically, when the port voltage v _IO is ac v _g, the relay is stuck. Because the live wire of the power grid is clamped on the positive bus of the inverter system, the influence on a differential mode loop of the system can be avoided, and even if the relay is adhered, the system can not be overflowed.

Example IV

Compared with the third embodiment, the present embodiment is different in that: as shown in fig. 22 and 23, when the positive relay group 131 is closed, the bidirectional switch unit 140 is in an open state, and the DC/AC unit 120 is connected to the power grid through the on switch tube S _a4, so that the live wire clamp of the power grid is located on the negative bus to form a suppression loop, thereby changing the flow path of the common mode current, further avoiding the common mode current from flowing through the diode of the switch tube S _a4, and preventing the waveform of the leakage current i _g0 from being distorted.

It is to be understood that the positive relay group 131 in the present embodiment includes the relays T ₁ and T ₃, and the negative relay group 132 includes the relays T ₂ and T ₄, but in other embodiments, the positive relay group 131 and the negative relay group 132 may include three or more relays, respectively, and the present application is not limited thereto.

According to fig. 23, the impedance circuit for the grid connection of the inverter system can be equivalent, and an equivalent circuit diagram as shown in fig. 24 can be obtained. Wherein the differential mode voltage generated by the DC/AC unit 120 itself is-V _dc/2. The output side positive and negative capacitances C _PV+ and C _PV- of the photovoltaic module PV, and the positive and negative bus capacitances C _dc+ and C _dc-, generally, C _PV+=C_PV-=C_PV,C_dc+=C_dc-=C_dc,V_PV=V_dc, of the inverter system mainly consider the ground impedance during grid connection, and the equivalent circuit shown in fig. 20 is simplified, so that a simplified circuit schematic shown in fig. 25 can be obtained.

As shown in fig. 25, the ac component of the leakage current i _g0 is: i _g0=-jω(2C_PV+2C_dc)v_g, it can be known that the leakage current i _g0 is determined by the capacitance to ground of the power grid side and the capacitance to the positive and negative buses, the frequency of the photovoltaic module PV and the power grid is 50Hz, and the alternating current component of the leakage current i _g0 is 50Hz, so that the waveform of the leakage current i _g0 is prevented from being distorted, and the leakage protector is prevented from tripping.

Further, the voltage from the point O to the ground in fig. 25 is v _g+V_dc/2, and as can be obtained in combination with fig. 23, the voltages of the capacitors to the ground of the positive and negative buses are respectively: v _dc+=v_g+V_dc;v_dc-=v_g. Therefore, the withstand voltage value of the capacitance to ground of the positive bus should be greater than (v _g+V_dc), and the withstand voltage value of the capacitance to ground of the negative bus should be greater than v _g.

Further, it is determined whether the relay set 130 is normal by detecting the port voltage v _IO. Specifically, when the port voltage v _IO is ac v _g, the relay is stuck. Because the live wire of the power grid is clamped on the negative bus of the inverter system, the influence on a differential mode loop of the system can be avoided, and even if the relay is adhered, the system can not be overflowed.

Example five

Compared with the fourth embodiment, the present embodiment is different in that: as shown in fig. 26 and 27, when the forward relay group 131 is closed, the switching tubes S ₂ and S ₃ are both in a conductive state, and form a suppression loop with the switching tube S _a1 or the switching tube S _a4 that are conductive in the DC/AC unit 120.

It is to be understood that the positive relay group 131 in the present embodiment includes the relays T ₁ and T ₃, and the negative relay group 132 includes the relays T ₂ and T ₄, but in other embodiments, the positive relay group 131 and the negative relay group 132 may include three or more relays, respectively, and the present application is not limited thereto.

According to fig. 27, the impedance circuit for the inverter system to be connected to the grid can be equivalent, and an equivalent circuit diagram as shown in fig. 28 can be obtained. Wherein the differential mode voltage generated by the DC/AC unit 120 itself is-V _dc/2. The output side positive and negative capacitances C _PV+ and C _PV- of the photovoltaic module PV, and the positive and negative bus capacitances C _dc+ and C _dc-, generally, C _PV+=C_PV-=C_PV,C_dc+=C_dc-=C_dc,V_PV=V_dc, of the inverter system mainly consider the ground impedance during grid connection, and the equivalent circuit shown in fig. 28 is simplified, so that a simplified circuit schematic shown in fig. 29 can be obtained.

As shown in fig. 29, the ac component of the leakage current i _g0 is: i _g0=-jω(2C_PV+2C_dc)v_g, it can be known that the leakage current i _g0 is determined by the capacitance to ground of the power grid side and the capacitance to the positive and negative buses, the frequency of the photovoltaic module PV and the power grid is 50Hz, and the alternating current component of the leakage current i _g0 is 50Hz, so that the waveform of the leakage current i _g0 is prevented from being distorted, and the leakage protector is prevented from tripping.

Further, the voltage to ground at the point O in fig. 29 is v _g+V_dc/2, and as can be obtained in conjunction with fig. 27, the voltages of the capacitors to ground of the positive and negative buses are respectively: v _dc+=v_g+V_dc;v_dc-=v_g. Therefore, the withstand voltage value of the capacitance to ground of the positive bus should be greater than (v _g+V_dc), and the withstand voltage value of the capacitance to ground of the negative bus should be greater than v _g.

Further, it is determined whether the relay set 130 is normal by detecting the port voltage v _IO. Specifically, when the port voltage V _IO is the direct current V _dc, the relay is normal; when the port voltage v _IO is ac v _g, the relay is stuck.

The foregoing has outlined the basic principles, features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made therein without departing from the spirit and scope of the invention, which is defined by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. The leakage current suppression method in the relay self-inspection is applied to the grid-connected process of an inverter system, and the output end of a DC/AC unit of the inverter system is connected with a power grid through a relay group; the relay group comprises a positive relay group and a negative relay group, the positive relay group comprises at least two relays connected in series with a positive bus, and the negative relay group comprises at least two relays connected in series with a negative bus; a bidirectional switch unit is also connected between the positive output terminal and the negative output terminal of the DC/AC unit; wherein when the forward relay group is closed, the inverter system forms a suppression loop for generating a voltage suppressing leakage current by controlling the DC/AC unit and the bidirectional switch unit.

2. The leakage current suppressing method in a relay self-test according to claim 1, wherein the DC/AC unit includes switching tubes S _a1、S_a4、S_b1 and S _b4 connected in a bridge type, wherein the switching tubes S _a1 and S _a4 are connected to each other to form a first branch, and the switching tubes S _b1 and S _b4 are connected to each other to form a second branch; the first branch and the second branch are connected in parallel with positive and negative buses, and the switching tubes S _a1 and S _b4 are close to the positive buses; when the forward relay group is closed, the suppression loop is formed by controlling the switching tube S _a1、S_a4、S_b1、S_b4 and the bidirectional switching unit.

3. The leakage current suppressing method in a relay self-test according to claim 2, wherein when the positive relay group is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to a power grid through the on switch tubes S _a4 and S _b4, so that the DC/AC unit outputs a differential mode direct current voltage to form a suppressing loop.

4. The leakage current suppressing method in a relay self-test according to claim 2, wherein when the positive relay group is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to a power grid through the on switch tubes S _a1 and S _b1, so that the DC/AC unit outputs a differential mode direct current voltage to form a suppressing loop.

5. The leakage current suppressing method in a relay self-test according to claim 2, wherein when the positive relay group is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to a power grid through the on switch tube S _a1, so that a live wire clamp of the power grid is located on a positive bus to form a suppressing loop.

6. The leakage current suppressing method in a relay self-test according to claim 2, wherein when the positive relay group is closed, the bidirectional switch unit is in an off state, and the DC/AC unit is connected to a power grid through the on switch tube S _a4, so that a live wire clamp of the power grid is located on a negative bus to form a suppressing loop.

7. The leakage current suppressing method in a relay self-test according to claim 2, wherein the bidirectional switching unit includes switching transistors S ₂ and S ₃ connected in anti-series, and when the positive relay group is closed, the switching transistors S ₂ and S ₃ are both in a conductive state and form a suppressing loop with the switching transistor S _a1 or the switching transistor S _a4 that is conductive in the DC/AC unit.

8. The leakage current suppressing method in a relay self-test according to claim 3, 6 or 7, wherein a withstand voltage value of a positive ground capacitance of the inverter system is larger than (V _g+V_dc), a withstand voltage value of a negative ground capacitance is larger than V _g, wherein V _dc is a bus voltage and V _g is a grid voltage.

9. The leakage current suppressing method in relay self-test according to claim 4 or 5, wherein a withstand voltage value of a positive ground capacitance of the inverter system is greater than V _g, a withstand voltage value of a negative ground capacitance is greater than (V _g-V_dc), wherein V _dc is a bus voltage and V _g is a grid voltage.

10. The method of any one of claims 1 to 7, wherein the positive relay group includes relays T ₁ and T ₃, the negative relay group includes relays T ₂ and T ₄, and the operation of the relay group is determined by detecting a port voltage v _IO.