CN117954410A

CN117954410A - Semiconductor packaging structure

Info

Publication number: CN117954410A
Application number: CN202211266726.0A
Authority: CN
Inventors: 石宏龙
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-17
Filing date: 2022-10-17
Publication date: 2024-04-30
Also published as: WO2024082345A1

Abstract

The present disclosure provides a semiconductor package structure, including a package substrate and a die, the package substrate including a preset package channel, a first contact and a second contact; the die comprises a first package die and a second package die, and the projection of a first pin of the first package die and a second pin of the second package die on the package substrate are overlapped; the first pin is electrically connected with the first contact through a first wire, the second pin is electrically connected with the second contact through a second wire, and the projection of the mounting end part of the first wire on the packaging substrate is staggered with the projection of the mounting end part of the second wire on the packaging substrate. In the method, the mounting ends of the wires connected with the pins belonging to different packaging grains are staggered at the corresponding pins of two packaging grains which are arranged in a stacked manner, so that the deflection angle of the conductive contact is smaller, and the packaging process requirement is met; and the distance between the conductive contact and the packaging crystal grain can be reduced, so that the length of the lead is reduced, and the packaging cost is reduced.

Description

Semiconductor packaging structure

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor package structure.

Background

Currently, a plurality of dies (Die) are disposed on a package substrate in a stacked manner, and the memory chips are, for example, LPDDR (Low Power Double Data Rate, low power memory technology) chips.

The multiple dies are stacked, and in the packaging process, some pins corresponding up and down exist in the stacked dies and are required to be led out of connecting wires, and the connecting wires are connected to the same packaging channel through the contact plates, namely, two connecting wires are required to be led out and then connected to the two contact plates at the same physical position where the contact plates are overlapped. The added connecting wires and the contact plates occupy a lot of space, and push signal wires of other pins, so that the deflection angle of the connecting wires led out by the pins at the edge of the crystal grain is overlarge, and when the existing packaging technology is used for processing, the yield of the semiconductor packaging structure is not high, and the packaging technology requirements cannot be met.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a semiconductor package structure including:

The packaging substrate comprises at least one preset packaging channel and at least one preset conductive contact group, wherein the preset conductive contact group is arranged corresponding to the preset packaging channel, each preset conductive contact group comprises a first contact and a second contact, and the first contact and the second contact are respectively and electrically connected to the preset packaging channel corresponding to the preset conductive contact group to which the first contact and the second contact belong;

The packaging substrate comprises a plurality of crystal grains, wherein the crystal grains are stacked and arranged on the packaging substrate, the crystal grains comprise at least one group of packaging crystal grain groups, the packaging crystal grain groups comprise first packaging crystal grains and second packaging crystal grains which are correspondingly arranged, and projection of a first pin of the first packaging crystal grain and a second pin of the second packaging crystal grain on the packaging substrate coincide;

the first pin is electrically connected with the first contact piece through a first wire, the mounting end part of the first wire is connected with the first pin, the second pin is electrically connected with the second contact piece through a second wire, the mounting end part of the second wire is connected with the second pin, and the projection of the mounting end part of the first wire on the packaging substrate and the projection of the mounting end part of the second wire on the packaging substrate are staggered.

In one embodiment, the first pin and the second pin each have a first end and a second end opposite to each other along a first direction, wherein the first direction is defined as an arrangement direction of the pins of each die;

the mounting end of the first wire is located at the first end of the first pin, and the mounting end of the second wire is located at the second end of the second pin.

In one embodiment, each die further includes a third pin, and the lengths of the first pin and the second pin in the first direction are greater than or equal to twice the length of the third pin in the first direction.

In one embodiment, a first gap is formed between any two adjacent third pins;

In the first direction, the length of the first pin is equal to the sum of the length of the first gap and twice the length of the third pin.

In one embodiment, the first pin and the second pin each include a first sub-pin and a second sub-pin, and the first sub-pin and the second sub-pin are arranged along a first direction, where the first direction is defined as an arrangement direction of pins of each die;

the mounting end part of the first lead is electrically connected with a first sub-pin of the first pin;

the mounting end of the second wire is electrically connected with a second sub-pin of the second pin.

In one embodiment, each die further includes a third pin, and the third pin, the first sub-pin, and the second sub-pin are equal in length in the first direction.

In one embodiment, a first gap is formed between any two adjacent third pins, and a second gap is formed between the first sub-pin and the second sub-pin;

The first gap and the second gap are equal in length in the first direction.

In one embodiment, the projection of the first pin and the second pin on the packaging substrate is 250-260 μm away from the preset conductive contact group in the second direction;

wherein the second direction is perpendicular to the first direction.

In one embodiment, the third pin is electrically connected to the third contact through a third wire, and the extending directions of two adjacent third contacts are substantially parallel.

In one embodiment, an angle between extending directions of two adjacent third contacts is smaller than 5 °.

In one embodiment, each of the dies includes a plurality of pins arranged along the first direction array, the first pin, and the third pin belonging to the pins;

The packaging substrate comprises a plurality of conductive contacts, and the first contact, the second contact and the third contact belong to the conductive contacts;

And along the first direction, an included angle between the conductive contact corresponding to the pin positioned at the edge of the die and a second direction is smaller than 35 degrees, wherein the second direction is perpendicular to the first direction, and the second direction is parallel to the packaging substrate.

In one embodiment, the package substrate includes a top surface and a bottom surface, the conductive contact is disposed on the top surface of the package substrate, and the bottom surface of the package substrate is provided with a bonding pad;

the packaging substrate further comprises a conductive plug, wherein the conductive plug penetrates through the packaging substrate, and the conductive plug is respectively connected with the conductive contact and the bonding pad.

In one embodiment, the first pin and the second pin include an ODT pin, a CS pin, and a CKE pin.

In one embodiment, adjacent ones of the die are adhesively connected by a die attach film; and/or the number of the groups of groups,

The crystal grain connected with the packaging substrate is bonded and connected with the packaging substrate through the wafer bonding film.

In one embodiment, the first contact and the second contact are substantially parallel; and/or the number of the groups of groups,

The extending direction of projection of the first lead on the packaging substrate is parallel to the extending direction of the first contact; and/or the number of the groups of groups,

The extending direction of the projection of the second wire on the packaging substrate is parallel to the extending direction of the second contact.

In one embodiment, the angle between the extending direction of the first contact and the extending direction of the second contact is 2 ° to 3 °.

In the semiconductor packaging structure provided by the disclosure, at the corresponding pins of two stacked packaging crystal grains, the mounting ends of the wires connected with the pins belonging to different packaging crystal grains are staggered, so that the deflection angle of the conductive contact is smaller, and the packaging process requirement is met; and the distance between the conductive contact and the packaging crystal grain can be reduced, so that the length of the lead is reduced, and the packaging cost is reduced.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a semiconductor package structure shown according to an exemplary embodiment.

Fig. 2 is a schematic diagram of a semiconductor package structure shown according to an exemplary embodiment.

Fig. 3 is a schematic diagram of a semiconductor package structure shown according to an exemplary embodiment.

Fig. 4 is a schematic diagram of a semiconductor package structure shown according to an exemplary embodiment.

Fig. 5 is a schematic diagram of a semiconductor package structure shown according to an exemplary embodiment.

Fig. 6 to 8 show schematic views of the semiconductor package structure of the comparative embodiment.

Fig. 9 is a simulation effect diagram of a semiconductor package structure shown according to an exemplary embodiment.

Fig. 10 is a simulation effect diagram of a semiconductor package structure in a comparative example.

Reference numerals:

100', a package substrate; 110', preset packaging channels; 120', conductive contacts; 121', first contacts; 122', a second contact; 123', a third contact; 210', a first package die; 211', a first pin; 220', a second package die; 221', a second pin; 231', a third pin; 300', wires; 310', a first wire; 320', a second wire; 330', a third wire; 500', target mark;

100. packaging a substrate; 100a, top surface; 100b, bottom surface; 110. presetting a packaging channel; 120. a conductive contact; 121. a first contact; 122. a second contact; 123. a third contact; 130. a bonding pad;

200. A crystal grain; 210. a first package die; 211. a first pin; 211a, a first sub-pin of the first pin; 211b, a second sub-pin of the first pin; 220. a second package die; 221. a second pin; 221a, a first sub-pin of the second pin; 221b, a second sub-pin of the second pin; 230. a third package die; 231. a third pin; 240. a fourth package die;

300. a wire; 310. a first wire; 320. a second wire; 330. a third wire;

400. A wafer bonding film;

500. And (5) marking a target.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In order to avoid excessive wire deflection angle, the wire deflection angle can be reduced by elongating the wire, which increases not only the packaging cost, but also the signal integrity.

As shown in fig. 6 and 7, a semiconductor package structure in a comparative embodiment is shown, which includes a package substrate 100', a preset package channel 110', a conductive contact 120' (including, in particular, a first contact 121', a second contact 122', a third contact 123 '), a first package die 210', a first pin 211', a second package die 220', a second pin 221', a third pin 231', a wire 300' (including, in particular, a first wire 310', a second wire 320', a third wire 330 '), and the like. Wherein, the mounting end of the first wire 310' may be located at the geometric center of the first pin 211', the mounting end of the second wire 320' may be located at the geometric center of the second pin 221', and the projections of the mounting ends of the first wire 310' and the second wire 320' on the package substrate 100' coincide.

Fig. 7 shows a possible example of other comparative embodiments, referring to fig. 7, referring to the orientation shown in the drawing, the first conductive line 310 'is inclined rightward, the second conductive line 320' is inclined leftward, limited by the physical dimensions of the first contact 121 'and the second contact 122', or a large inclination angle is required for the first conductive line 310 'and the second conductive line 320' in order to avoid electrical connection between the first conductive line 310 'and the second conductive line 320'. It can be appreciated that, when the number of the first pins 211' on the first package die 210' and the second pins 221' on the second package die 220' increases, the inclination angle of the conductive contact 120' corresponding to the pins located at the edge of the die is larger, which cannot meet the basic requirements of the packaging process, and also affects the product yield.

Fig. 7 and 8 show a semiconductor package structure in another comparative embodiment, in which the inclination angle of the conductive contact is reduced by increasing the distance between the conductive contact 120' and the die (y direction shown in fig. 8) in the scheme shown in fig. 8. As compared with the semiconductor package structure shown in fig. 7, it can be determined that d3 > d2, and thus, the structure shown in fig. 8 may cause the wires of the semiconductor package structure to become longer, longer wires may cause reflection noise to be enhanced, affecting signal integrity, and also increasing the cost of the wires.

Taking an ODT (termination resistance on on die termination chip) pin connected by the first wire 310 'and the second wire 320' as an example, during data reading and writing, when the processor accesses the first package die 210', the ODT pin of the first wire 310' is opened, and the ODT pin can counteract most of signal reflection. At this time, however, the second wire 320' connected to the second package die 220' is used as one branch of the data read/write link, and the ODT pin of the second wire 320' is in a closed state, so that the signal reflection effect cannot be counteracted, so that the signal reflection on the second wire 320' returns to the data read/write main link, i.e. the link accessing the first package die 210' through the first wire 310', thereby affecting the first wire 310', and affecting the signal integrity.

In order to solve the problems of excessive offset angles and poor signal integrity of the contact and the wire in the above comparative embodiment, the embodiment of the disclosure provides a semiconductor package structure, which includes a package substrate and a plurality of dies, the package substrate includes at least one preset package channel and at least one preset conductive contact group, the preset conductive contact group is disposed corresponding to the preset package channel, each preset conductive contact group includes a first contact and a second contact, the first contact and the second contact are respectively electrically connected to the preset package channel corresponding to the preset conductive contact group to which the first contact and the second contact belong, the plurality of dies are stacked on the package substrate, the plurality of dies include at least one group of package dies, the package dies include a first package die and a second package die which are disposed correspondingly, the projection of the first pin of the first package die and the second pin of the second package die overlap on the package substrate, the first pin is electrically connected to the first contact through the first wire, the mounting end of the first wire is connected to the first pin, the second pin is electrically connected to the second wire through the second wire, and the projection of the second pin is disposed on the projection end of the second wire, and the projection of the second wire is staggered on the package substrate. In the method, the mounting ends of the wires connected with the pins belonging to different packaging grains are staggered at the corresponding pins of two packaging grains which are arranged in a stacked manner, so that the deflection angle of the conductive contact is smaller, and the packaging process requirement is met; and the distance between the conductive contact and the packaging crystal grain can be reduced, so that the length of the lead is reduced, and the packaging cost is reduced.

In an exemplary embodiment of the present disclosure, as shown in fig. 1 to 5, the embodiment of the present disclosure provides a semiconductor package structure, such as an LPDDR chip. As shown in fig. 1, the semiconductor package structure includes a package substrate 100 and a plurality of dies 200, the dies 200 are integrated circuit structures made of semiconductor materials, different dies 200 can perform a predetermined function, the package substrate 100 is used as a package body for supporting the plurality of dies 200, and the plurality of dies 200 are stacked (z direction shown in fig. 1) on the package substrate 100.

Between die 200 and package substrate 100, and between die 200 and die 200, die attach film 400, such as die attach film (DIE ATTACH FILM, DAF), may be adhesively bonded using die attach film 400.

In this embodiment, as shown in fig. 2 to 5, the package substrate 100 includes at least one preset package channel 110, and at least one preset conductive contact group, that is, the first contact 121 and the second contact 122 (for example, gold fingers), the preset package channel 110, such as an ODT (on DIE TERMINAL, termination resistor) signal channel, a CS (CHIP SELECT ) signal channel, or a CKE (clock enables, clock enable) signal channel, the preset conductive contact group is disposed corresponding to the preset package channel 110, that is, the number of preset conductive contact groups is equal to the number of preset package channels 110, and each preset conductive contact group is connected to one preset package channel 110, so that when writing or reading data, the preset package channel 110 can select one contact in the preset conductive contact group to communicate, and further connect with a die connected to the contact.

In this embodiment, as shown in fig. 1, the plurality of dies 200 form at least one package die group, and the projections of the pins of the plurality of dies 200 on the package substrate 100 in each package die group overlap. The leads of die 200, also referred to as die pads (die pads), are connected to the internal integrated circuits (not shown) of die 200, and the transfer of signals between the integrated circuits and package substrate 100 can be accomplished by providing signal conductors 300 between the leads of die 200 and package substrate 100.

Referring to fig. 1, taking an example in which four dies 200 are disposed on a package substrate 100 and the four dies 200 form two package die groups, the four dies 200 are a first package die 210, a second package die 220, a third package die 230, and a fourth package die 240, respectively, wherein the four dies 200 are stacked in the order of the first package die 210, the third package die 230, the second package die 220, and the fourth package die 240 on a top surface 100a of the package substrate 100 in the order of the first package die 210, the third package die 230, the second package die 220, and the fourth package die 240, wherein the first package die 210 and the second package die 220 form one package die group, and the third package die 230 and the fourth package die 240 form another package die group.

In this embodiment, the first package die 210 and the second package die 220 are taken as examples, so as to explain the technical solution of the present disclosure.

Referring to fig. 1 to 5, projections of the first pins 211 (e.g., die pads) of the first package die 210 and the second pins 221 of the second package die 220 on the package substrate 100 overlap. Each preset conductive contact group comprises a first contact 121 and a second contact 122, and the first contact 121 and the second contact 122 are respectively electrically connected to the preset packaging channel 110 corresponding to the preset conductive contact group to which the first contact 121 and the second contact 122 belong. The first pin 211 is electrically connected to the first contact 121 through a first wire 310, and the second pin 221 is electrically connected to the second contact 122 through a second wire 320.

As can be seen from the above, in the same package die set, the first pins 211 and the second pins 221 respectively disposed on the two package dies are simultaneously connected to one preset package channel 110, and when data is read or written, a control signal can be transmitted to the first pins 211 or the second pins 221 through the same preset package channel 110 so as to be in communication connection with the first package die 210 or the second package die 220. The first pin 211 and the second pin 221 may be, for example, an ODT pin, a CS (CHIP SELECT ) pin, a CKE (clock enables, clock enable) pin, and the like.

Referring to fig. 2 to 5, the mounting end of the first wire 310 is connected to the first pin 211, the mounting end of the second wire 320 is connected to the second pin 221, the projection of the mounting end of the first wire 310 on the package substrate is a first projection, the projection of the mounting end of the second wire 320 on the package substrate is a second projection, and the first projection and the second projection are staggered, that is, the mounting end of the first wire 310 and the mounting end of the second wire 320 are staggered. The extending direction of the first projection is parallel to the extending direction of the first contact 121, and the extending direction of the second projection is parallel to the extending direction of the second contact 122, so that the wiring manner is more regular, and the wiring is convenient.

Taking the orientation shown in fig. 2 and 4 as an example, the mounting end of the first wire 310 is located at the left side of the central axis of the first pin 211 (i.e., the first end of the first pin 211, described in detail later), the mounting end of the second wire 320 is located at the right side of the central axis of the second pin 221 (i.e., the second end of the second pin 221, described in detail later), and the first wire 310 is inclined to the left (the reverse direction of the x direction shown in fig. 3) to connect with the first contact 121, and the second wire 320 is inclined to the right (the x direction shown in fig. 3) to connect with the second contact 122. It should be noted that, the conductive contact 120 is inclined to form an angle between the extending direction of the conductive contact 120 and a second direction (y direction shown in fig. 3), which is perpendicular to the vertical direction (z direction shown in fig. 2) and perpendicular to the first direction (x direction shown in fig. 2). The first contact 121 and the second contact 122 are substantially parallel or parallel, for example, an angle between an extending direction of the first contact 121 and an extending direction of the second contact 122 is 2 ° to 3 °.

Referring to fig. 3 and 7, fig. 3 is a semiconductor package structure provided in an embodiment of the present disclosure, and fig. 7 is a semiconductor package structure in a comparative embodiment, where, compared with the semiconductor package structure in a comparative embodiment, in a case where the distance between the conductive contact 120 and the die 200 is equal (in the y direction shown in fig. 3), that is, d1=d2, in the present disclosure, the mounting ends of the first conductive wire 310 and the second conductive wire 320 are staggered, so that the inclination angle of the conductive contact 120 is reduced, and further, the inclination angle of the conductive contact 120 corresponding to the edge pin of the die 200 is reduced, so that the packaging difficulty is reduced, the packaging requirement is more easily satisfied, and meanwhile, the product yield is also improved. The inclination angle of the conductive contact 120 is reduced, and the distance d1 between the conductive contact 120 and the die 200 is reduced, so that the amount of wires is reduced due to the fact that the materials of the wires are gold or copper, the packaging cost is reduced, and meanwhile, the signal integrity is improved.

In the embodiment of the disclosure, at the corresponding pins of two stacked package dies, the mounting ends of the wires connected with the pins belonging to different package dies are staggered, so that the deflection angle of the conductive contact is smaller, and the package process requirement is met; and the distance between the conductive contact and the packaging crystal grain can be reduced, so that the length of the lead is reduced, and the packaging cost is reduced.

In an exemplary embodiment, as shown in fig. 1 to 5, the difference between the present embodiment and the above-described embodiment is that, in the present embodiment, as shown in fig. 2 and 3, the first pins 211 and the second pins 221 each have opposite first and second ends along a first direction, wherein the first direction is defined as an arrangement direction of the pins of each die 200, and the first direction is the x direction shown in fig. 3. In the example of the orientation shown in fig. 3, the first end and the second end are not limited to the left and right end portions of the pin, and for example, the central axis of the pin may be defined as a boundary, the first end determined to be the pin on the right side of the central axis, and the second end determined to be the pin on the left side of the central axis.

In one example, referring to fig. 3, the mounting end of the first wire 310 is located at the first end (right end in the drawing) of the first pin 211, and the mounting end of the second wire 320 is located at the second end (left end in the drawing) of the second pin 221, so that the projections of the first wire 310 and the mounting end of the second wire 320 on the package substrate 100 are staggered, reducing the inclination angle of the wires and the conductive contacts.

As shown in fig. 2 to 5, each die 200 further includes a third lead 231, and the third lead 231 may be electrically connected to the third contact 123 on the package substrate 100 through a third wire 330, and the extending directions of two adjacent third contacts 123 are substantially parallel or parallel. It should be noted that, the projections of the corresponding third pins 231 of the two stacked dies 200 on the package substrate 100 overlap, but only one of the two corresponding third pins 231 belonging to the two dies 200 is connected to the contact through a wire, and is further connected to the package channels, that is, the package channels corresponding to the third pins 231, and each package channel is connected to only one pin. In one example, the included angle between the extending directions of two adjacent third contact pieces 123 is smaller than 5 °, and the offset angle of the third contact pieces is smaller due to the smaller included angle of the third contact pieces 123, which can reduce the wire bonding length and reduce the signal loss. For ease of understanding the technical solution of the present disclosure, for example, the dimensional parameter of the third pin 231 may be regarded as being consistent with the pins in the comparative embodiment.

Referring to fig. 3, in the first direction (x-direction shown in fig. 3), the lengths of the first and second pins 211 and 221 are greater than or equal to twice the length of the third pin 231. In this embodiment, by increasing the lengths of the first pin 211 and the second pin 221, the extent of staggering the projection of the mounting end of the first wire 310 and the projection of the mounting end of the second wire 320 on the package substrate 100 is increased, so as to reduce the inclination angle of the wire 300 and the conductive contact 120, and also shorten the distance between the conductive contact 120 and the die 200, save the wire cost, and reduce the reflection noise existing between the first wire 310 and the second wire 320, thereby improving the signal integrity.

Referring to fig. 3, a distance d1 between the conductive contact 120 and the die 200, that is, a distance d1 between a projection of the first pin 211 and the second pin 221 on the package substrate 100 and a preset conductive contact group in the second direction (y direction shown in fig. 3), and referring to the structure in the disclosure, the distance d1 can be shortened to 250 μm-260 μm, and compared with the distance between the conductive contact and the die in fig. 8 (d 3=500 um in fig. 8), the distance d1 is obviously reduced, the amount of wires is saved, and the package cost is reduced.

It can be known from experiments, experience, etc. that the longer the length of the wire 300, the greater the reflection intensity, and from the perspective of signal integrity, the shorter the wire, the better the signal integrity, and in this embodiment, by reducing the lengths of the first wire 310 and the second wire 320, the signal integrity is improved.

In one embodiment, as shown in fig. 3, there is a first gap between any two adjacent third pins 231, and in the first direction (x-direction shown in fig. 3), the length of the first pin 211 is equal to the sum of the length of the first gap and twice the length of the third pins 231, i.e., the first pin 211 occupies the space of the two third pins 231 and the first gap to provide enough area for the mounting ends of the first and second wires 310 and 320 to be distributed. In other possible examples (not shown in the drawings), the length of the first pin 211 may also be smaller than the sum of the length of the first gap and twice the length of the third pin 231, and may also be larger than the sum of the length of the first gap and twice the length of the third pin 231.

In an exemplary embodiment, as shown in fig. 1 to 5, the present disclosure provides a semiconductor package structure, and the semiconductor package structure in this embodiment is different from the above-described embodiments in that, as shown in fig. 4 and 5, the first and second pins 211 and 221 each include first and second sub-pins arranged along a first direction defined as an arrangement direction of pins of each die 200, that is, an x-direction shown in fig. 5. The functions of the first sub-pin 211a of the first pin and the second sub-pin 211b of the first pin may be identical, and the functions of the first sub-pin 221a of the second pin and the second sub-pin 221b of the second pin may be identical, so that connection errors can be avoided when the wires 300 are connected, and the wire connection speed can be improved.

In one example, referring to fig. 4 and 5, the mounting end of the first wire 310 is electrically connected with the first sub-pin 211a of the first pin, and the mounting end of the second wire 320 is electrically connected with the second sub-pin 221b of the second pin, so that the projection of the mounting end of the first wire 310 and the mounting end of the second wire 320 on the package substrate 100 are staggered, thereby reducing the inclination angle of the conductive contact 120.

In one embodiment, as shown in fig. 4 and 5, each die 200 further includes a third pin 231, the first sub-pin, and the second sub-pin being equal in length in a first direction (x-direction shown in fig. 5).

For convenience of explanation of the technical solution of the present disclosure, the parameters of the third pin 231 may be regarded as the same as those of the pins in the comparative embodiment, and the third pin 231, the third wire 330 and the third contact 123 are described in the foregoing embodiments, which are not repeated here. In this embodiment, by arranging the first pin 211 and the second pin 221 in the form of two sub-pins, and the length of each sub-pin is the same as that of the third pin 231, when the first wire 310 and the second wire 320 are arranged, the mounting ends of the first wire 310 and the second wire 320 can be respectively arranged on the first sub-pin and the second sub-pin, so that the projections of the mounting ends of the first wire 310 and the second wire 320 on the package substrate 100 are staggered.

In this embodiment, the lengths of the first sub-pins, the second sub-pins and the third pins 231 in the first direction are equal, so that the manufacturing process of the die 200 can be simplified.

In one example, as shown in fig. 4 and 5, there is a first gap between any adjacent two third pins 231, there is a second gap between the first and second sub-pins, and the lengths of the first and second gaps in the first direction (x direction shown in fig. 5) are equal.

In other possible examples (not shown in the drawings), the length of the second gap in the first direction may also be greater than the first gap, or may be less than the first gap.

In one exemplary embodiment, as shown in fig. 1 to 5, the disclosed embodiment provides a semiconductor package structure including a package substrate 100 and a plurality of dies 200. The semiconductor package structure in this embodiment also includes all the structures, devices, and the like designed in the above-described respective embodiments.

In this embodiment, as shown in fig. 2 to 5, each die 200 includes a plurality of pins arranged in an array along a first direction (x-direction shown in fig. 2), the first pin 211, the second pin 221 and the third pin 231 all belong to pins, the package substrate 100 includes a plurality of conductive contacts 120, the conductive contacts 120 may be referred to as gold fingers (connecting finger), and the first contact 121, the second contact 122 and the third contact 123 all belong to the conductive contacts 120.

Referring to fig. 3 and 5, on a straight line in the first direction (x direction shown in fig. 3), the conductive contact 120 corresponding to the lead at the edge of the die 200 has a maximum deflection angle, where the deflection angle refers to an angle between the extending direction of the conductive contact 120 and the second direction (y direction shown in fig. 3), and the maximum deflection angle is less than 35 °.

In one embodiment, as shown in fig. 1, the package substrate 100 includes a top surface 110a and a bottom surface 100b, the conductive contact 120 is disposed on the top surface 100a of the package substrate 100, and the bottom surface 100b of the package substrate 100 is provided with a pad 130, where the pad 130 is a pin of the semiconductor package structure.

In an application scenario, referring to fig. 1 to 5, the bonding pad 130 may be fixedly connected with other devices that need to be packaged by soldering, so that an electrical connection is formed between the semiconductor package structure and the devices. The package substrate 100 further includes conductive plugs (not shown) penetrating the package substrate 100, the conductive plugs respectively connecting the conductive contacts and the pads 130, or other structures requiring electrical connection between the top surface 100a and the bottom surface 100b of the package substrate 100 through the conductive plugs, the conductive plugs having good conductive properties, such as may be made of a metal material,

Fig. 9 is a simulation effect diagram of a semiconductor package structure according to an embodiment of the present disclosure, and fig. 10 is a simulation effect diagram of a semiconductor package structure according to a comparative embodiment, where a signal transmission rate used in the simulation is 4266Mbps.

As can be seen from simulation results, the target mark 500 (eye mask) of the semiconductor package structure provided by the present disclosure is larger than the target mark 500' of the comparative embodiment, the target mark 500 is also referred to as an eye pattern, the larger the target mark 500 is, the smaller crosstalk noise is, and the edge d4 (margin) of the present disclosure is larger than the edge d5 of the comparative embodiment in the case that the target mark 500 is the same in size, so that the semiconductor package structure (i.e., chip) provided by the embodiment of the present disclosure operates more stably.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor package structure, the semiconductor package structure comprising:

2. The semiconductor package according to claim 1, wherein the first and second leads each have opposite first and second ends along a first direction, wherein the first direction is defined as an arrangement direction of the leads of each die;

3. The semiconductor package according to claim 2, wherein each of the dies further comprises a third pin, and a length of the first pin and the second pin in the first direction is greater than or equal to twice a length of the third pin in the first direction.

4. A semiconductor package according to claim 3, wherein any adjacent two of the third pins have a first gap therebetween;

5. The semiconductor package according to claim 1, wherein the first and second leads each include first and second sub-leads arranged along a first direction defined as an arrangement direction of the leads of each die;

6. The semiconductor package according to claim 5, wherein each die further comprises a third pin, the first sub-pin, and the second sub-pin being equal in length in the first direction.

7. The semiconductor package according to claim 6, wherein a first gap is provided between any two adjacent third pins, and a second gap is provided between the first sub-pin and the second sub-pin;

The first gap and the second gap are equal in length in the first direction.

8. The semiconductor package according to any one of claims 2 to 7, wherein a distance between a projection of the first and second leads on the package substrate and the predetermined set of conductive contacts in the second direction is 250 μm to 260 μm;

wherein the second direction is perpendicular to the first direction.

9. The semiconductor package according to claim 3 or 6, wherein the third pin is electrically connected to the third contact through a third wire, and the extending directions of two adjacent third contacts are substantially parallel.

10. The semiconductor package according to claim 9, wherein an included angle between extending directions of two adjacent third contacts is less than 5 °.

11. The semiconductor package according to claim 9, wherein each of the dies includes a plurality of pins arranged in the first direction array, the first pin, and the third pin belonging to the pins;

12. The semiconductor package according to claim 11, wherein the package substrate includes a top surface and a bottom surface, the conductive contact is disposed on the top surface of the package substrate, and the bottom surface of the package substrate is provided with a bonding pad;

13. The semiconductor package according to any one of claims 1-7, wherein the first pin and the second pin comprise an ODT pin, a CS pin, and a CKE pin.

14. The semiconductor package according to any one of claims 1 to 7, wherein adjacent ones of the dies are bonded by a die attach film; and/or the number of the groups of groups,

15. The semiconductor package according to any one of claims 1-7, wherein the first and second contacts are substantially parallel; and/or the number of the groups of groups,

16. The semiconductor package according to claim 15, wherein an angle between the extending direction of the first contact and the extending direction of the second contact is 2 ° to 3 °.