CN218447230U - Solid state disk - Google Patents

Abstract

The utility model discloses a solid state hard drives, wherein, solid state hard drives includes: the packaging structure comprises a substrate, a packaging layer, a main control chip, a storage chip and a component; the main control chip, the storage chip and the components are all attached to one side of the substrate and are electrically connected with the conducting circuit of the substrate; the packaging layer is arranged on one side of the substrate to package the main control chip, the storage chip and the component; 247 pins are arranged on the other side of the substrate, each pin is electrically connected with the conductive circuit of the substrate, and the 247 pins are positioned in a 21-row 16-column square matrix. Through the structure, the utility model discloses make solid state hard disk can reduce whole solid state hard disk's size, satisfy the miniaturized dimensional requirement of solid state hard disk.

Description

Solid state disk

Technical Field

The utility model discloses be applied to solid state hard drives's technical field.

Background

Solid State Disks (SSDs) are hard disks made with arrays of solid state electronic memory chips, which are characterized by fast read and write, light weight, low energy consumption, small size, etc.

At present, with the rapid development of high and new technologies in various industries, the size requirement of solid state disks is higher and higher, and the number of miniaturized solid state disks in the market is also increasing, such as mSATA, m.2, and the like.

However, when the miniaturized hard disk is faced with some embedded application scenarios with high integration, miniaturization and high reliability requirements, the solid state disk of the above type still cannot meet the size requirement.

SUMMERY OF THE UTILITY MODEL

The utility model provides a solid state hard drives to solve the too big problem of solid state hard drives size.

In order to solve the technical problem, the utility model provides a solid state hard drives, include: the packaging structure comprises a substrate, a packaging layer, a main control chip, a storage chip and a component; the main control chip, the storage chip and the components are attached to one side of the substrate and are electrically connected with the conducting circuit of the substrate; the packaging layer is arranged on one side of the substrate to package the main control chip, the storage chip and the component; 247 pins are arranged on the other side of the substrate, each pin is electrically connected with the conductive circuit of the substrate, and the 247 pins are located in a 21-row 16-column square matrix.

The solid state disk is at least 14 × 18 mm long and wide and at least 1.3 mm high.

The distance between the pins at least comprises 0.8 mm, and the diameter of each pin at least comprises 0.55 mm.

The outermost two circles of the pins are partially arranged in an array at intervals, the number of the pins is 80, the next two circles are arranged in a full array, the number of the pins is 100, and the center position of the pins is arranged in a ten-row six-column full array.

A blank band is arranged between the secondary outer two circles and the central part, a pin is further arranged between the central part and the secondary outer two circles, and the pin is positioned in the 5 th row and the 5 th column of the 5 th row; and a pin is arranged between the outermost circle pin of the rest of the central parts and the adjacent secondary circle.

Wherein, the outermost two circles and the secondary two circles are closely arranged, and the 2 nd row and the 20 th row are arranged in a full row; columns 3 and 14 are full columns; columns 2, 4, 6, 8, 9, 11, 13, and 15 of rows 1 and 21 are blank areas; the first row and the second row in the 1 st column and the 16 th column are closely arranged, the 20 th row and the 21 st row are closely arranged, and the other rows are arranged by one pin at intervals; the 2 nd column and the 15 th column are arranged at equal intervals and one pin interval.

The pins positioned in the 1 st row and the 1 st column in the square array are defined as GPIO power supplies of the main control chip; and four pins in the square array, which are positioned in the 8 th column in the 3 rd row, the 9 th column in the 3 rd row, the 8 th column in the 4 th row and the 9 th column in the 4 th row, are defined as a VCC power supply of the memory chip.

12 pins in the square array, which are located in the 6 th row, the 6 th column, the 6 th row, the 7 th column, the 6 th row, the 10 th column, the 6 th row, the 11 th column, the 7 th row, the 6 th column, the 7 th row, the 7 th column, the 7 th row, the 10 th column, the 7 th row, the 11 th column, the 8 th row, the 6 th column, the 8 th row, the 7 th column, the 8 th row, the 10 th column and the 8 th row, the 11 th column, are defined as a core power supply of the main control chip.

12 pins positioned in a row 14, a row 6, a row 14, a column 7, a row 14, a column 10 and a row 14, a column 11, a row 15, a column 6, a row 15, a column 7, a row 15, a column 10 and a column 11, a row 16, a column 6, a row 16, a column 7, a row 16, a column 10 and a column 11 are defined as a VCCQ power supply of the memory chip; and 4 pins in the square array, which are positioned in the 8 th column in the 18 th row and the 9 th column in the 18 th row, and the 8 th column in the 19 th row and the 9 th column in the 19 th row, are defined as a VCC power supply of the memory chip.

Two pin signals in the square array, which are located in a 5 th row, a 3 rd column and a 5 th row, a 4 th column, a 9 th row, a 3 rd column and a 9 th row, a 4 th column, a 13 th row, a 3 rd column and a 13 th row, a 4 th column, a 17 th row, a 3 rd column and a 17 th row, a 4 th column, are high-speed serial bus differential receiving signals; and

two pin signals of the square array, which are positioned in a 7 th row, a 3 rd column and a 7 th row, a 4 th column, a 11 th row, a 3 rd column and a 11 th row, a 4 th column, a 15 th row, a 3 rd column and a 15 th row, a 4 th column, or a 19 th row, a 3 rd column and a 19 th row, a 4 th column, are high-speed serial bus differential transmission signals.

The utility model has the advantages that; be different from prior art's condition, the utility model discloses a packaging layer encapsulates main control chip, memory chip and components and parts in one side of base plate to make its conducting wire electricity with the base plate be connected, and draw forth the pin from the opposite side of base plate, thereby encapsulate a plurality of devices on the base plate, thereby can reduce whole solid state hard disk's size, satisfy the miniaturized size requirement of solid state hard disk. In addition, in the embodiment, external electrical connection of the solid state disk is led out by arranging 247 pins and enabling the 247 pins to be located in 21 rows and 16 columns of square matrixes, and the pin arrangement can be applied to small-size solid state disks to ensure the function realization of the solid state disks.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of a solid state disk provided in the present invention;

fig. 2 is a schematic structural diagram of an embodiment of the pin arrangement of the present invention;

fig. 3 is a schematic diagram illustrating signal definition of each pin in the solid state disk 10.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

It should be noted that, if directional indications (such as upper, lower, left, right, front, and rear … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indication is changed accordingly.

In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a solid state disk provided in the present invention.

The solid state disk 10 of the present embodiment includes a substrate 12, a package layer 11, a main control chip 13, a memory chip 14, and a component 15. The number of the main control chip 13, the number of the memory chip 14, and the number of the components 15 may all include one or more, and the specific number may be set based on actual requirements, which is not limited herein.

The main control chip 13, the memory chip 14 and the component 15 are all attached to one side of the substrate 12 and electrically connected to the conductive circuit of the substrate 12, so that the main control chip 13, the memory chip 14 and the component 15 are electrically connected.

The substrate 12 may include a PCB (Printed Circuit Board) in which conductive traces are formed to implement the electrical functions thereof. The components 15 may include one or more of resistors, capacitors, inductors, potentiometers, electron tubes, heat sinks, electromechanical components, connectors, semiconductor discrete devices, electroacoustic devices, laser devices, electronic display devices, optoelectronic devices, sensors, power supplies, switches, micro-motors, electronic transformers, relays, and other electronic components, which are not limited herein. Memory chips 14 may include NAND FLASH memory chips or other types of memory chips, but are not limited thereto.

The encapsulation layer 11 is disposed on one side of the substrate 12 and wraps the main control chip 13, the memory chip 14 and the component 15 to encapsulate the main control chip 13, the memory chip 14 and the component 15.

The encapsulation layer 11 may include one or more of epoxies, polyimides, bismaleimide Triazine (BT), ceramics based. And is not limited thereto.

The other side of the substrate 12 is provided with 247 pins 16, each pin 16 is electrically connected to the conductive circuit of the substrate 12, and the 247 pins 16 are located in a 21-row 16-column square matrix, so that the electrical connection between each pin 16 and the main control chip 13, the memory chip 14 and the component 15 is realized through the substrate 12, the functions of the main control chip 13, the memory chip 14 and the component 15 are integrated onto the 247 pins 16 on the other side of the substrate 12, and the external electrical connection of the solid state disk 10 is realized through the pins 16.

Through the structure, the solid state disk of this embodiment passes through the encapsulation layer and encapsulates main control chip, memory chip and components and parts in one side of base plate to make its conducting wire electricity be connected with the base plate, and draw forth the pin from the opposite side of base plate, thereby encapsulate a plurality of devices on the base plate, thereby can reduce whole solid state disk's size, satisfy the miniaturized size requirement of solid state disk. In addition, in the embodiment, external electrical connection of the solid state disk is led out by arranging 247 pins and enabling the 247 pins to be located in 21 rows and 16 columns of square matrixes, and the pin arrangement can be applied to small-size solid state disks to ensure the function realization of the solid state disks.

In other embodiments, the solid state disk 10 has a length and a width of at least 14 × 18 mm and a height of at least 1.3 mm. That is, the length L of the solid state disk 10 includes at least 18 mm, specifically 18 mm, 20 mm, 30 mm, or 46 mm, etc., the width W of the solid state disk 10 includes at least 14 mm, specifically 14 mm, 15 mm, 26 mm, or 30 mm, etc., and the height H of the solid state disk 10 includes at least 1.3 mm, specifically 1.3 mm, 1.5 mm, or 2.0 mm, etc.

In a specific application scenario, when the length L of the solid state disk 10 is 18 mm, the width thereof is 14 mm, and the height H thereof is up to 1.3 mm, the actual error may be within ± 0.2 mm. The size of the solid state disk 10 within this parameter range can meet the miniaturization requirement.

In other embodiments, the spacing between the leads 16 at least includes 0.8 mm, which may specifically include: 0.8 mm, 0.9 mm, 1.0 mm, etc., and the diameter of each pin 16 at least includes 0.55 mm, and specifically may include 0.55 mm, 0.60 mm, 0.70 mm, etc., which is not limited herein.

In a specific application scenario, when the length L of the solid state disk 10 is 18 mm, the width is 14 mm, and the height H is up to 1.3 mm, the distance between the pins 16 is 0.8 mm, the diameter of each pin 16 is 0.55 mm, and the actual error may be within ± 0.1 mm.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the pin arrangement according to the present invention.

In other embodiments, the outermost two circles 22 of the leads 16 are partially spaced and arrayed, for a total of 80 leads 16, the second outer two circles 23 are fully arrayed, for a total of 100 leads 16, and the central portion 21 is fully arrayed according to a row-by-row six-column pattern.

Wherein, the interval arrangement of this embodiment refers to a pin setting between two pins at an interval, for example: the pins 16 in the first row and the first column are spaced from the pins 16 in the first row and the third column. And a full array arrangement means that the pins 16 are not spaced from each other by the pins 16. Such as a full array of pins 16 in the central portion 21.

In other embodiments, a blank band exists between the second two outer circles 23 and the central portion 21, and a pin 16 is further included between the central portion 21 and the second two outer circles 23, and the pin 16 is located in the 5 th row and the 5 th column of the 5 th row; the outermost turn of the remaining central portion 21 has a lead 16 spaced from the adjacent next outer turn by one lead 16.

In other embodiments, the outermost two turns 22 are closely spaced with the second two turns 23, and the 2 nd and 20 th rows are in a full row arrangement; columns 3 and 14 are full columns; columns 2, 4, 6, 8, 9, 11, 13, and 15 of rows 1 and 21 are blank areas; the first row and the second row in the 1 st column and the 16 th column are closely arranged, the 20 th row and the 21 st row are closely arranged, and the other rows are arranged by one pin 16; the 2 nd and 15 th columns are equally spaced and spaced by one pin 16.

The close arrangement in this embodiment means that the pins 16 are arranged in sequence according to the sequence of each row and each column, but the pins 16 still have a space therebetween. For example: the pins 16 in the first column and the pins 16 in the second column and the second row are closely arranged. And two pins 16 are arranged one pin 16 apart, the distance is also the distance of the pitch of two pins apart from the diameter distance of one pin 16, for example: the pins 16 in the first row and the first column and the pins 16 in the first row and the third column are spaced by the diameter distance of the pins 16 in the first row and the second column, and are also spaced by the distance between the pins 16 in the first row and the first column and the distance between the pins 16 in the first row and the second column and the pins 16 in the first row and the second column.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating signal definition of each pin in the solid state disk 10, and specific signal definition refers to the drawing.

Specifically, in other embodiments, the pin 16 located in the 1 st row and the 1 st column in the square matrix is defined as a GPIO power supply of the main control chip 13, i.e., G1V8; and four pins 16 in the square matrix located at row 3, column 8, row 3, column 9, row 4, column 8, and row 4, column 9 define the VCC power supply for the memory chip 14, i.e., PWR _1.

In other embodiments, 12 pins 16 in the square matrix located in the 6 th row, the 6 th column, the 6 th row, the 7 th column, the 6 th row, the 10 th column, the 6 th row, the 11 th column, the 7 th row, the 6 th column, the 7 th row, the 7 th column, the 7 th row, the 11 th column, the 8 th row, the 6 th column, the 8 th row, the 7 th column, the 8 th row, the 10 th column and the 8 th row, the 11 th column are defined as a core power supply of the main control chip 13, i.e., PER _3.

In other embodiments, 12 pins 16 in the square array located in the row 14, the column 6, the row 14, the column 7, the row 14, the column 10 and the row 14, the column 11, the row 15, the column 6, the row 15, the column 7, the row 15, the column 10 and the column 11, the row 16, the column 6, the row 16, the column 7, the row 16, the column 10 and the column 11 define a VCCQ power supply of the memory chip 14; and 4 pins 16 in the square matrix located in the 8 th column of the 18 th row, the 9 th column of the 18 th row, the 8 th column of the 19 th row, and the 9 th column of the 19 th row are defined as a VCC power supply of the memory chip 14, i.e., PER _2.

In other embodiments, the pins 16 signals in the square array at SATA-A +/PERP0 in row 5, column 3 and SATA-A-/PERN0 in row 5, column 4, or PERP1 in row 9, column 3 and PERN1 in row 9, column 4, or PERP2 in row 13, column 3 and PERN2 in row 13, column 4, or PERP3 in row 17, column 3 and PETN3 in row 17, column 4 are high speed serial bus differential receive signals; and the signals of the pins 16 of the SATA-B +/PETp0 positioned on the 7 th row and the 3 rd column and the SATA-B-/PETn 0 positioned on the 7 th row and the 4 th column in the 7 th row and the PETp1 positioned on the 11 th row and the 3 rd column and the PETn1 positioned on the 11 th row and the 4 th column, or the PETp2 positioned on the 15 th row and the 3 rd column and the PETn2 positioned on the 15 th row and the 4 th column in the 15 th row and the 4 th column, or the PETp3 positioned on the 19 th row and the 3 rd column and the PETn3 positioned on the 19 th row and the 4 th column in the square array are high-speed serial bus differential transmission signals.

Wherein, the definition of each pin is explained as the following table:

the above is only the embodiment of the present invention, not the limitation of the patent scope of the present invention, all the equivalent structures or equivalent processes that are used in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the patent protection scope of the present invention.

Claims (10)

1. A solid state disk, comprising: the packaging structure comprises a substrate, a packaging layer, a main control chip, a storage chip and a component;

the main control chip, the storage chip and the components are attached to one side of the substrate and are electrically connected with the conducting circuit of the substrate; the packaging layer is arranged on one side of the substrate to package the main control chip, the storage chip and the component;

247 pins are arranged on the other side of the substrate, each pin is electrically connected with the conductive circuit of the substrate, and the 247 pins are located in a 21-row 16-column square matrix.

2. Solid state disk according to claim 1,

the solid state disk at least comprises 14 × 18 mm in length and width and 1.3 mm in height.

3. The solid state disk of claim 1 or 2, wherein a spacing between the pins comprises at least 0.8 mm, and a diameter of the pins comprises at least 0.55 mm.

4. The solid state disk of claim 1, wherein the two outermost circles of the pins are arranged in a partially spaced array of 80 pins, the two next outermost circles are arranged in a full array of 100 pins, and the center portions are arranged in a full array of eleven rows and six columns.

5. The solid state disk of claim 4, wherein a blank strip exists between the second two outer turns and the central portion, and a pin is further included between the central portion and the second two outer turns, the pin being located in row 5 and column 5; and a pin is arranged between the outermost circle pin of the rest central parts and the adjacent secondary circle.

6. The solid state disk of claim 4, wherein the outermost two turns are closely arranged with the second two turns, and the 2 nd and 20 th rows are arranged in a full row; columns 3 and 14 are full columns; columns 2, 4, 6, 8, 9, 11, 13, and 15 of rows 1 and 21 are blank areas; the first row and the second row in the 1 st column and the 16 th column are closely arranged, the 20 th row and the 21 st row are closely arranged, and the other rows are arranged by one pin at intervals; the 2 nd and 15 th columns are arranged at equal intervals and one pin is arranged at intervals.

7. The solid state disk of claim 1, wherein a pin in the 1 st row and 1 st column in the square matrix is defined as a GPIO power supply of the main control chip; and

four pins in the square array, which are positioned in the 8 th column in the 3 rd row, the 9 th column in the 3 rd row, the 8 th column in the 4 th row and the 9 th column in the 4 th row, are defined as a VCC power supply of the memory chip.

8. The solid state disk of claim 1, wherein 12 pins in the matrix located in row 6, column 6, row 6, column 7, row 6, column 10, row 6, column 11, row 7, column 6, row 7, column 7, row 7, column 10, row 7, column 11, row 8, column 6, row 8, column 7, row 8, column 10, and column 8 define a core power supply of the master chip.

9. The solid state disk of claim 1, wherein 12 pins in the square matrix located in row 14, column 6, row 14, column 7, row 14, column 10, row 14, column 11, row 15, column 6, row 15, column 7, row 15, column 10, row 15, column 11, row 16, column 6, row 16, column 7, row 16, column 10, row 16, column 11 define a VCCQ power supply of the memory chip; and

4 pins in the square array, which are positioned in the 8 th column in the 18 th row and the 9 th column in the 18 th row, and the 8 th column in the 19 th row and the 9 th column in the 19 th row, are defined as a VCC power supply of the memory chip.

10. The solid state disk of claim 1, wherein two pin signals in the matrix at row 5, column 3 and column 5, row 9, column 3 and column 9, row 4, row 13, column 3 and column 13, or row 17, column 3 and column 17, column 4 are high-speed serial bus differential receiving signals; and

two pin signals of the square array, which are positioned on the 7 th row, the 3 rd column and the 7 th row, the 4 th column, the 11 th row, the 3 rd column and the 11 th row, the 4 th column, the 15 th row, the 3 rd column and the 15 th row, the 4 th column, or the 19 th row, the 3 rd column and the 19 th row, the 4 th column, are high-speed serial bus differential sending signals.

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