KR102560781B1 - Semiconductor module - Google Patents

Abstract

A semiconductor module according to the concept of the present invention is provided. According to embodiments, a semiconductor module includes a module substrate having a first side parallel to a first direction; tabs provided adjacent to the first side on the upper surface of the module substrate; a plurality of upper packages provided on the upper surface of the module substrate and forming rows arranged in the first direction; and passive elements provided on the upper surface of the module substrate. In a plan view, at least a portion of the passive element may overlap one of the upper packages. The upper packages of a second row may be shifted in the first direction from the upper packages of a first row.

Description

Semiconductor module {Semiconductor module}

The present invention relates to a semiconductor module, and more particularly, to a semiconductor module including memory packages.

BACKGROUND OF THE INVENTION [0002] Recently, demand for high-capacity products has increased in electronic devices such as mobile phones and laptop computers. To meet these demands, semiconductor modules used in electronic devices are required to have high capacities. As the high capacity of semiconductor modules is accelerated, the sizes of semiconductor packages are increasing. Due to this, the problem of increasing the size of the semiconductor module and increasing the signal length within the semiconductor module has been raised.

An object to be solved by the present invention is to provide a semiconductor module with improved operating speed and reliability.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor module according to the concept of the present invention includes a module substrate having a first side parallel to a first direction; a plurality of upper packages provided on an upper surface of the module substrate and forming rows arranged in the first direction; and passive elements provided on the upper surface of the module substrate. In a plan view, at least a portion of the passive element may overlap one of the upper packages. The upper packages of a second row may be shifted in the first direction from the upper packages of a first row.

A semiconductor module according to the concept of the present invention is a module substrate having a first side, a second side opposite to the first side, a third side adjacent to the first side, and a fourth side opposite to the third side. ; tabs provided on an upper surface of the module substrate and provided adjacent to the first side; a plurality of memory packages mounted on the upper surface of the module substrate and forming rows arranged in a first direction; and a passive element mounted on the upper surface of the module substrate. The first direction may be parallel to the first side of the module substrate. The memory packages may include first packages forming a first row when viewed from a plan view; and second packages that form a second row and are more adjacent to the tabs than the first packages. A minimum distance between the first packages and the third side may be smaller than a minimum distance between the second packages and the third side. A minimum distance between the first packages and the fourth side may be smaller than a minimum distance between the second packages and the fourth side.

A semiconductor module according to the concept of the present invention includes a module substrate having a first side and a second side parallel to a first direction; tabs provided adjacent to the first side on an upper surface of the module substrate; a plurality of memory packages mounted on the upper surface of the module substrate and forming rows, each of the rows parallel to the first direction; and a passive element mounted on the upper surface of the module substrate. At least a portion of the passive element may overlap one of the memory packages in a plan view. The memory packages may include: first packages forming a first row in a plan view; and second packages that form a second row and are more adjacent to the tabs than the first packages. Each of the first packages may have a long axis parallel to the second direction, each of the second packages may have a long axis parallel to the first direction, and the second direction may be perpendicular to the first direction.

According to the present invention, at least a part of the passive element may overlap any one of the upper packages in plan view. The arrangement of the top packages can be adjusted so that the length of the signal path between the tabs and the top packages can be reduced. Operation speed and reliability of the semiconductor module may be improved. Also, the semiconductor module may have a high capacity.

1A is a plan view illustrating a top surface of a semiconductor module according to example embodiments.
FIG. 1B is a diagram for explaining electrical connections between upper tabs and upper packages of the semiconductor module of FIG. 1A .
Figure 1c is a cross-sectional view taken along the line Ⅰ-Ⅰ' of Figure 1a.
FIG. 1D is an enlarged view of region II of FIG. 1A.
FIG. 1E is a cross-section taken along the line III-III′ of FIG. 1D.
FIG. 1F is a cross-section taken along line IV-IV' in FIG. 1D.
FIG. 1G is a plan view illustrating a lower surface of the semiconductor module of FIG. 1A.
1H is a diagram for explaining electrical connections between lower tabs and lower packages.
1I is a diagram showing a side surface of one of upper packages and a first passive element.
2 is a diagram for explaining mounting of a second passive element according to embodiments.
3A is a cross-sectional view illustrating a semiconductor module according to example embodiments.
3B is a cross-sectional view illustrating a semiconductor module according to example embodiments.

In this specification, like reference numerals may refer to like elements throughout. Hereinafter, a semiconductor module according to the concept of the present invention will be described.

1A is a plan view illustrating a top surface of a semiconductor module according to example embodiments. FIG. 1B is a diagram for explaining electrical connections between upper tabs and upper packages of the semiconductor module of FIG. 1A . Figure 1c is a cross-sectional view taken along the line Ⅰ-Ⅰ' of Figure 1a. FIG. 1D is an enlarged view of region II of FIG. 1A. FIG. 1E is a cross-section taken along the line III-III′ of FIG. 1D. FIG. 1F is a cross-section taken along line IV-IV' in FIG. 1D. FIG. 1G is a plan view illustrating a lower surface of the semiconductor module of FIG. 1A. 1H is a diagram for explaining electrical connections between lower tabs and lower packages.

1A to 1G , the semiconductor module 1 includes a module substrate 100, upper tabs 210, 220, and 230, a semiconductor package 310, a semiconductor device 320, upper packages 400, It may include a passive element 600 , lower tabs 211 , 221 , and 231 , and lower packages 401 .

The module substrate 100 may be a printed circuit board (PCB) having a circuit pattern. The module substrate 100 may have an upper surface 100a and a lower surface 100b facing each other. The module substrate 100 may have a first side 101 , a second side 102 , a third side 103 , and a fourth side 104 . The second side 102 of the module substrate 100 may be opposite to the first side 101 . The first side 101 and the second side 102 of the module substrate 100 may be parallel to the first direction D1. Here, the first direction D1 may be parallel to the upper surface 100a of the module substrate 100 . The second direction D2 may be parallel to the top surface 100a of the module substrate 100 and substantially perpendicular to the first direction D1 . The third direction D3 may be parallel to the top surface 100a of the module substrate 100 and may be opposite to the first direction D1 . Vertical in this specification may include an error range that may occur in a process. The third side 103 of the module substrate 100 may be adjacent to the first side 101 and the second side 102 . The third side 103 and the fourth side 104 of the module substrate 100 may face each other. The third side 103 and the fourth side 104 of the module substrate 100 may be parallel to the second direction D2 .

Top tabs 210 , 220 , 230 may be provided on the top surface 100a of the module substrate 100 . The top tabs 210 , 220 , and 230 may be provided adjacent to the first side 101 of the module substrate 100 . The upper tabs 210 , 220 , and 230 may be aligned along the first direction D1 to form a row parallel to the first direction D1 . Each of the upper tabs 210 , 220 , and 230 may have a long axis parallel to the second direction D2 when viewed in plan view. The upper tabs 210, 220, and 230 may include metal, such as copper or aluminum. As shown in FIG. 1C , the upper tabs 210 , 220 , and 230 may be part of the conductive pattern of the module substrate 100 exposed by the passivation layer 109 , but are not limited thereto.

The upper tabs 210 , 220 , and 230 may include first upper tabs 210 , second upper tabs 220 , and third upper tabs 230 . Functions and arrangements of the upper tabs 210, 220, and 230 may be standardized. For example, the function and arrangement of the upper tabs 210, 220 and 230 may satisfy the JEDEC standard. The first top tabs 210 may be closer to the third side 103 of the module substrate 100 than the second and third top tabs 220 and 230 . The second upper tabs 220 may be closer to the fourth side 104 of the module substrate 100 than the third upper tab 230 . The first and second upper taps 210 and 220 may function as input/output terminals of data signals. The third upper tab 230 may be provided between the first upper tabs 210 and the second upper tabs 220 when viewed from a plan view. The third upper tap 230 may function as a transmission path for a command/address (C/A) signal.

The semiconductor package 310 may be mounted on the upper surface 100a of the module substrate 100 . The semiconductor package 310 may be disposed in the center region of the upper surface 100a of the module substrate 100 when viewed in plan view. The semiconductor package 310 may function as a logic package or a buffer package. As shown in FIG. 1C , the semiconductor package 310 may include a first package substrate 311 , a first semiconductor chip 312 , and a first molding pattern 313 . For example, a printed circuit board (PCB) or a redistribution layer may be used as the first package substrate 311 . The first semiconductor chip 312 may be mounted on the first package substrate 311 . The first semiconductor chip 312 includes logic circuits and may function as at least one of a logic chip and a buffer chip. A first molding pattern 313 may be provided on the first package substrate 311 to seal the first semiconductor chip 312 . The connection terminal 500 may be interposed between the module substrate 100 and the first package substrate 311 to connect to the module substrate 100 and the semiconductor package 310 . The connection terminal 500 may include at least one of a pillar, a bump, and a solder ball. The connection terminal 500 may include a conductive material. The first semiconductor chip 312 may be electrically connected to the wirings 150 in the module substrate 100 through the first package substrate 311 and the connection terminal 500 . The wires 150 may include conductive patterns and vias.

The semiconductor package 310 may be electrically connected to the third upper tab 230 through the wires 150 in the module substrate 100 . Accordingly, a command/address signal may be transmitted and received between the third upper tap 230 and the first semiconductor chip 312 . The semiconductor package 310 may be electrically connected to the upper packages 400 and the lower packages 401 through the wires 150 in the module substrate 100 . The semiconductor package 310 may control the upper packages 400 and the lower packages 401 . In this specification, being electrically connected to the module substrate 100 may mean being electrically connected to the wires 150 in the module substrate 100 . The wirings 150 of FIG. 1C are schematically shown, and the arrangement and shape of the wirings 150 may be modified in various ways. Although the wirings 150 are omitted for simplicity in the drawings except for FIG. 1C, the present invention is not limited thereto.

The semiconductor device 320 may be mounted on the upper surface 100a of the module substrate 100 . The semiconductor device 320 may be spaced apart from the semiconductor package 310 in a plan view. The semiconductor device 320 may include a serial presence detect (SPD) chip. For example, information of the semiconductor module 1 may be stored in the SPD chip of the semiconductor device 320 . Here, the information of the semiconductor module 1 may include which memories are present in the semiconductor module 1 and when to use timing to access the memories. An SPD chip may be used as the semiconductor device 320 . In this case, the SPD chip may be directly mounted on the upper surface 100a of the module substrate 100 to form the semiconductor element 320 . As another example, a semiconductor package 310 including an SPD chip may be used as the semiconductor device 320 . In this case, the semiconductor device 320 may include a second package substrate, an SPD chip mounted on the second package substrate, and a second molding pattern covering the SPD chip on the second package substrate. The semiconductor device 320 may be electrically connected to the semiconductor package 310 through the module substrate 100 .

Upper packages 400 may be mounted on the upper surface 100a of the module substrate 100 . The upper packages 400 may be spaced apart from the semiconductor package 310 , the semiconductor device 320 , and the upper tabs 210 , 220 , and 230 . The upper packages 400 may be spaced apart from each other. Each of the upper packages 400 may be memory packages. The upper packages 400 may be identical to each other. For example, the top packages 400 may have the same plane, shape, and storage capacity. Each of the upper packages 400 may include an upper substrate 470 , an upper semiconductor chip 480 , and an upper molding layer 490 as shown in FIG. 1C . The upper semiconductor chip 480 may be a memory chip. For example, the upper semiconductor chip 480 may include DRAM. As another example, the upper semiconductor chip 480 may include SRAM, SDRAM, or MRAM. The upper semiconductor chip 480 may be mounted on the upper substrate 470 . The upper molding layer 490 is provided on the upper substrate 470 and may cover the upper semiconductor chip 480 . An upper connection terminal 501 may be provided between the module substrate 100 and the upper packages 400 . The upper connection terminal 501 may include at least one of a pillar, a bump, and a solder ball. The upper packages 400 may be electrically connected to the module substrate 100 through upper connection terminals 501 .

As shown in FIGS. 1A and 1B , upper packages 400 may be arranged along a plurality of rows X1 and X2 . Each of the rows X1 and X2 may be parallel to the first direction D1. Each of the rows X1 and X2 may include a plurality of packages. 1B, a solid line between the upper connection terminal 501 and the first and second upper tabs 210 and 220 indicates the electrical connection between the upper packages 400 and the first and second upper tabs 210 and 220. represents schematically. The upper packages 400 may transmit and receive signals to and from external devices through the module substrate 100 and the first and second upper tabs 210 and 220 . Signals between the upper packages 400 and the first upper taps 210 and between the upper packages 400 and the second upper taps 220 may be data DQ signals. As the lengths of the signal paths between the upper packages 400 and the first upper tabs 210 and between the upper packages 400 and the second upper tabs 220 decrease, the reliability and operation speed of the semiconductor module 1 increase. can be improved Also, high-capacity memory packages may be used as the upper packages 400 .

According to embodiments, the upper packages 400 may be shifted in the second direction D2. For example, the minimum spacing A10 between the top packages 400 and the top tabs 210, 220, 230 is the minimum distance A10 between the top packages 400 and the second side 102 of the module substrate 100. It may be shorter than the interval A20. Accordingly, lengths of signal paths between the upper packages 400 and the first upper tabs 210 and between the upper packages 400 and the second upper tabs 220 may be reduced.

The upper packages 400 may include first packages 410 and second packages 420 . The first packages 410 may be upper packages 400 of the first row X1 . The second packages 420 may be upper packages 400 of the second row X2 . The second packages 420 may be closer to the first side 101 of the module substrate 100 and the upper tabs 210 , 220 , and 230 than the first packages 410 . The total number of second packages 420 may be the same as the total number of first packages 410, but is not limited thereto. Each of the second packages 420 may have a long axis parallel to the first direction D1 . For example, the width W of each of the second packages 420 may be greater than the length L. Accordingly, lengths of signal paths between the second packages 420 and the first and second upper tabs 210 and 220 may be further reduced. In the present specification, the width of a certain element may mean the distance of the element in the first direction D1, and the length may mean the distance of the element in the second direction D2.

Some of the upper packages 400 may form a first group G10. Other parts of the upper packages 400 may form the second group G20. The upper packages 400 of the first group G10 may be provided between the semiconductor package 310 and the third side 103 of the module substrate 100 in a plan view. As shown in FIG. 1B , the upper packages 400 of the first group G10 may be electrically connected to the first upper tabs 210 through the module substrate 100 . The upper packages 400 of the first group G10 may not be electrically connected to the second upper tabs 220 and the third upper tab 230 . In the top package 400 of the first group G10, the one closest to the fourth side 104 of the module substrate 100 among the first packages 410 and the first one among the first top tabs 210 The length of the signal path S10 between the package 410 and the connection may correspond to the maximum signal path length. According to embodiments, in the upper package 400 of the first group G10 , the first packages 410 may be shifted from the second packages 420 in the first direction D1 . For example, the minimum distance B10 between the first packages 410 and the third side 103 of the module substrate 100 is the second packages 420 and the third side of the module substrate 100 ( 103) may be shorter than the minimum interval B20. In the upper package 400 of the first group G10 , the number of first packages 410 may be the same as the number of second packages 420 . In the upper package 400 of the first group G10, the maximum distance between the first packages 410 and the third side 103 of the module substrate 100 is the second packages 420 and the module substrate ( 100) may be shorter than the maximum distance between the third sides 103. A signal path (S10) between one of the first packages 410 closest to the fourth side 104 of the module substrate 100 and the first upper tab 210 connected to the first package 410 length may be reduced. Accordingly, a maximum signal path length between the upper packages 400 of the first group G10 and the first upper tabs 210 may be reduced.

The upper packages 400 of the second group G20 may be provided between the semiconductor package 310 and the second side 102 of the module substrate 100 in a plan view. The upper packages 400 of the second group G20 may be electrically connected to the second upper tabs 220 through the module substrate 100 . The upper packages 400 of the second group G20 may not be electrically connected to the first upper tabs 210 and the third upper tabs 230 . In the upper package 400 of the second group G20, the one nearest to the third side 103 of the module substrate 100 among the first packages 410 and the first one among the second upper tabs 220 The length of the signal path S20 between the package 410 and the connection may correspond to the maximum signal path length. According to embodiments, in the upper package 400 of the second group G20 , the first packages 410 may be shifted from the second packages 420 in the third direction D3 . For example, the minimum distance C10 between the first packages 410 of the second group G20 and the fourth side 104 of the module substrate 100 is the distance between the second packages 420 and the module substrate ( It may be shorter than the minimum distance C20 between the fourth sides 104 of 100. In the upper package 400 of the second group G20 , the number of first packages 410 may be the same as the number of second packages 420 . In the upper package 400 of the second group G20, the maximum distance between the first packages 410 and the fourth side 104 of the module substrate 100 is the second packages 420 and the module substrate ( 100) may be shorter than the maximum spacing between the fourth sides 104. Accordingly, the maximum signal path length between the upper packages 400 of the second group G20 and the second upper tabs 220 may be reduced.

The module substrate 100 may have a first region R1 , second regions R2 , and third regions R3 in a plan view as shown in FIG. 1A . The first region R1 of the module substrate 100 may be provided between the first packages 410 and the first to third upper tabs 210 , 220 , and 230 . The second regions R2 of the module substrate 100 may be provided between the first packages 410 and the second packages 420 . Any one of the third regions R3 of the module substrate 100 is between the outermost first package 410 and the third side 103 of the module substrate 100 and between the outermost second package 420 and the module. It may be provided between the third side 103 of the substrate 100 . Another one of the third regions R3 of the module substrate 100 is between the outermost first package 410 and the fourth side 104 of the module substrate 100 and between the outermost second package 420 and the module. It may be provided between the fourth side 104 of the substrate 100 .

The passive element 600 may be mounted on the upper surface 100a of the module substrate 100 . The passive element 600 may include at least one of a resistor, a capacitor, and an inductor. At least one of the passive elements 600 may overlap any one of the upper packages 400 in plan view. The passive element 600 may include a first passive element 610 , a second passive element 620 , and a third passive element 630 . Hereinafter, the arrangement relationship of the passive element 600 and the upper packages 400 will be described. In the description of FIGS. 1D, 1E, and 1F, a single upper package is described for simplicity of description.

As shown in FIGS. 1A, 1D, and 1E , the first passive element 610 may include a first part 610A and a second part 610B connected to each other. The first portion 610A of the first passive element 610 may overlap one of the upper packages 400 in a plan view. The second portion 610B of the first passive element 610 may not overlap the upper package 400 . The second portion 610B of the first passive element 610 may overlap the first region R1 of the module substrate 100 in a plan view. As another example, the second portion 610B of the first passive element 610 may overlap the second region R2 of the module substrate 100 in a plan view, as shown in FIG. 1A . Alternatively, the second portion 610B of the first passive element 610 may overlap the third region R3 in a plan view. As shown in FIGS. 1D and 1F , the second passive element 620 may completely overlap the upper package 400 in plan view. According to embodiments, as the upper packages 400 overlap the first and second passive elements 610 and 620 in plan view, the semiconductor module 1 may be miniaturized.

According to embodiments, as the upper packages 400 are overlapped with the first and second passive elements 610 and 620 in a plan view, the upper packages 400 are the first and second passive elements. 610 and 620 can be arranged more freely without being constrained to the arrangement. For example, as the upper package 400 overlaps the first and second passive elements 610 and 620 , the upper package 400 may be more shifted in the second direction D2 . In this case, the second part 610B of the first passive element 610 may overlap the first region R1 or the second region R2 in plan view. As the top package 400 overlaps the first and second passive elements 610 and 620, in the top package 400 of the first group G10, the first packages 410 are the second packages. It may be further shifted in the first direction D1 from 420 . In the upper package 400 of the second group G20 , the first packages 410 may be further shifted from the second packages 420 in the third direction D3 . In this case, the second part 610B of the first passive element 610 may overlap the third regions R3 in a plan view. Accordingly, a length of a signal path between the upper packages 400 and the first and second upper tabs 210 and 220 may be reduced, thereby improving electrical characteristics of the semiconductor module 1 .

The first passive element 610 and the second passive element 620 may be provided in the gap between the module substrate 100 and the upper package 400 as shown in FIGS. 1E and 1F. The upper surface of the first passive element 610 and the upper surface of the second passive element 620 may be provided at a level lower than or equal to the lower surface of the upper package 400 . The first and second passive elements 610 and 620 may be spaced apart from the upper connection terminal 501 . Accordingly, an electrical short between the first and second passive elements 610 and 620 and the upper connection terminal 501 may be prevented.

According to embodiments, an external force may be applied on the top package 400 . The external force may be applied during a manufacturing process of the semiconductor module 1 , a transfer process of the semiconductor module 1 , or an operation process of the semiconductor module 1 . An edge portion of the upper package 400 may be bent by the external force. If the warpage is excessive, the upper package 400 may be damaged. According to embodiments, the first passive element 610 or the second passive element 620 may overlap an edge portion of the upper package 400 in a plan view. For example, the first passive element 610 may be provided between the lower surface of the edge portion of the upper package 400 and the upper surface 100a of the module substrate 100 . Accordingly, excessive bending of the semiconductor package 310 may be prevented.

The first pad 151 and the second pad 152 may be provided on the upper surface 100a of the module substrate 100 . The first pad 151 and the second pad 152 may include a conductive material such as metal. According to embodiments, each of the first passive element 610 and the second passive element 620 may include a first electrode 601 and a second electrode 602 spaced apart from each other. The second electrode 602 may be electrically separated from the first electrode 601 . An insulator 603 may be provided between the first electrode 601 and the second electrode 602 . However, the structure and components of the passive element 600 are not limited to those shown and may be variously modified. A first connection part 510 may be provided between the first electrode 601 and the first pad 151 . The first electrode 601 may be electrically connected to the module substrate 100 through the first connection part 510 . A second connection portion 520 may be provided between the second pad 152 and the second electrode 602 . The second electrode 602 may be electrically connected to the module substrate 100 through the second connection part 520 .

Each of the first connection part 510 , the second connection part 520 , and the upper connection terminal 501 may include a solder material. The solder material may include at least one of tin, silver, gold, and bismuth. According to example embodiments, forming the first connection portion 510 may include providing a solder material between the first pad 151 and the first electrode 601 and soldering the solder material. Forming the second connection portion 520 may include providing a solder material between the second pad 152 and the second electrode 602 and soldering the solder material. Formation of the upper connection terminal 501 may include providing a solder material between the module substrate 100 and the upper package 400 and soldering the solder material. Soldering for forming the first connection part 510 , the second connection part 520 , and the upper connection terminal 501 may be formed by a single process. The soldering process may be performed by heat treatment. At this time, the first electrode 601 or the second electrode 602 may be excessively spaced from the module substrate 100 due to the tension between the solder material and the electrodes 501 and 502 in the soldering process. In this case, it may be difficult to form the first connection part 510 or the second connection part 520 .

According to embodiments, the lower surface of the upper package 400 may be provided on the first passive element 610 . In the process of mounting the first passive element 610, the upper package 400 prevents the first electrode 601 or the second electrode 602 of the first passive element 610 from being excessively spaced from the module substrate 100. It can be prevented. Accordingly, the first connection part 510 and the second connection part 520 can be connected to the first electrode 601 and the second electrode 602 satisfactorily, respectively. Similarly, as the upper package 400 is provided on the upper surface of the second passive element 620, the first electrode 601 and the second electrode 602 of the second passive element 620 are formed on the module substrate 100. can be prevented from being excessively separated from

Referring back to FIG. 1A , the third passive element 630 may be spaced apart from the upper packages 400 without overlapping with the upper packages 400 . The third passive element 630 may be provided on any one of the first region R1 , the second regions R2 , and the third regions R3 of the module substrate 100 . Alternatively, the third passive element 630 may be provided between the first packages 410 in a plan view. As another example, the third passive element 630 may not be provided. As another example, any one of the first passive element 610 and the second passive element 620 may be omitted.

Lower tabs 211, 221, and 231 may be provided on the lower surface 100b of the module substrate 100 as shown in FIGS. 1G and 1H. The lower tabs 211 , 221 , and 231 may be part of the conductive pattern of the module substrate 100 exposed by the passivation layer 109 as shown in FIG. 1C , but are not limited thereto. The lower tabs 211, 221, and 231 may include metal. A planar arrangement of the lower tabs 211 , 221 , and 231 may correspond to a planar arrangement of the upper taps 210 , 220 , and 230 . For example, the lower tabs 211 , 221 , and 231 may be adjacent to the first side 101 of the module substrate 100 . The lower tabs 211, 221, and 231 are spaced apart from each other and may be electrically isolated. The lower tabs 211 , 221 , and 231 may include first lower tabs 211 , second lower tabs 221 , and third lower tabs 231 . The first lower tabs 211 may be closer to the third side 103 of the module substrate 100 than the second lower tabs 221 and the third lower tabs 231 . The second lower tabs 221 may be closer to the fourth side 104 of the module substrate 100 than the third lower tabs 231 . The first and second lower taps 211 and 221 may function as input/output terminals of data signals of the lower packages 401 . The third lower tab 231 may be provided between the first lower tabs 211 and the second lower tabs 221 . The third lower tap 231 may function as a transmission path of a command/address signal.

Each of the lower packages 401 may be a memory package. The lower packages 401 may have the same size, shape, and storage capacity as each other. The lower packages 401 may have the same size, shape, and storage capacity as the upper packages 400 . Each of the lower packages 401 may include a lower substrate 471 , a lower semiconductor chip 481 , and a lower molding layer 491 as shown in FIG. 1C . The lower semiconductor chip 481 may be a memory chip. The lower semiconductor chip 481 may be mounted on the lower substrate 471 . The lower semiconductor chip 481 may be the same type as the upper semiconductor chip 480, but is not limited thereto. The lower molding layer 491 is provided on the lower substrate 471 and may cover the lower semiconductor chip 481 . A lower connection terminal 502 may be provided between the module substrate 100 and the lower packages 401 . The lower packages 401 may be electrically connected to the module substrate 100 through lower connection terminals 502 .

The lower packages 401 may be spaced apart from the lower tabs 211 , 221 , and 231 . A planar arrangement of the lower packages 401 may correspond to a planar arrangement of the upper packages 400 . For example, as shown in FIGS. 1G and 1H , the lower packages 401 may be arranged along a plurality of rows X1' and X2'. Each of the rows X1' and X2' may be parallel to the first direction D1. Each of the rows X1' and X2' may include a plurality of lower packages 401. The number of lower packages 401 in the second row X2' may be the same as the number of lower packages 401 in the first row X1'. The lower packages 401 may transmit and receive signals to and from external devices through the first lower tabs 211 or the second lower tabs 221 . As the lengths of the signal paths between the lower packages 401 and the first lower tabs 211 and between the lower packages 401 and the second lower tabs 212 decrease, the reliability and operating speed of the semiconductor module 1 decrease. can be improved. In this case, signals between the lower packages 401 and the first lower taps 211 may be data DQ signals. According to embodiments, the lower packages 401 may be shifted in the second direction D2. For example, the minimum distance A11 between the lower packages 401 and the lower tabs 211 , 221 , and 231 is the minimum distance between the lower packages 401 and the fourth side 104 of the module substrate 100 . It may be shorter than the interval A21. Accordingly, lengths of signal paths between the lower packages 401 and the lower tabs 211 , 221 , and 231 may be reduced.

The lower packages 401 of the second row X2' may be more adjacent to the lower tabs 211, 221, and 231 than the lower packages 401 of the first row X1'. Each of the lower packages 401 in the second row (X2') may have a long axis parallel to the first direction (D1). For example, the width of each of the lower packages 401 in the second row (X2') may be greater than the length. Accordingly, the lower packages 401 may be disposed more adjacent to the lower tabs 211 , 221 , and 231 . Lengths of signal paths between the lower packages 401 and the first and second lower tabs 211 and 221 may be reduced. Each of the lower packages 401 in the first row (X1') may have a long axis parallel to the second direction (D2).

Some of the lower packages 401 may form the first group G11. Other parts of the lower packages 401 may form the second group G21. The lower packages 401 of the first group G11 may be disposed closer to the third side 103 than the fourth side 104 of the module substrate 100 in a plan view. In FIG. 1H , solid lines between the lower connection terminal 502 and the first and second lower tabs 211 and 221 represent electrical connections between the lower packages 401 and the first and second lower tabs 211 and 221 . represented schematically. The lower packages 401 of the first group G11 may be electrically connected to the first lower tabs 211 through the module substrate 100 . The lower packages 401 of the first group G11 may not be electrically connected to the second lower tabs 221 and the third lower tabs 231 . Among the bottom packages 401 of the first group G11, the one closest to the fourth side 104 of the module substrate 100 and the first bottom tabs among the bottom packages 401 of the first row X1' The length of the signal passage S11 between the parts 211 connected to the lower package 401 may correspond to the maximum signal passage length. According to embodiments, in the lower packages 401 of the first group G11, the lower packages 401 of the first row X1' are different from the lower packages 401 of the second row X2'. It may be shifted in one direction (D1). For example, the minimum distance B11 between the lower packages 401 of the first row (X1') and the third side 103 of the module substrate 100 is the lower packages 401 of the second row (X2'). ) and the minimum distance B21 between the third side 103 of the module substrate 100. In the lower packages 401 of the first group G11, the number of lower packages 401 in the first row X1' may be the same as the number of lower packages 401 in the second row X2'. there is. In the lower packages 401 of the first group G11, the maximum distance between the lower packages 401 of the first row X1' and the third side 103 of the module substrate 100 is the second row X2 ') and the third side 103 of the module substrate 100 may be shorter than the maximum distance. Accordingly, a maximum signal path length between the lower packages 401 of the first group G11 and the first lower tabs 211 may be reduced.

The lower packages 401 of the second group G21 may be disposed closer to the fourth side 104 than the third side 103 of the module substrate 100 in a plan view. The lower packages 401 of the second group G21 may be electrically connected to the second lower tabs 221 through the module substrate 100 . The lower packages 401 of the second group G21 may not be electrically connected to the first lower tabs 211 and the third lower tabs 231 . Among the bottom packages 401 of the second group G21, the one most adjacent to the third side 103 of the module substrate 100 and the second bottom tabs among the bottom packages 401 of the first row X1' The length of the signal path S21 between the parts 221 connected to the lower package 401 may correspond to the maximum signal path. According to embodiments, in the lower packages 401 of the second group G21, the lower packages 401 of the first row X1' are different from the lower packages 401 of the second row X2'. It may be shifted in three directions (D3). For example, the minimum distance C11 between the lower packages 401 of the first row (X1') and the fourth side 104 of the module substrate 100 is the lower packages 401 of the second row (X2'). ) and the minimum distance C21 between the fourth side 104 of the module substrate 100. Accordingly, a maximum signal path length between the lower packages 401 of the second group G21 and the second lower tabs 221 may be reduced.

The semiconductor package 310 , the semiconductor device 320 , and the passive device 600 may not be provided on the lower surface 100b of the module substrate 100 .

According to embodiments, the sum of the total number of upper packages 400 and lower packages 401 may be 2n+A. Here, n is a natural number greater than or equal to 1, and A may be an integer greater than or equal to 0. Some of the upper packages 400 and lower packages 401 may function as memory packages. The total number of upper packages 400 and lower packages 401 serving as the memory packages may be 2n. Other parts of the upper packages 400 and lower packages 401 may function as spare memory packages provided in case the memory packages do not operate. For example, when the memory packages are in an active state, spare memory packages may be in an inactive state. The total number of the spare memory packages may be A. However, the number and function of the upper and lower memory packages 400 and 401 are not limited thereto and may be variously modified.

1I is a diagram showing a side surface of one of upper packages and a first passive element. In the following description, a singular upper package is described for simplicity of description. Contents overlapping with those described above are omitted.

Referring to FIGS. 1E and 1I , an upper package 400 may include an upper substrate 470 , an upper semiconductor chip 480 , and an upper molding layer 490 . The upper substrate 470 may include an insulating layer and metal patterns 475 . Metal patterns 475 are provided in the insulating layer and may function as electrical connection passages. Portions of the metal patterns 475 may be exposed on the side surface of the upper substrate 470 . A side surface of the upper substrate 470 may correspond to a lower portion of the side surface 400s of the upper package 400 . The upper semiconductor chip 480 may be sealed by the upper molding layer 490 and may not be exposed to the side surface 400s of the upper package 400 . A side surface of the upper molding layer 490 may correspond to an upper portion of the side surface 400s of the upper package 400 . The upper molding layer 490 may include an insulating polymer.

As described above, a portion of the first passive element 610 may overlap the upper package 400 . Although not shown, the first passive element 610 may overlap the side surface 400s of the upper package 400 in a plan view. The first passive element 610 may be provided between the module substrate 100 and the upper substrate 470 . The first passive element 610 may be spaced apart from the exposed portions of the metal patterns 475 by a predetermined interval. For example, exposed surfaces of the metal patterns 475 may not overlap the first passive element 610 in a plan view. Accordingly, even if a minor error occurs during the manufacturing process of the semiconductor module 1, an electrical short between the exposed portions of the first passive element 610 and the metal patterns 475 can be prevented. . For example, either one of the electrodes 601 and 602 or one of the connectors 510 and 520 of the first passive element 610 may not contact the exposed surfaces of the metal patterns 475. .

FIG. 2 is a view for explaining mounting of a second passive element according to embodiments, and corresponds to a cross section taken along line III-III' in FIG. 1C. In the following description, a singular upper package is described for simplicity of explanation. Contents overlapping with those described above are omitted.

Referring to FIGS. 1A, 1C, and 2 , the second passive element 620 may overlap the upper package 400 in plan view. However, unlike FIG. 1F , the second passive element 620 may be mounted on the lower surface of the upper package 400 .

The conductive pad 473 , the first pad 151 , and the second pad 152 may be provided on the lower surface of the upper package 400 . The conductive pad 473 , the first pad 151 , and the second pad 152 may include a conductive material such as metal. The conductive pad 473 may be connected to the upper connection terminal 501 .

The first pad 151 and the second pad 152 may be spaced apart from the conductive pad 473 . A first connection part 510 may be provided between the first pad 151 and the first electrode 601 of the second passive element 620 . The second connection part 520 may be provided between the second pad 152 and the second electrode 602 . The second passive element 620 may be electrically connected to the upper package 400 through the first connection part 510 and the second connection part 520 . The second passive element 620 may be spaced apart from the upper surface 100a of the module substrate 100 .

FIG. 3A is a cross-sectional view of a semiconductor module according to example embodiments, and corresponds to a cross-section taken along line III-III′ of FIG. 1C. FIG. 3B is a cross-sectional view of a semiconductor module according to example embodiments, and corresponds to a cross-section taken along line IV-IV' in FIG. In the following description, a singular upper package is described for simplicity of description. Contents overlapping with those described above are omitted.

Referring to FIGS. 1A , 1C , and 3A , a first support 710 may be provided between the first passive element 610 and the upper package 400 . The first support part 710 may physically contact the first passive element 610 and the upper package 400 . The first support part 710 includes an insulating material and may not be electrically connected to the first passive element 610 and the upper package 400 . Warping of the upper package 400 may be prevented by the first passive element 610 and the first support part 710 .

Referring to FIGS. 1A , 1C , and 3B , a second support 720 may be provided between the second passive element 620 and the upper package 400 . The second support part 720 may physically contact the second passive element 620 and the upper package 400 . The second support part 720 includes an insulating material and may not be electrically connected to the second passive element 620 and the upper package 400 . Warping of the upper package 400 may be prevented by the second passive element 620 and the second support part 720 .

The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments, and can be used in various other combinations, modifications, and environments without departing from the gist of the invention. The appended claims should be construed to cover other embodiments as well.

Claims (21)

a module substrate having a first side parallel to a first direction and a second side opposite to the first side;
a plurality of upper packages provided on an upper surface of the module substrate and arranged along rows parallel to the first direction; and
Including a first passive element, a second passive element, and a third passive element provided on the upper surface of the module substrate,
The upper packages of a first row are shifted relative to the upper packages of a second row and are arranged in the first direction;
The module substrate is:
a first region provided between the first side of the module substrate and the upper packages of the second row in plan view;
a second area provided between the top packages of the first row and the top packages of the second row; and
a third region provided between a third side of the module substrate and the outermost upper package in the first row and between the third side and the outermost upper package in the second row;
The first passive element is:
a first portion provided between the upper surface of the module substrate and a lower surface of a first upper package which is one of the upper packages of the second row; and
a second portion provided in the first region of the module substrate and not provided between the upper surface of the module substrate and the lower surface of the first upper package;
The second passive element is:
a first portion provided between the upper surface of the module substrate and a lower surface of a second upper package which is one of the upper packages of the first row; and
a second portion provided in the second region of the module substrate and not provided between the upper surface of the module substrate and the lower surface of the second upper package;
The third passive element is:
a first portion provided between the upper surface of the module substrate and the lower surface of the outermost upper package in the first row; and
and a second portion provided in the third region of the module substrate and not provided between the upper surface of the module substrate and the lower surface of the outermost upper package in the first row.
According to claim 1,
Further comprising tabs provided adjacent to the first side on the upper surface of the module substrate;
The first area is provided between the tabs and the upper packages of the second row in plan view,
the top packages of the second row are disposed closer to the tabs than the top packages of the first row;
The third side of the module substrate is adjacent to the first side and extends in a direction different from the first direction.
delete delete According to claim 2,
Each of the upper packages in the first row has a long axis parallel to the second direction,
Each of the upper packages in the second row has a long axis parallel to the first direction,
The second direction is a semiconductor module perpendicular to the first direction. According to claim 2,
The semiconductor module of claim 1 , wherein a minimum distance between the tabs and the upper packages is smaller than a minimum distance between the upper packages and the second side of the module substrate. According to claim 1,
Further comprising lower packages mounted on the lower surface of the module substrate and forming rows arranged in the first direction,
The semiconductor module of claim 1 , wherein the lower packages of a first row are shifted from the lower packages of a second row in the first direction. According to claim 1
Each of the top packages:
package substrate;
a memory chip mounted on the package substrate; and
A semiconductor module including a molding layer covering the memory chip on the package substrate. According to claim 1
The semiconductor module further comprises a connection part provided between the first upper package and the first passive element, wherein the first passive element is connected to the first upper package through the connection part.
a module substrate having a first side, a second side opposite the first side, a third side adjacent to the first side, and a fourth side opposite to the third side;
tabs provided on an upper surface of the module substrate and provided adjacent to the first side;
a plurality of memory packages mounted on the upper surface of the module substrate and forming rows arranged in a first direction; and
A passive element mounted on the upper surface of the module substrate and including a first part and a second part,
the first direction is parallel to the first side of the module substrate;
At least a portion of the passive element overlaps with any one of the memory packages in a plan view,
The memory packages are:
First packages forming a first row when viewed from a plan view; and
comprising second packages forming a second row and closer to the tabs than the first packages;
The module substrate includes a first region provided between the tabs and the second packages when viewed in plan view;
The first part of the passive element is provided between the top surface of the module substrate and the bottom surface of any one of the second packages,
The semiconductor module of claim 1 , wherein the second part of the passive element is provided in the first region, but not provided between the top surface of the module substrate and the bottom surfaces of the second packages.
According to claim 10,
Some of the memory packages form a first group;
another part of the memory packages constitutes a second group;
the memory packages of the second group are closer to the fourth side of the module substrate than the memory packages of the first group;
The tabs are:
first tabs adjacent to the third side; and
including second tabs closer to the fourth side than the first tabs;
The first tabs are electrically connected to the memory packages of the first group,
The second tabs are electrically connected to the memory packages of the second group. According to claim 11,
In the memory packages of the first group, the first packages are shifted from the second packages in the first direction;
In the memory packages of the second group, the first packages are shifted and arranged in a direction opposite to the first direction from the second packages. According to claim 12,
Further comprising a logic package mounted on the upper surface of the module substrate,
The semiconductor module of claim 1 , wherein the logic package is provided between the memory packages of the first group and the memory packages of the second group when viewed from a plan view. According to claim 13,
The tabs further include a third tab provided between the first tabs and the second tabs,
The third tab is electrically connected to the logic package. According to claim 13,
Further comprising a semiconductor device mounted on the upper surface of the module substrate,
The semiconductor module according to claim 1 , wherein the semiconductor device includes a serial presence detection chip.
According to claim 11,
The minimum distance between the first packages and the third side is smaller than the minimum distance between the second packages and the third side;
The semiconductor module of claim 1 , wherein a minimum distance between the first packages and the fourth side is smaller than a minimum distance between the second packages and the fourth side.
a module substrate having a first side parallel to a first direction and a second side parallel to the first direction;
tabs provided adjacent to the first side on an upper surface of the module substrate;
a plurality of memory packages mounted on the upper surface of the module substrate and forming rows, each of the rows parallel to the first direction; and
A passive element mounted on the upper surface of the module substrate and including a first part and a second part,
At least a portion of the passive element overlaps one of the memory packages in a plan view,
The memory packages are:
First packages forming a first row when viewed from a plan view; and
comprising second packages forming a second row and closer to the tabs than the first packages;
Each of the first packages has a long axis parallel to the second direction,
Each of the second packages has a long axis parallel to the first direction,
The second direction is perpendicular to the first direction,
One area of the module substrate is provided between the first packages and the second packages in a plan view,
The first part of the passive element is provided between the upper surface of the module substrate and the lower surface of any one of the first packages,
The second part of the passive element is provided on the one region of the module substrate, and is not provided between the upper surface of the module substrate and the lower surface of any one of the first packages.
delete According to claim 17,
The module substrate has a third side adjacent to the first side and a fourth side opposite to the third side,
The semiconductor module of claim 1 , wherein a minimum distance between the first packages and the third side is smaller than a minimum distance between the second packages and the third side. According to claim 19,
The semiconductor module of claim 1 , wherein a minimum distance between the first packages and the fourth side is smaller than a minimum distance between the second packages and the fourth side. According to claim 19,
A minimum distance between the memory packages and the tabs is smaller than a minimum distance between the second side of the module substrate and the memory packages.