CN117941033A - Method for cleaning silicon wafer and manufacturing method - Google Patents

Method for cleaning silicon wafer and manufacturing method Download PDF

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Publication number
CN117941033A
CN117941033A CN202280058117.8A CN202280058117A CN117941033A CN 117941033 A CN117941033 A CN 117941033A CN 202280058117 A CN202280058117 A CN 202280058117A CN 117941033 A CN117941033 A CN 117941033A
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Prior art keywords
cleaning
silicon wafer
wafer
sio
etching
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藤井康太
阿部达夫
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention relates to a cleaning method of a silicon wafer, which is a cleaning method for roughening the silicon wafer, and comprises the following steps: preparing a silicon wafer having a bare surface without a natural oxide film exposed as the silicon wafer; and a cleaning step of cleaning the prepared silicon wafer with an aqueous solution containing ammonium hydroxide and hydrogen peroxide to roughen the front surface and the back surface or the back surface of the silicon wafer, wherein an aqueous solution having an etching selectivity of Si to SiO 2 of 95 to 1100 is used as the aqueous solution used in the cleaning step. Thus, a cleaning method capable of roughening the front surface and the back surface or the back surface of a silicon wafer and a method for producing a silicon wafer capable of obtaining a silicon wafer with only one surface roughened are provided.

Description

Method for cleaning silicon wafer and manufacturing method
Technical Field
The present invention relates to a cleaning method of a silicon wafer capable of roughening the front surface and the back surface or the back surface of the silicon wafer.
Background
The process for producing a silicon wafer for a semiconductor device includes a single crystal production process for growing a single crystal ingot by a Czochralski (CZ) method or the like, and a wafer processing process for slicing the single crystal ingot and processing the single crystal ingot into a mirror surface shape, and may further include an annealing process for performing a heat treatment or an epitaxial growth process for forming an epitaxial layer in order to provide additional value.
The mirror-like processing includes a DSP (double-sided polishing) step and a CMP (single-sided polishing) step. More specifically, from the standpoint of particle quality and conveyance, the DSP-processed wafer can be conveyed to the CMP process as required after cleaning and in a manner of storage in water without drying. Therefore, in the CMP process, it is necessary to clamp and convey the wafer stored in water to the CMP apparatus by a robot or the like. In addition, after the CMP process, it is also necessary to clamp a wafer wetted with a polishing agent, pure water, or the like, and convey the wafer to a cleaning step as needed.
In such a wafer processing step, it is necessary to convey the wafer in a wet rather than dry environment, but particularly when the wafer sucked by the jig is detached in the wet environment, the wafer cannot be detached even if the jig is detached, and thus, there is a case where the conveyance is defective. As a cause of this, it is considered that the wafer is affected by the roughness of the wafer surface to be clamped, and if the roughness of the wafer surface to be clamped is too good, the contact area with the jig is increased, and even if the clamping is released, the wafer is not easily detached, whereas if the surface roughness of the wafer is poor, the contact area is reduced, and the wafer is easily detached. In general, the clamped surface is very likely to form a clamping mark, and the quality is lowered, so that the clamped surface is often the back surface of a silicon wafer. Therefore, from the viewpoint of reducing the conveyance failure, it is particularly preferable to provide a method for manufacturing such a wafer by roughening only the back surface of the silicon wafer.
As a general cleaning method of a silicon wafer, there is a method called RCA cleaning. The RCA cleaning is a method of performing cleaning according to a target combination SC1 (standard cleaning 1 (STANDARD CLEANING 1)) cleaning, SC2 (standard cleaning 2 (STANDARD CLEANING)) cleaning, and DHF (diluted hydrofluoric acid (Diluted Hydrofluoric Acid)) cleaning.
The SC1 cleaning is a cleaning method as follows: mixing ammonia water and hydrogen peroxide in an arbitrary proportion, removing (lift-off) the attached particles by etching the surface of the silicon wafer by using an alkaline cleaning solution, further using the electrostatic repulsion of the silicon wafer and the particles to inhibit reattachment of the silicon wafer and remove the particles. The SC2 cleaning is a cleaning method as follows: and (3) dissolving and removing metal impurities on the surface of the silicon wafer by using a cleaning solution mixed with hydrochloric acid and hydrogen peroxide in any proportion. The DHF cleaning is a cleaning method for removing a chemical oxide film on the surface of a silicon wafer with hydrofluoric acid. Further, ozone water cleaning with a strong oxidizing power may be used to remove organic substances adhering to the surface of the silicon wafer or to form a chemical oxide film on the surface of the silicon wafer after DHF cleaning. The above-described cleaning may be combined according to the purpose to perform cleaning of the silicon wafer.
Since SC1 cleaning is a cleaning accompanied by etching, it is generally known that the surface roughness of a wafer increases after SC1 cleaning.
Further, as a method for evaluating the surface roughness of the wafer, an Sa (three-dimensional calculated average height) value obtained by AFM (atomic force microscope: atomic Force Microscopy) or a haze (haze) value obtained by a particle counter can be used as an index. Haze, expressed as haze, is widely used as an index of roughness of a silicon surface, and the higher the degree of haze, the rougher the surface of a wafer. The throughput (throughput) of haze inspection using a particle counter is very high, and the entire surface of the wafer can be inspected.
Patent document 1 describes a method of forming natural oxide films having different thicknesses by cleaning a silicon wafer with a diluted aqueous solution having a composition of ammonium hydroxide, hydrogen peroxide, and water in the range of 1:1:5 to 1:1:2000.
Patent document 2 describes that in SC1 cleaning, if the concentration of OH － ionized by ammonium hydroxide is high, direct etching of Si is preferentially caused, and the surface roughness of the wafer increases.
Patent documents 3 to 6 also disclose techniques related to cleaning of semiconductor substrates such as silicon wafers.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open No. 7-66195
Patent document 2: japanese patent laid-open publication No. 2011-82372
Patent document 3: japanese patent laid-open No. 7-240394
Patent document 4: japanese patent laid-open No. 10-242107
Patent document 5: japanese patent laid-open No. 11-121419
Patent document 6: japanese patent application laid-open No. 2012-523706
Disclosure of Invention
Technical problem to be solved by the invention
As described above, in order to reduce the conveyance failure in the processing step, a silicon wafer with a rough back surface is required to be clamped. The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a cleaning method capable of roughening the front surface and the back surface or the back surface of a silicon wafer, and a method for producing a silicon wafer capable of obtaining a silicon wafer in which only one surface is selectively roughened.
Technical means for solving the technical problems
In order to achieve the above object, the present invention provides a cleaning method for roughening a silicon wafer, comprising:
preparing a silicon wafer having a bare surface without a natural oxide film exposed as the silicon wafer; and
A cleaning step of cleaning the prepared silicon wafer with an aqueous solution containing ammonium hydroxide and hydrogen peroxide to roughen the front and back surfaces or the back surface of the silicon wafer,
Wherein, as the aqueous solution used in the cleaning step, an aqueous solution having an etching selectivity of Si to SiO 2 of 95 to 1100 is used.
In such a cleaning method for a silicon wafer, a natural oxide film is formed by oxidation with hydrogen peroxide, and roughening occurs during etching, whereby a wafer with roughened front and back surfaces or back surfaces can be manufactured.
In this case, the etching selectivity of Si to SiO 2 of the aqueous solution used in the cleaning step may be determined from (etching amount of Si/etching amount of SiO 2), and any one of a silicon wafer, an epitaxial wafer, and an SOI wafer, on which a bare surface without a natural oxide film is exposed, may be used as a wafer for calculating the etching amount of Si, and a wafer with a silicon oxide film having a film thickness of 3nm or more may be used as a wafer for calculating the etching amount of SiO 2.
With such a method, the etching behavior of SiO 2 and Si can be evaluated with high accuracy.
Further, the natural oxide film formed in the cleaning step can be left on the surface of the silicon wafer after the cleaning step.
If a natural oxide film remains after cleaning, particle adhesion can be suppressed.
Further, as described above, the roughening of the present invention is produced by etching a natural oxide film formed by oxidation of hydrogen peroxide. When an aqueous solution in the above etching selection ratio range is used and the surface state after cleaning is a natural oxide film rather than a bare surface, oxidation is sufficient during cleaning and etching of Si is not performed advantageously, and therefore, roughening can be made more sufficient.
Further, the relation between the etching selectivity and the cleaning time of Si with respect to SiO 2 and the surface roughness may be obtained in advance, and the etching selectivity and the cleaning time of Si with respect to SiO 2 may be selected based on the obtained relation, and the cleaning step may be performed.
Since the roughening degree by the cleaning method of the present invention varies depending on the etching selectivity and the cleaning time of Si to SiO 2 in the cleaning step, it is effective to determine the relation between the conditions of the etching selectivity and the cleaning time and the roughening degree in advance.
The present invention also provides a method for producing a silicon wafer, characterized in that a surface of a silicon wafer, which is cleaned by the cleaning method of the present invention and has roughened front and rear surfaces, is subjected to CMP processing, and a silicon wafer, in which only a surface opposite to the surface on the one side is selectively roughened, is obtained.
In this way, by polishing only one surface after roughening the front and back surfaces, it is possible to produce a wafer in which one surface is in a good surface state and only the surface opposite to the one surface is roughened.
The present invention also provides a method for producing a silicon wafer, wherein a silicon wafer having only the back surface thereof cleaned and roughened is obtained by a single wafer processing method by the cleaning method of the present invention.
In this way, a wafer having only the back surface cleaned and roughened can be manufactured.
Effects of the invention
In the method for cleaning a silicon wafer according to the present invention, the surface and the back surface or the back surface of the silicon wafer can be roughened.
Further, according to the method for manufacturing a silicon wafer of the present invention, a wafer having a favorable surface state on one side and selectively roughened on only the surface opposite to the one side can be manufactured.
Drawings
Fig. 1 is a flowchart showing an example of a cleaning method of a silicon wafer of the present invention.
FIG. 2 is a graph showing the relationship among the haze increase, LLS number, and surface state after cleaning a bare silicon wafer with various liquid compositions; and a graph showing Scanning Electron Microscope (SEM) images of level 5 and level 9.
Fig. 3 is a graph showing the cleaning time dependence of the haze increase amount at a composition of NH 4OH:H2O2:H2 o=1:0.4:1000.
Detailed Description
As described above, in order to reduce the conveyance failure in the processing step, a silicon wafer having a rough back surface is required.
In order to solve the above-mentioned problems, the inventors of the present application have studied intensively the oxidation and etching actions using a cleaning liquid composed of ammonium hydroxide, hydrogen peroxide and water. As a result, it has been found that when a silicon wafer, in particular, a bare surface having no natural oxide film exposed thereon, is cleaned with a cleaning liquid having a relatively high etching selectivity for Si with respect to SiO 2, an oxide film formed by oxidation with hydrogen peroxide is etched with ammonium hydroxide, and the silicon wafer is rapidly etched and roughened at a position where Si is partially exposed; and the roughening behavior can be adjusted by controlling the selection ratio in a range of 95 to 1100 inclusive, thereby completing the present application.
Hereinafter, the present invention will be described in detail with reference to the drawings as an example of the embodiment, but the present invention is not limited thereto.
Fig. 1 is a flowchart showing an example of a cleaning method of a silicon wafer of the present invention.
(Step S1: preparation step of silicon wafer)
As shown in S1 of fig. 1, a silicon wafer whose front and back surfaces (or back surfaces) are to be roughened is prepared. The conductivity type or diameter of the wafer is not limited, and the surface state of the wafer needs to be such that a bare surface without a natural oxide film is exposed. For example, a polished wafer such as a DSP wafer exposes a bare surface without a natural oxide film, and can be directly cleaned in S2 described below. When the natural oxide film is present, the natural oxide film can be peeled off by, for example, HF cleaning or the like, thereby exposing the bare surface. The HF cleaning conditions are not limited, and the concentration of the chemical, the cleaning time, the cleaning temperature, and the like are not limited as long as the natural oxide film can be peeled off.
(Step S2: cleaning step)
Next, as shown in S2, the silicon wafer with the exposed surface is cleaned with an aqueous solution containing ammonium hydroxide and hydrogen peroxide, in which the etching selectivity of Si to SiO 2 (Si/SiO 2 etching selectivity) is 95 to 1100.
The roughening phenomenon according to the present invention will be described in detail from the viewpoint of etching behavior of Si and SiO 2. In addition, a method for calculating the etching amounts of Si and SiO 2 will be described below.
In fig. 2, the SC1 composition (liquid composition NH 4OH:H2O2:H2 O), the cleaning temperature, and the cleaning time were changed, and the DSP-processed wafer with the bare surface exposed was cleaned (indicated by the levels 1 to 12), and the haze value as an index of roughness was obtained by a particle counter, and the difference from the haze value obtained in advance before cleaning (hereinafter, referred to as the haze increment) was shown. Higher values indicate a rougher surface. Also shown are the results of surface observations of Ref without roughening treatment and SEM (scanning electron microscope: scanning Electronic Microscopy) at levels 5 and 9.
The liquid medicines used were 28 mass% aqueous ammonia (NH 4 OH) and 30 mass% hydrogen peroxide (H 2O2), which are also indicated as mass% (wt)%, respectively. The term "mass% means a concentration expressed as a percentage by mass of the cleaning solution to the solute (ammonium hydroxide, hydrogen peroxide) contained therein, and is also denoted as wt%. The etching selectivity of Si to SiO 2, which is determined by the calculation method described later, is also indicated in fig. 2.
It can be seen that in levels 5, 6, 8, 9, 12, the haze increases significantly. When SEM images were further observed, the irregularities were observed at level 5 and level 9, but not at Ref. From the above, it is clear that in these levels, the surface is very rough and has been roughened.
On the other hand, in levels 3, 4, and 11, the haze increased by about 0.8 to 0.9ppm, but the increase, i.e., the degree of roughening, was small, and it could not be said that it had been roughened. Further, LLS (Localized light scattering defect: localized LIGHT SCATTER) numbers are also very large, and defect quality is greatly deteriorated. The reason for this is considered that since the surface state after the cleaning is a hydrophobic surface, the bare surface is exposed during the cleaning, and etching of Si proceeds significantly, forming etching spots (etch pit). In the remaining level, the plane state was a hydrophilic plane, but the haze increase amount was also small.
Focusing on the etching selectivity of Si to SiO 2 at levels 5, 6, 8, 9, and 12, it is found that the ratios are 1098, 95.5, 280, 121, 834 in the range of about 95 to 1100, respectively, and that roughening can be performed without deteriorating the LLS number at the selectivity in the range.
The reason for this will be described in detail. In the SC1 cleaning, hydrogen peroxide functions as an oxidizing agent, and Si is oxidized to form SiO 2 (natural oxide film, hereinafter also simply referred to as oxide film). The ammonium hydroxide releases OH － through an ionization reaction, through which OH － SiO 2 on the wafer surface is etched. If the composition of the liquid medicine is general (for example, NH 4OH:H2O2:H2 o=1:1:10), an oxide film is always present on the wafer during the cleaning process, and the thickness of the oxide film formed without exposing the bare surface (Si) is always about 1nm regardless of the cleaning time. This is known to be caused by a balance of oxidation and etching rates. That is, it can be interpreted as: if H 2O2 is a chemical having a predetermined concentration or higher, the oxidation rate of Si by H 2O2 is faster than the etching rate of SiO 2 by OH －, so that an oxide film is always present on the wafer without exposing Si. In other words, if H 2O2 is lower than the predetermined concentration, the etching rate due to OH － is faster than the oxidation rate of Si due to H 2O2, and thus the etching reaction of Si due to OH － proceeds without oxidation. In this case, si is exposed after cleaning, and thus becomes a water repellent surface.
Here, for example, as shown in NH 4OH:H2O2:H2 o=1:0.4:1000 at level 5, it is seen that the H 2O2 ratio of the liquid medicine composition at the level after roughening is lower than NH 4 OH. Therefore, it is considered that when a silicon wafer with a bare surface is cleaned with such a chemical solution, the surface state after cleaning is a hydrophilic surface, and oxidation reaction is first performed to form an oxide film, but since the oxidation rate is low, etching of SiO 2 becomes a relative advantage, siO 2 is etched, and Si is etched at a position where Si is partially exposed, and roughening is performed. As the lower limit value of the selection ratio, the level 6 is 95.5 and roughened, but the level 7 is 20.5 and not roughened, and thus it is necessary to be 95 or more.
On the contrary, if the selection ratio is less than 95, si is not exposed even if the oxidation rate becomes sufficiently high and the etching action is performed, and therefore, it is considered that the roughening phenomenon cannot be performed.
Next, an upper limit value of the selection ratio is considered. As described above, the roughening of the present invention is performed by etching the oxide film formed and etching the exposed Si. That is, when the oxidation by H 2O2 is not performed or when the oxidation rate is significantly slow, the oxidation reaction is not performed, and only the Si etching is performed. In such a case, roughening according to the present invention cannot be achieved, and the LLS number is also deteriorated. Levels 3,4, 11 are the case, and their etch selectivity ratio is higher than the level at which roughening is performed (levels 5, 6, 8, 9, 12). The upper limit of the selection ratio is 1100, since the selection ratio of level 5 is 1098, roughening is performed, and level 4 is 1286, roughening cannot be performed. That is, roughening can be achieved by cleaning the exposed wafer with a cleaning liquid having an etching selectivity in the range of 95 to 1100 (further in the range of 95.5 to 1098).
The natural oxide film formed in the cleaning step is left on the wafer surface particularly after the cleaning step of S2 by using the cleaning liquid having such etching selectivity. That is, in the case of a surface state in which SiO 2 is etched and Si is etched at a position where Si is partially exposed, a wafer which is roughened more reliably and has a more sufficient degree of roughening can be obtained.
In addition, the level 5 is roughened at 1:0.4:1000 and the level 12 is roughened at 1:0.02:10, so the composition of the liquid medicine is not limited as long as the above-mentioned selection ratio is used as an index.
Next, a method for calculating the etching selectivity of Si/SiO 2 as an index in the present invention will be described in detail. The etching selectivity ratio of Si to SiO 2 of the aqueous solution used in S2 can be determined from (etching amount of Si/etching amount of SiO 2).
For the etching amount of Si, any one of a silicon wafer, an epitaxial wafer, or an SOI (silicon on insulator (Silicon on Insulator)) wafer, on which a natural oxide film is not present, i.e., a bare surface without a natural oxide film, is prepared, and the prepared wafer is cleaned with an aqueous solution of an arbitrary liquid composition (an aqueous solution of an etching selection ratio of Si/SiO 2 to be calculated), and then a difference in wafer thickness before and after cleaning, a difference in epitaxial layer thickness, or a difference in Si layer thickness of the SOI wafer is measured as the etching amount.
For example, for removing the natural oxide film, HF cleaning and the like are exemplified. The HF cleaning conditions are not limited, and the concentration of the chemical, the cleaning time, the cleaning temperature, and the like are not limited as long as the natural oxide film can be peeled off. If the natural oxide film is present on the wafer, si is not etched until the natural oxide film is etched, and the etching amount of Si cannot be accurately evaluated. Further, since the roughening phenomenon is performed by the presence of the natural oxide film and the wafer surface is roughened, the measured value may be affected, and therefore the wafer for calculating the etching amount of Si must be a wafer without the presence of the natural oxide film.
The choice of the wafer to be used may be appropriately selected according to the etching amount. In general, a silicon wafer having a diameter of 300mm has a thickness of about 775 μm, and therefore, if the etching amount is at least 1 μm or more, the thickness variation can be grasped. For example, the wafer thickness measured by a general flatness measuring instrument or the like can be used as an index, and the wafer thickness before and after cleaning can be used as an etching amount. The thickness of the wafer can be measured by the measuring instrument, and the measuring instrument is not particularly limited. For example, when the etching amount is several tens of nm, the variation in thickness is very small, and it is difficult to grasp the variation, so that it is not preferable to use the wafer thickness as an index.
When the etching amount is several tens nm to several hundreds nm, an epitaxial wafer having an epitaxial thickness of several μm or an SOI wafer having a Si layer on the surface side of the Si/SiO 2/Si structure having a thickness of several tens nm to several hundreds nm may be used, and the etching amount may be appropriately selected according to the need. In the case of an epitaxial wafer, for example, the film thickness difference can be calculated by measuring the epitaxial thickness after cleaning by extension resistance measurement (SPREADING RESISTANCE ANALYSIS) using the fact that the resistivity is different between the epitaxial layer and the substrate layer. For example, when an ellipsometer (Spectroscopic Ellipsometry) is used for measuring the film thickness of an SOI wafer, for example, when the etching amount is several nm, it is possible to evaluate with good accuracy by using an SOI wafer having an Si layer of 100nm or less. The epitaxial wafer and the SOI wafer are not particularly limited as long as the thickness of the epitaxial layer and the Si layer can be evaluated.
Next, as a wafer for calculating the etching amount of SiO 2, a wafer having a silicon oxide film of 3nm or more is preferably prepared.
In general, when SC1 cleaning is performed in which etching of an oxide film and oxidation reaction of silicon compete with each other on a silicon wafer having a natural oxide film, the silicon oxide film is etched to be thin, and an oxide species is likely to diffuse into the silicon oxide film to perform oxidation reaction of silicon, so that the natural oxide film thickness becomes a constant value without depending on the cleaning time. At this time, even if the difference in film thickness between before and after cleaning is calculated, since there is a silicon oxide film generated by the oxidation reaction of silicon, the etching amount of SiO 2 cannot be accurately obtained. Further, the typical native oxide film thickness is about 1nm, and it is also difficult to measure the 1nm variation with good accuracy.
Therefore, for example, a silicon oxide film of 3nm or more can be prepared by thermal oxidation, and the thickness of the oxide film before and after cleaning can be measured, thereby accurately measuring the etching amount of SiO 2. If the film thickness is 3nm or more, the oxide species will not diffuse in the oxide film and oxidation of silicon will not occur. Therefore, since only SiO 2 is etched, the etching amount of SiO 2 can be accurately calculated. Further, the film thickness of the silicon oxide film can be measured with high accuracy. The thicker the film thickness of SiO 2, the less likely the oxide species will diffuse in the oxide film, and further, the etching of SiO 2 alone can be ensured, and the etching amount of SiO 2 can be calculated with higher accuracy, so the upper limit of the film thickness is not specified.
The film thickness of the silicon oxide film may be appropriately selected according to the etching amount, and the wafer with the silicon oxide film prepared may be cleaned with an aqueous solution for calculating the etching selectivity of Si/SiO 2, and the difference in film thickness between before and after cleaning may be calculated.
In this way, the etching rate of Si and the etching rate of SiO 2 were obtained at the same liquid composition and cleaning temperature, and then the etching selectivity of Si to SiO 2 was calculated from (etching rate of Si/etching rate of SiO 2). The etching rate per unit time may be calculated, and the etching selectivity of Si to SiO 2 may be calculated from (the etching rate of Si/the etching rate of SiO 2).
If the index is 95 to 1100 inclusive, although oxidation reaction proceeds, the etching reaction is dominant, siO 2 is etched and Si is preferentially etched only at the position where Si is exposed, and thus roughening proceeds.
Further, since the etching behavior of Si and SiO 2 varies depending on the cleaning temperature, the etching selectivity of Si/SiO 2 can be determined in advance for each of the composition and the cleaning temperature, thereby ensuring roughening under various conditions.
In addition, the degree of roughening also varies with the washing time. Therefore, preliminary experiments for obtaining the relation between the etching selectivity of Si to SiO 2 and the cleaning time and the surface roughness (for example, the haze increase) can be performed in advance. Based on this relationship, the cleaning step S2 can be performed by selecting the etching selection ratio and the cleaning time so that the desired roughening degree is obtained after the cleaning. This is an effective method capable of further ensuring that a desired degree of roughening is obtained.
For example, fig. 3 shows the amount of haze increase when cleaning is performed at a cleaning time of 30 seconds, 60 seconds, 180 seconds, and 360 seconds, with the liquid composition being NH 4OH:H2O2:H2 o=1:0.4:1000, the cleaning temperature being 80 ℃ (etching selection ratio 1098). The longer the washing time, the more the haze increase increases, and a positive correlation is observed, and the roughening degree can be adjusted by adjusting the washing time.
The etching selection ratio can be adjusted by the liquid composition or the cleaning temperature to control the roughening degree, and the cleaning time can be adjusted to control the roughening degree, so that the etching liquid can be used according to the needs.
Next, a cleaning method in the cleaning according to the present application will be described. Most wafer cleaning methods now use a liquid such as a chemical liquid or pure water, and are called wet cleaning. The main methods include a batch method in which a large number of wafers are cleaned at one time, and a single wafer method in which wafers are processed one by one. In the batch processing method, both the front and back surfaces of the wafer are immersed in a chemical solution in terms of the device constitution, and therefore, if the cleaning of the present application is performed, the front and back surfaces are roughened. In contrast, in the single wafer processing method, since the liquid medicine is sprayed while the wafer is rotated, only one surface of the wafer can be cleaned. The inventors of the present application have studied and as a result, in the present application, if the cleaning step is performed using an aqueous solution having an etching selectivity of Si/SiO 2 of 95 to 1100, the roughening can be performed either in a batch process or in a single wafer process. An appropriate method can be selected in consideration of the wafer manufacturing process.
As described above, in order to produce a wafer having only a rough back surface, only the back surface may be cleaned in the case of the single wafer processing method, and both the front surface and the back surface may be roughened in the case of the batch processing method. It is therefore desirable that: as shown in the method for producing a silicon wafer according to the present invention, the cleaning method according to the present invention is followed by a polishing step, and the quality of the surface side is improved.
For example, by performing the wafer cleaning method of the present invention using a batch-type cleaning machine, the front surface and the back surface of a silicon wafer are roughened together, and then one surface (i.e., the front surface) is subjected to single-sided polishing such as CMP processing, whereby a wafer in which only the surface opposite to the one surface (i.e., the back surface) is selectively roughened can be manufactured.
In such a wafer, the wafer can be stably manufactured without causing a gripping failure even in a wet environment.
Examples
Hereinafter, the present invention will be described more specifically by way of examples and comparative examples of the present invention, but the present invention is not limited thereto.
Examples 1 to 8
A bare silicon wafer after DSP processing was prepared, and haze evaluation was performed by using a particle counter SP3 manufactured by KLA CORPORATION.
Next, cleaning was performed by a batch cleaner under cleaning conditions using an aqueous solution having a liquid composition, a cleaning temperature, and a cleaning time divided into 8 levels as shown in table 1 below (examples 1 to 8). The aqueous solution was prepared by using 28 mass% aqueous ammonia (NH 4 OH) and 30 mass% hydrogen peroxide (H 2O2).
Meanwhile, the Si etching rate and the SiO 2 etching rate were calculated from the difference in film thickness between before and after the cleaning by the method described above for the 8 aqueous solutions used, and the Si/SiO 2 etching selectivity was calculated.
In examples 1 to 8, except for example 5 in which the process margin was small, the etching amount of Si was calculated by using a silicon wafer having a bare surface without a natural oxide film exposed after HF cleaning, and the etching amount of Si was calculated from the wafer thickness before and after wafer cleaning by using a flatness measuring instrument. Example 5 the Si etching amount was determined from the Si layer thickness before and after cleaning using an SOI wafer having an Si layer of 80nm by using an ellipsometer M-2000V manufactured by j.a. woola. The etching amount of SiO 2 was calculated using a wafer having a 5nm oxide film formed by thermal oxidation, and the etching amount of SiO 2 was calculated from the oxide film thicknesses before and after cleaning using an ellipsometer.
In examples 1, 2, 3 and 4, the etching amounts of Si and SiO 2 were changed with the cleaning time, but the etching selectivity was the same, and the etching amounts were evaluated at the level of example 3, and the determined etching selectivity was applied to the levels of examples 1, 2 and 4.
As shown in table 1, the etching selectivity in examples 1 to 8 was within the range of the etching selectivity in the present invention (95 to 1100).
Then, the cleaned wafer was evaluated by SP3 to evaluate haze and LLS number. The difference in haze before and after cleaning was taken as an increase (also referred to as haze deterioration amount).
As shown in table 1, the haze increases at the level of examples 1 to 8 were all 2ppm or more, and were all greater than those of comparative examples 1 to 12 described below, and it was determined that all the levels were sufficiently roughened. In addition, the total level was hydrophilic, and the LLS number was evaluated to be 0 to 4pcs, but less, and good.
Further, the surface (surface) of the wafer after cleaning obtained at the level of example 3 was subjected to CMP processing with a process margin of 500 nm. The LLS number of each wafer after the CMP process was evaluated by using a particle counter SP5/19nmUP manufactured by KLA CORPORATION, and found to be 12pcs, which was good.
Then, the conveyance test of gripping the back side of the wafer held in the water and releasing the wafer on the stage of the polisher was repeated 200 times, and as a result, the conveyance was possible 200 times without occurrence of defects.
Further, the same gripping test as in example 3 was performed also on the wafers after cleaning of other examples 1 to 2 and 4 to 8, and as a result, the wafers could be carried 200 times similarly without causing any defects.
Comparative examples 1 to 12
A bare silicon wafer after DSP processing was prepared, and haze evaluation was performed by SP 3.
Next, cleaning was performed by a batch cleaner under cleaning conditions using an aqueous solution having a liquid composition, a cleaning temperature, and a cleaning time divided into 12 levels as shown in table 2 below (comparative examples 1 to 12). The aqueous solution was prepared by using 28 mass% aqueous ammonia (NH 4 OH) and 30 mass% hydrogen peroxide (H 2O2).
Meanwhile, the etching amount of Si and the etching amount of SiO 2 were calculated from the film thickness difference before and after the cleaning by the method described above for the 12 levels of the aqueous solutions used, and the Si/SiO 2 etching selectivity was calculated. In each of comparative examples 1 and 2, a silicon wafer having a bare surface without a natural oxide film exposed after HF cleaning was used, and the etching amount of Si was determined from the wafer thickness before and after wafer cleaning by a flatness measuring instrument. Comparative examples 3 to 12 the Si etching amount was determined from the thickness of the Si layer before and after cleaning by using an SOI wafer having an Si layer of 80nm and an ellipsometer M-2000V manufactured by J.A. Woollam Co. The etching amount of SiO 2 was calculated using a wafer having a 5nm oxide film formed by thermal oxidation, and the etching amount of SiO 2 was calculated from the oxide film thicknesses before and after cleaning using an ellipsometer.
As shown in table 2, the etching selectivity in comparative examples 1 to 12 was outside the range of the etching selectivity in the present invention.
Then, the cleaned wafer was evaluated by SP3 to evaluate haze and LLS number. The difference in haze before and after cleaning was taken as an increase (also referred to as haze deterioration amount).
In the levels of comparative examples 1 and 2 in which the etching selectivity was more than 1100, the haze increase was 1ppm or less and less, and it was judged that the film was not roughened. In addition, the surface state becomes a hydrophobic surface, and the LLS number is also greatly deteriorated. In comparative examples 3 to 12 in which the etching selectivity was less than 95, the haze increase was very small, and it was judged that it was not roughened.
Further, after CMP processing was performed with a process margin of 500nm on one surface (surface) of the wafer after cleaning obtained at the level of comparative example 3, the same chucking test as in example 3 was performed 200 times by a CMP processing machine. Among 200 times, a defect occurs in which 4 times of wafers cannot be detached from the jig.
Further, the same gripping test as in example 3 was performed also on the wafers after cleaning of the other comparative examples 1 to 2 and 4 to 12, and as a result, a defect was occurred in which the wafers could not be detached from the jig a plurality of times in 200 times.
From the above results, it is understood that in examples 1 to 8 of the present invention, the cleaning liquid having an etching selectivity of Si to SiO 2 of 95 to 1100 can be used to sufficiently roughen the front and back surfaces (particularly, the back surfaces) of the silicon wafer to exhibit roughness suitable for the adsorption by the jig.
On the other hand, in comparative examples 1 to 12, since the etching selectivity ratio of Si to SiO 2 was less than 95 and greater than 1100, the front and back surfaces (particularly the back surface) of the silicon wafer could not be sufficiently roughened to exhibit roughness suitable for adsorption by a jig.
In addition, the present invention is not limited to the above embodiments. The above embodiments are examples, and all embodiments having substantially the same constitution and exhibiting the same effects as the technical idea described in the claims of the present invention are included in the technical scope of the present invention.

Claims (6)

1. A cleaning method for roughening a silicon wafer, the cleaning method comprising:
preparing a silicon wafer having a bare surface without a natural oxide film exposed as the silicon wafer; and
A cleaning step of cleaning the prepared silicon wafer with an aqueous solution containing ammonium hydroxide and hydrogen peroxide to roughen the front and back surfaces or the back surface of the silicon wafer,
Wherein, as the aqueous solution used in the cleaning step, an aqueous solution having an etching selectivity of Si to SiO 2 of 95 to 1100 is used.
2. The method for cleaning a silicon wafer according to claim 1, wherein the etching selectivity of the aqueous solution used in the cleaning step, si to SiO 2, is determined from (etching amount of Si/etching amount of SiO 2), one of a silicon wafer, an epitaxial wafer and an SOI wafer, which exposes a bare surface without a natural oxide film, is used as a wafer for calculating the etching amount of Si, and a wafer with a silicon oxide film having a film thickness of 3nm or more is used as a wafer for calculating the etching amount of SiO 2.
3. The method according to claim 1 or 2, wherein a natural oxide film formed in the cleaning step is left on the surface of the silicon wafer after the cleaning step.
4. The method for cleaning a silicon wafer according to any one of claims 1 to 3, wherein the relation between the etching selectivity and the cleaning time of Si with respect to SiO 2 and the surface roughness is obtained in advance, and the etching selectivity and the cleaning time of Si with respect to SiO 2 are selected based on the obtained relation, and the cleaning step is performed.
5. A method for producing a silicon wafer, characterized in that a silicon wafer having one surface of which the front and rear surfaces are roughened and which is selectively roughened only on the surface opposite to the one surface is obtained by performing CMP processing on the surface of the silicon wafer which has been cleaned by the method for cleaning a silicon wafer according to any one of claims 1 to 4.
6. A method for producing a silicon wafer, characterized in that by the method for cleaning a silicon wafer according to any one of claims 1 to 4, a silicon wafer having only the back surface cleaned and roughened is obtained by a single wafer treatment method.
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