CN117938142A - Method for balancing level conversion time - Google Patents
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Abstract
The method for balancing the level conversion time is characterized by comprising the steps of setting a double-end output node and a control voltage VC node in a level conversion circuit, wherein the double-end output node comprises an output node A and an output node B, an A signal and a B signal are provided for a data selection circuit and are in-phase signals, the control voltage VC node provides a second delay control voltage Vc2 signal and a first delay control voltage Vc1 signal for the data selection circuit after passing through a level delay circuit, the Vc1 signal and the Vc2 signal are mutually in-phase signals, and Vc1 and Vc2 are used as level control ends to select rising edges and falling edges of the output voltage VOUT from the A signal and the B signal.
Description
Technical Field
The invention relates to the technical field of level shifting circuits, in particular to a method for balancing level shifting time.
Background
The duty cycle of the output signal may be changed due to structural problems in the level shift circuit. Fig. 1 is a schematic diagram of a level shifter circuit in the prior art. As shown in fig. 1, the level conversion circuit includes a first voltage V1 node, a second voltage V2 node, an input voltage VIN terminal, a high power supply voltage VDDH terminal, a ground terminal GND, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first inverter Ng1, wherein the V2 node is respectively connected to a drain of MP1, a gate of MP2, and a drain of MN1, sources of MP1 and MP2 are respectively connected to the VDDH terminal, sources of MN1 and MN2 are connected to GND after interconnection, the V1 node is respectively connected to a gate of MP1, a drain of MP2, and a drain of MN2, the gate of MN2 is connected to the input voltage VIN terminal, the VIN terminal is connected to an input terminal of the first inverter Ng1, an output terminal of the first inverter Ng1 is connected to the gate of MN1, and the first inverter Ng1 is connected to the low power supply voltage VDDL terminal. When the input voltage VIN increases from low to high in fig. 1, V1 is pulled low, the right pmos (i.e., MP 1) is turned on, and the gate voltage of nmos (i.e., MN 1) decreases from high to low, and V2 is pulled high. When VIN goes from high to low, the gate voltage of the right nmos (i.e., MN 1) goes from low to high and V2 is pulled low. If V2 is output, the rising edge transmission delay of single-ended output is greater than the falling edge, resulting in the output total transmission delay becoming larger and the duty cycle changing. For this, the solutions generally adopted are as follows: in order to balance the transmission delay of single-ended output, the driving capability of the fast edge side is generally weakened in the subsequent logic to achieve slow edge delay, the total transmission delay is the slow edge delay finally, and the delay of one side is increased to achieve the purpose of balancing the duty ratio.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a method for balancing the level conversion time, which improves a level conversion circuit from single-ended output to double-ended output, and selects the fast edges of in-phase double-ended output, thereby being beneficial to ensuring that the rising edge and the falling edge of the output voltage VOUT are both fast edges, and further maintaining the set duty ratio precision.
The technical scheme of the invention is as follows:
The method is characterized by comprising the steps of setting a double-end output node and a control voltage Vc node in a level conversion circuit, wherein the double-end output node comprises an output node A and an output node B, the output node A provides an A signal for a data selection circuit, the output node B provides a B signal for the data selection circuit, the A signal and the B signal are in-phase signals, the control voltage Vc node provides a second delay control voltage Vc2 signal and a first delay control voltage Vc1 signal for the data selection circuit after passing through a level delay circuit, the Vc1 signal and the Vc2 signal are mutually opposite signals, vc1 and Vc2 are used as level control ends, and rising fast edges and falling fast edges of an output voltage VOUT are selected from the A signal and the B signal.
The level conversion circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a first inverter and a second inverter, wherein the sources of the MP1 and the MP2 are connected with a high power supply voltage VDDH end, the drain electrode of the MP1 is respectively connected with the grid electrode of the MP2, the drain electrodes of the output node B and the MN1, the drain electrode of the MP2 is respectively connected with the grid electrode of the MP1, the VC node, the input end of the second inverter and the drain electrode of the MN2, the output end of the second inverter is connected with the output node A, the sources of the MN1 and the MN2 are connected with the ground end GND after being connected, the grid electrode of the MN1 is connected with the output end of the first inverter, the input end of the first inverter is respectively connected with the grid electrode of the MN2 and the input voltage VIN end, and the second inverter and the first inverter are respectively connected with a low power supply voltage VDDL end.
The level delay circuit comprises an even number of inverters which are sequentially connected in series, for example, two inverters which comprise a fifth inverter and a fourth inverter, wherein the input end of the fifth inverter is connected with a VC node, the output end of the fifth inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with a Vc2 node, the Vc2 node is connected with the input end of a third inverter in the data selection circuit, the output end of the third inverter is connected with a Vc1 node, and the third inverter, the fourth inverter and the fifth inverter are all connected with a high power supply voltage VDDH end.
The data selection circuit comprises a third PMOS tube MP3, a third NMOS tube MN3, a fourth PMOS tube MP4 and a fourth NMOS tube MN4, wherein the MP3 is connected with an output node B after being connected with a source electrode of the MN3, the MP3 is connected with an output voltage VOUT end after being connected with a drain electrode of the MN3, the MP4 is connected with an output voltage VOUT end after being connected with a source electrode of the MN4, the MP4 is connected with an output node A after being connected with a drain electrode of the MN4, the equal grid electrodes of the MP3 and the MN4 are connected with a Vc2 node, the equal grid electrodes of the MP4 and the MN3 are connected with a Vc1 node, the equal substrate of the MP3 and the MP4 are connected with a high power supply voltage VDDH end, and the equal substrate of the MN3 and the MN4 is connected with GND.
The rising fast edge of VOUT is the rising edge of the a signal and the falling fast edge of VOUT is the falling edge of the B signal.
VDDL＝3.3V，VDDH＝5.5V。
The invention has the following technical effects: the invention relates to a method for balancing level conversion time, which improves a level conversion circuit from single-ended output to double-ended output, and provides control signals which are mutually opposite in phase to a data selection circuit through a level delay circuit so as to select fast edges of in-phase double-ended output, so that the rising edge and the falling edge of final output are both fast edges, the duty ratio can be kept unchanged in the conversion logic of the level, and the driving capability of the fast edge side is not required to be weakened in subsequent logic to achieve delay of slow edges like the transmission delay caused by single-ended output in FIG. 1.
Drawings
Fig. 1 is a schematic diagram of a level shifter circuit in the prior art.
Fig. 2 is a schematic diagram of a balanced level shift time circuit formed by implementing a method for balancing level shift time according to the present invention.
Fig. 3 is a schematic diagram of the voltage timing of each node referred to in fig. 2. Each node involved includes VOUT, vc2, vc1, B, a. VOUT is the output voltage, vc1 is the first delay control voltage, vc2 is the second delay control voltage, and Vc1 and Vc2 are signals after delay of the control voltage Vc.
Fig. 4 is a timing diagram of the rising edge of each node level referred to in fig. 2. The nodes involved include a, VOUT, B. In FIG. 4, V (V, voltage volts, scale-0.5,0.0, ··6.0) is plotted on the ordinate, time (ns, time, nanoseconds, scale 1.4,1.5, ··2.4, 2.5). The rising edge of VOUT in fig. 4 is substantially coincident with the rising edge of a, and is a fast edge with respect to B.
Fig. 5 is a timing diagram of the falling edge of each node level referred to in fig. 2. Each node involved includes B, VOUT, a. In FIG. 5, V (V, voltage volts, scale-0.5,0.0, ··6.0) is plotted on the ordinate, time (ns, time, nanoseconds, scale 7.0,7.1, ·· 8.0,8.1) is plotted on the abscissa. The falling edge of VOUT in fig. 5 is substantially coincident with the falling edge of B, and is a fast edge with respect to a.
The labels in the figures are illustrated below: VIN-input voltage; v1-a first voltage or a node thereof; v2-a second voltage or node thereof; VOUT-output voltage; VC-control voltage; vc 1-a first delay control voltage; vc 2-a second delay control voltage; both A and B-are nodes or node voltages (A and B are double-ended output nodes of level conversion, and are gated by a data selection circuit, wherein the data selection circuit comprises a first transmission gate consisting of MP3 and MN3, a second transmission gate consisting of MP4 and MN4, and a third inverter Ng 3); VDDH-first supply voltage or high supply voltage; VDDL-second power supply voltage or low power supply voltage; GND-ground; ng1 to Ng 5-first to fifth inverters (where Ng5 and Ng4 constitute a level delay circuit); MP 1-MP 4-first PMOS tube to fourth PMOS tube; MN 1-MN 4-first to fourth NMOS transistors (MP 1, MP2, MN1, MN2, ng1 and Ng2 form a level conversion circuit).
Detailed Description
The invention is described below with reference to the figures (fig. 1-5) and examples.
Fig. 1 is a schematic diagram of a level shifter circuit in the prior art. Fig. 2 is a schematic diagram of a balanced level shift time circuit formed by implementing a method for balancing level shift time according to the present invention. Fig. 3 is a schematic diagram of the voltage timing of each node referred to in fig. 2. Fig. 4 is a timing diagram of the rising edge of each node level referred to in fig. 2. Fig. 5 is a timing diagram of the falling edge of each node level referred to in fig. 2. Fig. 1 is used for comparison with fig. 2 and the like of the present invention. Referring to fig. 2 to 5, a method for balancing level transition time includes setting a double-ended output node and a control voltage VC node in a level transition circuit, where the double-ended output node includes an output node a and an output node B, the output node a provides an a signal to a data selection circuit, the output node B provides a B signal to the data selection circuit, the a signal and the B signal are in-phase signals, the control voltage VC node provides a second delay control voltage VC2 signal and a first delay control voltage VC1 signal to the data selection circuit after passing through a level delay circuit, the VC1 signal and the VC2 signal are opposite signals, and VC1 and VC2 are used as level control terminals to select a rising fast edge and a falling fast edge from the a signal and the B signal as a rising fast edge and a falling fast edge of an output voltage VOUT.
The level conversion circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1 and a second NMOS tube MN2, wherein sources of the first inverter Ng1 and the second inverter Ng2 are connected with a high power supply voltage VDDH end, drains of the MP1 are respectively connected with a grid electrode of the MP2, a drain electrode of the output node B and a drain electrode of the MN1, drains of the MP2 are respectively connected with a grid electrode of the MP1, a VC node, an input end of the second inverter Ng2 and a drain electrode of the MN2, an output end of the second inverter Ng2 is connected with an output node A, sources of the MN1 and the MN2 are connected with a grounding end GND after being connected, a grid electrode of the MN1 is connected with an output end of the first inverter Ng1, an input end of the first inverter Ng1 is respectively connected with a grid electrode of the MN2 and an input voltage end VIN, and the second inverter Ng2 and the first inverter Ng1 are respectively connected with a low power supply voltage VDDL end.
The level delay circuit comprises two inverters or even number of inverters which are sequentially connected in series, wherein the two inverters comprise a fifth inverter Ng5 and a fourth inverter Ng4, the input end of the fifth inverter Ng5 is connected with a VC node, the output end of the fifth inverter Ng5 is connected with the input end of the fourth inverter Ng4, the output end of the fourth inverter Ng4 is connected with a Vc2 node, the Vc2 node is connected with the input end of a third inverter Ng3 in the data selection circuit, the output end of the third inverter Ng3 is connected with a Vc1 node, and the third inverter Ng3, the fourth inverter Ng4 and the fifth inverter Ng5 are all connected with a high power supply voltage VDDH end. The data selection circuit comprises a third PMOS tube MP3, a third NMOS tube MN3, a fourth PMOS tube MP4 and a fourth NMOS tube MN4, wherein the MP3 is connected with an output node B after being connected with a source electrode of the MN3, the MP3 is connected with an output voltage VOUT end after being connected with a drain electrode of the MN3, the MP4 is connected with an output voltage VOUT end after being connected with a source electrode of the MN4, the MP4 is connected with an output node A after being connected with a drain electrode of the MN4, the equal grid electrodes of the MP3 and the MN4 are connected with a Vc2 node, the equal grid electrodes of the MP4 and the MN3 are connected with a Vc1 node, the equal substrate of the MP3 and the MP4 are connected with a high power supply voltage VDDH end, and the equal substrate of the MN3 and the MN4 is connected with GND.
The rising fast edge of VOUT is the rising edge of the a signal and the falling fast edge of VOUT is the falling edge of the B signal. Vddl=3.3v, vddh=5.5v, and conversion from VDDL (3.3V) to VDDH (5.5V) is a basic function of level conversion.
The circuit (e.g., as shown in fig. 2) implemented by a method of balancing level shift times of the present invention is actually an improvement over the prior art fig. 1. The improved circuit is output from two ends, a level delay circuit and a data selection circuit are added, and the data selection circuit can select the fast edges output from two ends, so that the rising edge and the falling edge of the final output are both fast edges.
The circuit structure realized by the method for balancing the level conversion time consists of a level conversion circuit, a level delay circuit and a data selection circuit. The level delay circuit consists of two inverters, and signals Vc1 and Vc2 after delay of one end output signal VC of level conversion can be input into the data selection circuit. The rising edge of the level-shifted double-ended output a in fig. 2 is the fast edge (see fig. 4), the falling edge of the level-shifted double-ended output B is the fast edge (see fig. 5), and the data selection circuit has two transmission gates (the upper transmission gates MP3 and MN 3in fig. 2; the lower transmission gates MP4 and MN4 in fig. 2) and an inverter (Ng 3) which uses Vc1 and Vc2 as the level control terminals to select the fast edge of the level-shifted double-ended output signal.
The improved circuit (shown in figure 2) carries out level conversion of 3.3V-5.5V, and when the output is the rising edge, vc1 and Vc2 are respectively low and high, and the lower transmission gate is conducted, so that the output is A; when the output is the falling edge, vc1 and Vc2 are respectively high and low, and the upper transmission gate is conducted, so that the output is B. Thus, the rising edge of VOUT and the falling edge of VOUT are both fast edges.
What is not described in detail in the present specification belongs to the prior art known to those skilled in the art. It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (6)
1. The method is characterized by comprising the steps of setting a double-end output node and a control voltage Vc node in a level conversion circuit, wherein the double-end output node comprises an output node A and an output node B, the output node A provides an A signal for a data selection circuit, the output node B provides a B signal for the data selection circuit, the A signal and the B signal are in-phase signals, the control voltage Vc node provides a second delay control voltage Vc2 signal and a first delay control voltage Vc1 signal for the data selection circuit after passing through a level delay circuit, the Vc1 signal and the Vc2 signal are mutually opposite signals, vc1 and Vc2 are used as level control ends, and rising fast edges and falling fast edges of an output voltage VOUT are selected from the A signal and the B signal.
2. The method of claim 1, wherein the level shift circuit comprises a first PMOS MP1, a second PMOS MP2, a first NMOS MN1, a second NMOS MN2, a first inverter and a second inverter, sources of MP1 and MP2 are connected to a high power supply voltage VDDH terminal, drains of MP1 are connected to gates of MP2, output nodes B and MN1, drains of MP2 are connected to gates of MP1, VC nodes, input terminals of the second inverter and drains of MN2, an output terminal of the second inverter is connected to an output node a, sources of MN1 and MN2 are connected to a ground GND after interconnection, gates of MN1 are connected to an output terminal of the first inverter, an input terminal of the first inverter is connected to gates of MN2 and an input voltage terminal, and both the second inverter and the first inverter are connected to a low power supply voltage VDDL terminal.
3. The method for balancing level shift time according to claim 1, wherein the level delay circuit comprises an even number of inverters connected in series in sequence, an input terminal of a first inverter of the even number of inverters is connected to a VC node, an output terminal of a last inverter of the even number of inverters is connected to a VC2 node, the VC2 node is connected to an input terminal of a third inverter of the data selection circuit, an output terminal of the third inverter is connected to a VC1 node, and each of the third inverter and the even number of inverters is connected to a high power supply voltage VDDH terminal.
4. The method for balancing level shift time according to claim 3, wherein the data selection circuit comprises a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4, wherein MP3 is connected to the output node B after being interconnected with the source electrode of MN3, MP3 is connected to the output voltage VOUT terminal after being interconnected with the drain electrode of MN3, MP4 is connected to the output voltage VOUT terminal after being interconnected with the source electrode of MN4, MP4 is connected to the output node a after being interconnected with the drain electrode of MN4, the gate of MP3 and MN4 is connected to the node Vc2, the gate of MP4 and MN3 is connected to the node Vc1, the substrates of MP3 and MP4 are connected to the high power supply voltage VDDH terminal, and the substrates of MN3 and MN4 are connected to GND.
5. The method of balancing level shift time of claim 1, wherein the rising edge of VOUT is a rising edge of an a signal and the falling edge of VOUT is a falling edge of a B signal.
6. The method of balancing level shift time according to claim 1, wherein VDDL = 3.3V and vddh = 5.5V.
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| CN202311825696.7A CN117938142A (en) | 2023-12-27 | 2023-12-27 | Method for balancing level conversion time |
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