CN117936539A - A resistor array structure - Google Patents

Abstract

The embodiment of the invention discloses a resistor array structure, which comprises a plurality of polysilicon layers, a plurality of first metal layers, a plurality of second metal layers and a plurality of third metal layers; each resistor in the resistor array structure is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching unit, and the resistance and the impedance of different matching paths in the same matching unit are equal; the first metal layer on each polysilicon layer is connected with a specific modulation potential, so that the purpose of stabilizing the resistance value of the polysilicon is achieved; the resistor array structure is also provided with a second suspended metal layer and a third suspended metal layer, so that the metal layers above the polysilicon layers can be ensured to be consistent, and the temperature gradient distribution of the polysilicon layers forming each resistor is uniform.

Description

A resistor array structure

Technical Field

The present invention relates to the field of microelectronic technology, and more particularly to a resistor array structure.

Background technique

As the link between the digital domain and the analog domain, the digital-to-analog converter (DAC) is widely used in electronic products, and high-precision DAC plays an extremely important role in the high-resolution digital-to-analog conversion process, in which the quality of resistor matching is crucial. As shown in Figure 1, it is a 3-bit thermometer code DAC structure (as shown in Figure 1), in which resistors U0~U6 must be matched equally. The common resistor array is shown in Figure 2. Resistors U0~U6 are arranged in sequence without fine matching, occupying a large layout area, and resistor mismatch will lead to serious power loss, increased noise, decreased signal-to-noise ratio, affecting the sensitivity of the circuit, and making the frequency response uneven. Therefore, for high-precision resistor modules, good matching is particularly important to obtain stable performance indicators and long life. Only through reasonable matching can the theoretical performance of circuit components be better exerted.

Summary of the invention

In view of this, the present invention proposes a layout design of a resistor array structure to solve the technical problem caused by the inability to precisely match resistors in the prior art.

An embodiment of the present invention provides a resistor array structure, comprising a plurality of polysilicon layers arranged in parallel to each other, a plurality of first metal layers arranged in parallel to each other, a plurality of second metal layers arranged in parallel to each other, and a plurality of third metal layers arranged in parallel to each other; the polysilicon layers are arranged in at least one row; the lengths of the polysilicon layers are equal and arranged at the same intervals; the first metal layer is stacked on top of the polysilicon layer; the second metal layer is stacked on top of the first metal layer; the third metal layer is stacked on top of the second metal layer; the polysilicon layer, the first metal layer and the third metal layer have the same extension direction, and the second metal layer The extension direction is perpendicular to the extension direction of the polysilicon layer; the resistor array structure includes multiple resistors, each resistor is composed of multiple polysilicon layers electrically connected, and two adjacent polysilicon layers constituting the same resistor are electrically connected through a matching path in a matching unit; each matching unit includes matching paths equal to the number of resistors; each matching path includes a second matching metal layer and a third matching metal layer with ends electrically connected; wherein, the second matching metal layer is the second metal layer constituting the matching unit in the second metal layer, and the third matching metal layer is the third metal layer constituting the matching unit in the third metal layer.

Preferably, the first metal layer on the polysilicon layer is connected to a corresponding modulation potential to reduce the influence of the substrate voltage on the resistance value of the resistor.

Preferably, the first metal layer on the plurality of polysilicon layers constituting the same resistor is connected to the same modulation potential.

Preferably, the same modulation potential is equal to the voltage at the input end of the resistor.

Preferably, when the polysilicon layers are distributed in the same row, the matching unit includes a first matching unit; when the polysilicon layers are distributed in different rows, the matching unit includes a first matching unit and a second matching unit, wherein the first matching unit is a matching unit for realizing electrical connection between the polysilicon layers located in the same row, and the second matching unit is a matching unit for realizing electrical connection between the polysilicon layers located in different rows.

Preferably, the number of polysilicon layers in the same row is 2k times the number of resistors, wherein k is any positive integer; the polysilicon layers constituting the same resistor in the same row are electrically connected via 2k-1 first matching units.

Preferably, k first matching units among the 2k-1 first matching units are located at the first side edge of the rectangular area, and the remaining k-1 first matching units are located at the second side edge of the rectangular area, wherein the rectangular area is an area formed by a polysilicon layer in the same row, and the first side and the second side are opposite and are respectively located at both ends of the polysilicon layer.

Preferably, when the polysilicon layers are distributed in different rows, the number of the polysilicon layers in each row is equal.

Preferably, the first matching unit is symmetrical about the symmetry axis, and two polysilicon layers electrically connected through the matching path in the first matching unit are located on both sides of the symmetry axis and are axisymmetric;

Each matching path of the first matching unit includes two third matching metal layers and one second matching metal layer, the two third matching metal layers are located on both sides of the symmetry axis and are axially symmetrical, two ends of the second matching metal layer are respectively electrically connected to one end of the two third matching metal layers, and the other ends of the two third matching metal layers are respectively electrically connected to two axially symmetrical polysilicon layers.

Preferably, the third matching metal layer is connected to the second matching metal layer via a first type through hole; wherein the first type through hole is a through hole for realizing electrical connection between the second metal layer and the third metal layer.

Preferably, the second suspended metal layer and the second matching metal layer are disconnected near the first type through hole, wherein the second suspended metal layer is a second metal layer in the second metal layer that is not connected to any potential and is not connected to the first metal layer, the third metal layer or the polysilicon layer;

The third suspended metal layer is disconnected from the third matching metal layer near the first type through hole, wherein the third suspended metal layer is a third metal layer in the third metal layer that is not connected to any potential and is not connected to the first metal layer, the second metal layer or the polysilicon layer.

Preferably, the first type through holes in the same first matching unit are arranged isosceles, that is, the length of the second matching metal layer in each matching path in the same first matching unit is an arithmetic progression.

Preferably, the length of the second matching metal layer in each matching path in the same first matching unit increases arithmetically toward an edge of the rectangular area parallel to a first direction; wherein the first direction is a direction parallel to an extension direction of the second metal layer.

Preferably, each of the polysilicon layers is connected to the third matching metal layer via a second type through hole located at an end of the polysilicon layer, wherein the second type through hole is a through hole for electrically connecting the polysilicon layer and the third matching metal layer.

Preferably, each first metal layer connected to the modulation potential is disconnected near the second type through hole, and the length of each first metal layer connected to the modulation potential is less than the length of the polysilicon layer, so that there is no electrical connection between the second type through hole and the first metal layer connected to the modulation potential.

Preferably, when the number of polysilicon layers constituting the same resistor in the same row is greater than 2, two first matching units connected to the same polysilicon layer are respectively distributed at two ends of the polysilicon layer.

Preferably, the resistance values of the matching paths in the first matching unit are equal.

Preferably, the lengths of the matching paths in the first matching unit are equal.

Preferably, the second matching unit includes a matching path located above the rectangular area, and a matching path located outside the rectangular area, wherein the resistance values of the matching paths located above the rectangular area in each matching path are equal; wherein the rectangular area is an area formed by a polysilicon layer located in the same row.

Preferably, the lengths of the matching paths in the second matching unit and located on the rectangular area are equal.

Preferably, the resistance values of the matching paths in the second matching unit that are outside the rectangular area are equal.

Preferably, the lengths of the matching paths outside the rectangular area in the respective matching paths in the second matching unit are equal.

Preferably, when the number of polysilicon layers constituting the same resistor in the same row is greater than 2, a spacing region is further provided between the first matching units located at the first side edge and the second side edge of the rectangular region in the length direction of the polysilicon layer, and the spacing region includes second spacing metal layers equal in number to the resistors;

The first metal layer on the plurality of polysilicon layers constituting the same resistor is electrically connected to the same second spacer metal layer, and the second spacer metal layer is the second metal layer located in the spacer region.

Preferably, third modulation metal layers having a number equal to the number of resistors are provided on both sides or one side of the rectangular area, for electrically connecting to the second spacing metal layers respectively.

Preferably, virtual resistors are further arranged on both sides of the rectangular area formed by the polysilicon layer in the same row, and the virtual resistors include the polysilicon layer, the first metal layer and the third metal layer.

Preferably, the virtual resistor further includes a second metal layer.

Preferably, the polysilicon layer constituting the virtual resistor and the first metal layer constituting the virtual resistor are connected to the ground potential, and the second metal layer constituting the virtual resistor and the third metal layer constituting the virtual resistor are suspended and not connected to any potential.

Compared with the prior art, the present invention adopts an upgraded common centroid matching method, which has the following advantages:

1. The first metal layer on each polysilicon layer constituting the resistor is connected to a specific modulation potential. The reverse modulation effect of the first metal layer can reduce or offset the electrical deviation of the polysilicon resistor caused by the substrate, thereby achieving the purpose of stabilizing the resistance of the polysilicon resistor;

2. The resistor array structure is further provided with a second suspended metal layer and a third suspended metal layer, each of which is not connected to the second matching metal layer and the third matching metal layer, so that the metal layers above each polysilicon layer can be kept consistent, so that the temperature gradient of the polysilicon layer constituting each resistor is evenly distributed, and the wiring is evenly distributed, so as to better ensure that the impedance of each resistor is matched and consistent;

3. The impedance of the resistors in different matching paths in the same matching unit is equal, so that the impedance of each resistor can be guaranteed to be consistent;

4. The endpoints of the second matching metal layer and the third matching metal layer in the first matching unit are set to be cut off near each first type through hole to reduce the influence of the parasitic capacitance caused by the second matching metal layer and the third matching metal layer not being cut off near each first type through hole on the resistance matching.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG1 is a schematic diagram of a prior art digital-to-analog converter;

FIG2 is a schematic diagram of a resistor array structure in the prior art;

FIG3 is a first schematic diagram of a resistor array structure in this embodiment;

FIG4 is an enlarged view of the second type through hole vicinity of the resistor array structure in this embodiment;

FIG5 is a schematic diagram of a matching unit in this embodiment;

FIG6 is a second schematic diagram of the resistor array structure in this embodiment;

FIG. 7 is an enlarged schematic diagram of the second matching unit in FIG. 6 in this embodiment.

Detailed ways

The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes only and are not necessarily drawn to scale.

The present embodiment discloses a resistor array structure of a DAC, comprising a plurality of polysilicon layers arranged in parallel to each other, a plurality of first metal layers arranged in parallel to each other, a plurality of second metal layers arranged in parallel to each other and a plurality of third metal layers arranged in parallel to each other; the polysilicon layers are arranged in at least one row; and insulating dielectric isolation layers are respectively arranged between the polysilicon layer and the first metal layer, between the first metal layer and the second metal layer, and between the second metal layer and the third metal layer; wherein the lengths of the polysilicon layers are equal and arranged at the same intervals; the first metal layer is stacked on the polysilicon layer; the second metal layer is stacked on the first metal layer; the third metal layer is stacked on the second metal layer; the polysilicon layers constituting the resistors arranged in the same row are sequentially arranged in parallel in a rectangular area at the same intervals, and the lengths and widths of the first metal layers are the same; the second metal layer is arranged perpendicularly to the first metal layer, and the third metal layer is arranged perpendicularly to the second metal layer. The polysilicon layer, the first metal layer and the third metal layer overlap in the direction of stacking.

The resistor array structure includes multiple resistors, each resistor is composed of multiple electrically connected polysilicon layers, and two adjacent polysilicon layers constituting the same resistor are electrically connected through a matching path in a matching unit, so that the multiple polysilicon layers constituting the same resistor can be electrically connected; the matching unit includes a second matching metal layer and a third matching metal layer whose ends are electrically connected; wherein the second matching metal layer is the second metal layer constituting the matching unit in the second metal layer, and the third matching metal layer is the third metal layer constituting the matching unit in the third metal layer.

The matching unit includes a first matching unit and a second matching unit, wherein the first matching unit is a matching unit for realizing electrical connection between the polysilicon layers in the same row, and the second matching unit is a matching unit for realizing electrical connection between the polysilicon layers in different rows. Each of the matching units includes matching paths equal in number to the resistors, and the resistance values of the matching paths in the same matching unit are the same.

The number of polysilicon layers in the same row is an even multiple of the number of resistors, that is, the number of polysilicon layers in the same row is 2k times the number of resistors, where k is an arbitrary positive integer; the polysilicon layers constituting the same resistor in the same row are electrically connected through 2k-1 first matching units. Among the 2k-1 first matching units, k first matching units are located at the first side edge of the rectangular area, and the remaining k-1 first matching units are located at the second side edge of the rectangular area, wherein the rectangular area is the area formed by the polysilicon layers in the same row, and the first side and the second side are opposite and are located at both ends of the polysilicon layer respectively.

It should be noted that in order to symmetrically arrange the wirings (first metal layer, second metal layer and third metal layer) on the polysilicon layers in the same row, the number of polysilicon layers in the same row is set to an even number.

As an example, FIG3 is a schematic diagram of a resistor array structure of a 3-bit DAC, with a total of 2 ³ -1=7 resistors: U0, U1, U2, U3, U4, U5 and U6, each resistor being composed of four polysilicon layers 14 connected together, and two adjacent ones of the four polysilicon layers 14 constituting the same resistor are connected through a matching path in a first matching unit, and all the polysilicon layers 14 are arranged side by side in a row, so the resistor array structure includes three first matching units: a first matching unit 1, a first matching unit 2 and a first matching unit 3, each polysilicon layer 14 is connected to the third matching metal layer 13 in the first matching unit through a second type through hole Via3p, that is, the polysilicon layer 14 is connected to the first matching unit through the second type through hole Via3p, so that the polysilicon layers 14 are connected to each other through the first matching unit. As shown in FIG3 , the resistor U0 is composed of four polysilicon layers U0<0>, U0<1>, U0<2> and U0<3> that are electrically connected, the resistor U1 is composed of four polysilicon layers U1<0>, U1<1>, U1<2> and U1<3> that are electrically connected, the resistor U2 is composed of four polysilicon layers U2<0>, U2<1>, U2<2> and U2<3> that are electrically connected, the resistor U3 is composed of four polysilicon layers U3<0>, U3<1>, U3<2> and U3<3> that are electrically connected… the resistor U6 is composed of four polysilicon layers U6<0>, U6<1>, U6<2> and U6<3> that are electrically connected, wherein U0<0> and U0<1> are connected via one of the matching paths in the first matching unit 1, and U0<1> and U0<2> are connected via one of the matching paths in the first matching unit 2. The seven matching paths in the first matching unit 1 respectively establish electrical connections between U0<0> and U0<1>, between U1<0> and U1<1>, between U2<0> and U2<1>, ... between U6<0> and U6<1>, and the seven matching paths in the first matching unit 2 respectively establish electrical connections between U0<1> and U0<2>, between U1<1> and U1<2>, between U2<1> and U2<2>, ... between U6<1> and U6<2>; the seven matching paths in the first matching unit 3 respectively establish electrical connections between U0<2> and U0<3>, between U1<2> and U1<3>, between U2<2> and U2<3>, ... between U6<2> and U6<3>. Among them, one end of U0<0>, U1<0>, U2<0>, U3<0>, U4<0>, U5<0> and U6<0> is used as the input end, and the other end is connected to the first matching unit 1; one end of U0<1>, U1<1>, U2<1>, U3<1>, U4<1>, U5<1> and U6<1> is connected to the first matching unit 1, and the other end is connected to the first matching unit 2; one end of U0<2>, U1<2>, U2<2>, U3<2>, U4<2>, U5<2> and U6<2> is connected to the first matching unit 2, and the other end is connected to the first matching unit 3; one end of U0<3>, U1<3>, U2<3>, U3<3>, U4<3>, U5<3> and U6<3> is connected to the first matching unit 3, and the other end is used as the output end Vout.

The connection path of the resistors is described below with reference to FIG. 3 , taking resistor U0 as an example, including U0<0>, U0<1>, U0<2>, and U0<3> that are electrically connected in sequence. The input end of the resistor U0 is connected to SW0 through one end of U0<0>; the other end of U0<0> is connected to the third matching metal layer in a matching path of the first matching unit 1 through the second type through hole Via3p, and one end of another third matching metal layer in the matching path is connected to one end of U0<1> through the second type through hole Via3p; the other end of U0<1> is connected to the third matching metal layer in a matching path in the first matching unit 2 through the second type through hole Via3p, and one end of another third matching metal layer in the matching path is connected to one end of U0<2> through the second type through hole Via3p; the other end of U0<2> is connected to the third matching metal layer in a matching path in the first matching unit 3 through the second type through hole Via3p, and one end of another third matching metal layer in the matching path is connected to one end of U0<3> through the second type through hole Via3p, and the other end of U0<3> is output as the output end Vout.

As can be seen from Figure 3, one of the first matching units 2 is located at the first side edge of the rectangular area, and two of the first matching units (the first matching unit 1 and the first matching unit 3) are located at the second side edge of the rectangular area, wherein the rectangular area is an area formed by the polysilicon layer in the same row, and the first side and the second side are opposite to each other and are respectively located at both ends of the polysilicon layer 14.

As shown in Figure 4, an enlarged view of the vicinity of the second type through hole Via3p in Figure 3 can be seen from Figure 4 that the length of each first metal layer 11 connected to the modulation potential is less than the length of the polysilicon layer 14, and the first metal layer 11 is disconnected near the second type through hole Via3p, so that the second type through hole Via3p is not electrically connected to the first metal layers 11 connected to the modulation potential.

As shown in FIG5 , it is a schematic diagram of the first matching unit, each first matching unit is an axisymmetric figure (the direction of the symmetry axis Z _L is the direction of the first metal layer 11/polysilicon layer 14), and the two polysilicon layers electrically connected by the matching path in the first matching unit are located on both sides of the symmetry axis and are axisymmetric, that is, U0<0> and U0<1> are symmetric about the symmetry axis Z _L , U1<0> and U1<1> are symmetric about the symmetry axis Z _L , U2<0> and U2<1> are symmetric about the symmetry axis Z _L , U3<0> and U3<1> are symmetric about the symmetry axis Z _L , U4<0> and U4<1> are symmetric about the symmetry axis Z _L , U5<0> and U5<1> are symmetric about the symmetry axis Z _L , and U6<0> and U6<1> are symmetric about the symmetry axis Z _L. Each first matching unit includes matching paths equal to the number of resistors, and each matching path includes two axisymmetric third matching metal layers 131 located on both sides of the symmetry axis, and a second matching metal layer 121 connecting the two mutually symmetric third matching metal layers 131. The two third matching metal layers constituting each matching path are located on both sides of the symmetry axis and are axially symmetrical, the two ends of the second matching metal layer are electrically connected to one end of the two third matching metal layers, and the other ends of the two third matching metal layers are electrically connected to two axially symmetrical polysilicon layers. The two symmetrical third matching metal layers 131 located on both sides of the symmetry axis Z _L are connected to one of the second matching metal layers 121 through the first type via Via23; as shown in FIG. 5, the resistance value formed by the two symmetrical second matching metal layers 121 located on both sides of the symmetry axis and the third matching metal layer 131 connected thereto in series is equal, so that each matching path in each first matching unit can be matched. As an example, in this embodiment, the widths of all second metal layers 12 and all third metal layers 13 are equal, and the lengths of each matching path are equal, that is, the sum of the lengths of the two symmetrical third matching metal layers 131 and the second matching metal layer 121 connected thereto in each matching path is equal. As shown in FIG. 5 , a matching path L0 connecting U0<0> and U0<1> and a matching path L6 connecting U6<0> and U6<1> are shown. The lengths of L0 and L6 are equal, and the resistances of the matching paths L0 and L6 are equal.

As shown in Figures 3 and 5, the resistor array structure is also provided with a second suspended metal layer 122 and a third suspended metal layer 132. The second suspended metal layer 122 and the second matching metal layer 121 are disconnected near the first type through hole Via23, and the third suspended metal layer 132 and the third matching metal layer 131 are disconnected near the first type through hole Via23. The second suspended metal layer 122 is the second metal layer that is not connected to any potential, nor to the first metal layer, the third metal layer or the polysilicon layer. The third suspended metal layer 132 is a metal layer in the third metal layer that is not connected to any potential, nor to the first metal layer, the second metal layer or the polysilicon layer. It can ensure that the metal layers above each polysilicon layer 14 are consistent, so that the temperature gradient distribution of the polysilicon layer 14 constituting each resistor is uniform, and the routing distribution is uniform, thereby better ensuring that the impedance of each resistor is matched and consistent. The endpoints of the second matching metal layer 121 and the third matching metal layer 131 in each matching unit are arranged near each first type through hole Via23, so as to reduce the influence of the parasitic capacitance caused by the second metal layer 12 and the third metal layer 13 not being cut off near each first type through hole Via23 on the resistance matching; that is, each second suspended metal layer 122 is disconnected from the second matching metal layer 121 in the matching unit by a small distance near the first type through hole Via23 connecting the second matching metal layer 121 and the third matching metal layer 131 in the matching path, and each third suspended metal layer 132 is disconnected from the third matching metal layer 131 in the matching path by a small distance near the first type through hole Via23 connecting the second matching metal layer 121 and the third matching metal layer 131 in the matching path, thereby maximally ensuring the uniform distribution of each metal layer, ensuring the uniform distribution of the metal layers on each polysilicon layer 14, and ensuring the uniform distribution of the temperature gradient.

As shown in FIG5 , the first type vias Via23 in each first matching unit are arranged isosceles, and the number is twice the number of resistors, that is, the number is 14, and they are arranged symmetrically on both sides of the symmetry axis Z _L. Therefore, the length of the second matching metal layer 121 in the same first matching unit is an arithmetic progression, and increases arithmetic progression toward the edge of the rectangular area parallel to the first direction (also toward the direction of the second type vias Via3p electrically connected to the polysilicon layer 14 and the third matching metal layer 131 in the matching unit), so that the closer the third matching metal layer 131 is to the edge of the rectangular area (also the closer to the second type vias Via3p), the shorter the length is, and the longer the second matching metal layer 121 electrically connected thereto is; wherein the first direction is a direction parallel to the extension direction of the second metal layer.

When the number of polysilicon layers constituting the same resistor in the same row is greater than 2, the two first matching units connected to the same polysilicon layer 14 are respectively distributed at the two ends of the polysilicon layer 14, that is, respectively close to the two parallel edges of the rectangular area. As shown in FIG3 , each resistor is composed of four polysilicon layers 14 connected, the two ends of the polysilicon layers U0<1> to U6<1> are respectively connected to the first matching unit 1 and the first matching unit 2, and the two ends of the polysilicon layers U0<2> to U6<2> are respectively connected to the first matching unit 2 and the first matching unit 3; the first matching unit 1 and the first matching unit 3 are presented as inverted triangles, close to the upper edge of the rectangular area; the first matching unit 2 is presented as an equilateral triangle, close to the lower edge of the rectangular area, wherein the rectangular area is the area formed by the polysilicon layers in the same row.

As shown in Figure 3, when the number of polysilicon layers used to form the same resistor in the same row is greater than 2, a spacing area 15 is further provided between two matching units connected to the same polysilicon layer 14 along the length direction of the polysilicon layer 14, that is, a spacing area is also provided between the first matching units located at the first side edge and the second side edge of the rectangular area, and the spacing area 15 includes second spacing metal layers 123 equal to the number of resistors, and the second spacing metal layer 123 is a second metal layer located in the spacing area; wherein, each second spacing metal layer 123 equal to the number of resistors in the spacing area is electrically connected to the first metal layer 11 on each polysilicon layer 14 constituting the same resistor; specifically, the electrical connection is made through a third type through hole Via12; wherein, the third type through hole Via12 is a through hole for realizing electrical connection between the first metal layer 11 and the second metal layer 12. As shown in FIG3 , two matching units connected to the same polysilicon layer 14 are spaced apart by seven second spacing metal layers 123, which are the same number as the resistors, in the direction along the length of the polysilicon layer 14. Each second spacing metal layer 123 is connected to four first metal layers 11 on four polysilicon layers 14 constituting the same resistor through four third-type through holes Via12. Each second spacing metal layer 123 is connected to a third modulation metal layer 133 through a first-type through hole Via23. The first-type through hole Via23 connecting the second spacing metal layer 123 and the third modulation metal layer 133 is connected to the first-type through hole Via14. a23 is located outside the rectangular area formed by the arrangement of the polysilicon layer 14, and each third modulation metal layer 133 is connected to a corresponding modulation potential Vuo~Vu6, which corresponds to the voltage of the input end of each resistor, and the third modulation metal layer 133 is a metal layer in the third metal layer connected to the modulation potential; specifically, as shown in FIG3, in this embodiment, the input end of each resistor is a port connecting the polysilicon layer U0<0>~U0<6> and each switch tube SW0~SW6, that is, the voltage at the input end of each resistor corresponds to the voltage at the port marked SW0~SW6 in the figure. The output port of each resistor is a port where the polysilicon layer U0<3>~U6<3> is electrically connected to each other, that is, the port marked VOUT in FIG3.

As shown in Figure 3, the seven third modulation metal layers 133 connected to the modulation potentials Vuo~Vu6 are located on both sides of the rectangular area; in other embodiments, the third modulation metal layer 133 connected to the modulation potential may also be located on the same side of the rectangular area, and the two matching units connected to the same polysilicon layer 14 may also be separated by a second spacing metal layer 123 greater than the number of resistors in the direction along the length of the polysilicon layer 14. This is not limited here and can be flexibly set according to specific applications and layout design.

It should be noted that the resistor in this embodiment uses a polysilicon layer 14, and there are carriers in the polysilicon layer 14. Therefore, when affected by the substrate electric field, the distribution of carriers in the resistor will change, and the resistance value will change slightly. The stronger the electric field, the more obvious the resistance change. In this embodiment, the first metal layer 11 on each polysilicon layer 14 is connected to a specific modulation voltage. By utilizing the reverse modulation effect of the first metal layer 11, the electrical deviation of the polysilicon resistor caused by the substrate can be reduced or offset, thereby achieving the purpose of stabilizing the resistance value of the polysilicon resistor.

As shown in FIG3 , a polysilicon layer 14, a first metal layer 11, and a third metal layer 13 are also provided on the left and right sides of the rectangular area, acting as a dummy resistor, which can alleviate the deviation of the resistance value caused by the chip process. In other embodiments, dummy resistors may be provided all around the rectangular area, and dummy resistors may be provided above or below the rectangular area, and the number and shape of the settings are not limited. In other embodiments, a second metal layer may also be provided between the first metal layer and the second metal layer acting as a dummy resistor; as an example, the polysilicon layer 14 acting as a dummy resistor and the first metal layer acting as a dummy resistor are connected and connected to the ground potential, and the second metal layer acting as a dummy resistor and the third metal layer acting as a dummy resistor are suspended.

The embodiment shown in FIG3 takes 3 bits as an example for demonstration, with a total of 2 ³ -1=7 resistors, each resistor being composed of 4 connected polysilicon layers 14, and all the polysilicon layers being distributed in one row. In other embodiments, it can also be any ibit (i is a positive integer), and the corresponding number of resistors is 2 ⁱ -1. The number of polysilicon layers 14 constituting each resistor can also be set according to specific requirements, and all the polysilicon layers can also be distributed in multiple rows. When the polysilicon layers are distributed in different rows, the number of the polysilicon layers in each row is equal.

As shown in FIG6 , the polysilicon layer 14 is divided into multiple rows for arrangement. Taking 3bit as an example, it includes 2 ³ -1=7 resistors, each resistor is composed of 8 polysilicon layers 14 connected, and 7*8=56 polysilicon layers 14 are divided into two rows for arrangement, each row includes 7*4=28 polysilicon layers 14, and the polysilicon layers 14 in the same row are electrically connected through the first matching unit, and the polysilicon layers 14 in the same row include 3 first matching units. As shown in FIG6 , the polysilicon layer in the lower row includes the first matching unit 1, the first matching unit 2 and the first matching unit 3, and the polysilicon layer in the upper row includes the first matching unit 5, the first matching unit 6 and the first matching unit 7. U0<3>~U6<3> and U0<4>~U6<4> in different rows are electrically connected through the second matching unit 4. The second matching unit is the same as the first matching unit, and includes 7 matching paths equal to the number of resistors. As shown in FIG6 , as an example, each matching path of the second matching unit 4 includes three third matching metal layers 131 and two second matching metal layers 121, and each matching path of the second matching unit 4 is composed of the second matching metal layers 121 and the third matching metal layers 131 connected alternately. As shown in FIG6 , the second matching unit 4 is divided into three parts: 41, 42 and 43, wherein 41 and 43 are located above the rectangular area, and 42 is located outside the rectangular area and between 41 and 43, and is used to connect 41 and 43. As an embodiment shown in FIG6 , due to space limitations, the resistance of the matching paths located above the rectangular area in each matching path of the second matching unit 4 is equal; preferably, the length of the matching paths located above the rectangular area in each matching path is equal, that is, the sum of the lengths of 41 and 43 between different matching paths and constituting the same matching path is equal; as shown in FIG6 and FIG7 , the lengths of different matching paths located in 42 are an arithmetic progression, so that the lengths of each matching path of the second matching unit 4 are an arithmetic progression. As shown in FIG. 7 , it is an enlarged view of the second matching unit in FIG. 6 , and FIG. 7 schematically shows two matching paths in 41 and 43 located on the rectangular area, wherein the sum of the lengths of L01 and L02 is equal to the sum of the lengths of L61 and L62, and the lengths of different matching paths in 42 are an arithmetic progression. In addition, each row of the polysilicon layer 14 includes a spacing region, and the spacing region includes second spacing metal layers 123 equal to the number of resistors, and each second spacing metal layer 123 is electrically connected to the corresponding third modulation metal layer 133.

It should be noted that, preferably, the impedance of each matching path of the second matching unit 4 is preferably equal, and the corresponding length is also equal. Due to space limitations, the length of each matching path in FIG6 presents an arithmetic progression. As another embodiment, the shorter matching path in 42 can be made equal in length by adding bends to each matching path in 42, thereby making the length of each matching path of the second matching unit 4 equal, and the corresponding impedance is also equal. As shown in FIG6, both sides of the polysilicon layer 14 constituting the resistor in each row also include a polysilicon layer acting as a virtual resistor. The lengths of L01, L02, L61 and L62 in FIG6 and FIG7 all include the length above the polysilicon layer acting as a virtual resistor, but since the lengths of L01 and L02, or L61 and L6 above the polysilicon layer acting as a virtual resistor are equal, the sum of the lengths of L01 and L02 located above the rectangular area constituting the resistor is also equal to the sum of the lengths of L61 and L62 located on the rectangular area constituting the resistor. The shape of the matching path of the second matching unit and the number of metal layers included include but are not limited to those shown in FIG. 6 and FIG. 7 . The matching paths that can ensure that the corresponding impedance differences between the matching paths are within an acceptable range are within the protection scope of the present invention.

For example, ibit includes ²ⁱ -1 resistors. When each resistor is composed of m polysilicon layers 14 connected together, the number of polysilicon layers is ( ²ⁱ -1)*m. All polysilicon layers 14 are divided into n rows, and each row includes ( ²ⁱ -1)*m/n polysilicon layers 14. The polysilicon layers 14 in adjacent rows are electrically connected through the second matching unit, and the polysilicon layers in the same row of the rest of the same resistor are electrically connected through the first matching unit. Therefore, the number of first matching units is mn, and the number of second matching units is n-1; the polysilicon layers in the same row include (mn)/n first matching units.

It should be further explained that, in the examples of FIG. 3 to FIG. 7 , for the convenience of illustration, the width of the polysilicon layer 14 is greater than the width of the first metal layer 11, and the widths of the first metal layer 11, the second metal layer 12, and the third metal layer 13 are all equal. In practical applications, the widths of the polysilicon layer 14, the first metal layer 11, and the third metal layer 13 are all equal, and the width of the second metal layer only needs to be able to cover the entire length of the polysilicon layer 14 in the length direction of the polysilicon layer 14 while satisfying the minimum spacing of the second metal layer.

In summary, the present embodiment discloses a resistor array structure of a DAC, comprising a plurality of polysilicon layers arranged in parallel to each other, a plurality of first metal layers arranged in parallel to each other, a plurality of second metal layers arranged in parallel to each other and a plurality of third metal layers arranged in parallel to each other; the polysilicon layers are arranged in at least one row; the lengths of the polysilicon layers are equal and arranged at the same intervals; the first metal layer is stacked on top of the polysilicon layer; the second metal layer is stacked on top of the first metal layer; the third metal layer is stacked on top of the second metal layer; the polysilicon layer, the first metal layer and the third metal layer have the same extension direction, and the extension direction of the second metal layer is perpendicular to the extension direction of the polysilicon layer; the resistor array structure comprises a plurality of resistors, each resistor is composed of a plurality of polysilicon layers electrically connected, and two adjacent polysilicon layers constituting the same resistor are electrically connected through a matching unit; the matching unit comprises a second matching metal layer and a third matching metal layer whose ends are electrically connected; wherein the second matching metal layer is the second metal layer constituting the matching unit in the second metal layer, and the third matching metal layer is the third metal layer constituting the matching unit in the third metal layer. The first metal layer on each polysilicon layer of the present embodiment is connected to a specific modulation potential. The reverse modulation effect of the first metal layer can reduce or offset the electrical deviation of the polysilicon resistor caused by the substrate, thereby achieving the purpose of stabilizing the resistance of the polysilicon resistor; the resistor array structure of the present embodiment is also provided with a suspended second metal layer and a third metal layer, and each suspended second metal layer and third metal layer is not connected to the second metal layer and the third metal layer in the matching unit, so that the metal layers above each polysilicon layer can be kept consistent, so that the temperature gradient distribution of the polysilicon layer constituting each resistor is uniform, and the routing distribution is uniform, so as to better ensure that the impedance of each resistor is matched and consistent; the resistor impedances of different matching paths in the same matching unit of the present embodiment are equal, so that the impedance of each resistor can be guaranteed to be consistent.

Although the embodiments or implementations are described and explained separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that the embodiments or implementations can be replaced and integrated between them. If one of the embodiments or implementations is not explicitly recorded, reference can be made to another recorded embodiment.

According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims (27)

1. A resistor array structure, characterized in that:

the semiconductor device comprises a plurality of polysilicon layers which are arranged in parallel, a plurality of first metal layers which are arranged in parallel, a plurality of second metal layers which are arranged in parallel and a plurality of third metal layers which are arranged in parallel; the polysilicon layer is arranged in at least one row;

The lengths of the polysilicon layers are equal, and the polysilicon layers are distributed at the same intervals; the first metal layer is laminated above the polysilicon layer; the second metal layer is laminated above the first metal layer; the third metal layer is laminated above the second metal layer; the extending directions of the polysilicon layer, the first metal layer and the third metal layer are the same, and the extending direction of the second metal layer is perpendicular to the extending direction of the polysilicon layer;

The resistor array structure comprises a plurality of resistors, each resistor is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching path in a matching unit; each matching unit comprises the matching paths with the same number of resistors; each matching path comprises a second matching metal layer and a third matching metal layer, wherein the ends of the second matching metal layer and the third matching metal layer are electrically connected; the second matching metal layer is a second metal layer forming a matching unit in the second metal layer, and the third matching metal layer is a third metal layer forming a matching unit in the third metal layer.

2. The resistor array structure of claim 1, wherein:

the first metal layer on the polysilicon layer is connected with a corresponding modulation potential to reduce the influence of the substrate voltage on the resistance value.

3. The resistor array structure of claim 2, wherein:

the first metal layers on the polysilicon layers forming the same resistor are connected with the same modulation potential.

4. A resistor array structure according to claim 3 wherein:

the same modulation potential is equal to the voltage at the input of the resistor.

5. The resistor array structure of claim 1, wherein:

when the polysilicon layers are distributed in the same row, the matching units comprise first matching units;

When the polysilicon layers are distributed in different rows, the matching unit comprises a first matching unit and a second matching unit; the first matching units are matching units for realizing electrical connection between the polysilicon layers in the same row, and the second matching units are matching units for realizing electrical connection between the polysilicon layers in different rows.

6. The resistor array structure of claim 5, wherein:

the number of the polysilicon layers positioned in the same row is 2k times of the number of the resistors, wherein k is any positive integer;

The polysilicon layers which are positioned in the same row and form the same resistor are electrically connected through 2k-1 first matching units.

7. The resistor array structure of claim 6, wherein:

k first matching units in the 2k-1 first matching units are located at the first side edge of a rectangular area, the other k-1 first matching units are located at the second side edge of the rectangular area, the rectangular area is an area formed by a polycrystalline silicon layer located in the same row, and the first side and the second side are opposite and located at two ends of the polycrystalline silicon layer respectively.

8. The resistor array structure of claim 5, wherein:

When the polysilicon layers are distributed in different rows, the number of polysilicon layers in each row is equal.

9. The resistor array structure of claim 5, wherein:

The first matching unit is symmetrical about a symmetry axis, and two polysilicon layers electrically connected through a matching path in the first matching unit are positioned at two sides of the symmetry axis and are axisymmetrical;

Each matching path of the first matching unit comprises two third matching metal layers and one second matching metal layer, the two third matching metal layers are located on two sides of the symmetrical axis and are axisymmetric, two ends of the second matching metal layers are respectively and electrically connected with one end of the two third matching metal layers, and the other ends of the two third matching metal layers are respectively and electrically connected with two axisymmetric polysilicon layers.

10. The resistor array structure of claim 1, wherein:

The third matching metal layer is connected with the second matching metal layer through the first type through hole; wherein the first type of via is a via that enables electrical connection between the second metal layer and the third metal layer.

11. The resistor array structure of claim 10, wherein:

the second suspended metal layer is disconnected from the second matching metal layer near the first type through hole, wherein the second suspended metal layer is a second metal layer which is not connected with any potential in the second metal layer and is not connected with the first metal layer, the third metal layer or the polycrystalline silicon layer;

And the third suspended metal layer is disconnected from the third matching metal layer near the first type through hole, wherein the third suspended metal layer is a third metal layer which is not connected with any potential in the third metal layer and is not connected with the first metal layer, the second metal layer or the polycrystalline silicon layer.

12. The resistor array structure of claim 10, wherein:

The first type through holes in the same first matching unit are in isosceles arrangement, so that the lengths of the second matching metal layers in the matching paths in the same first matching unit are in an arithmetic progression.

13. The resistor array structure of claim 7, wherein:

The lengths of the second matching metal layers in the matching paths in the same first matching unit are in equal difference increment to the edge, parallel to the first direction, of the rectangular area; wherein the first direction is a direction parallel to the extending direction of the second metal layer.

14. The resistor array structure of claim 9, wherein:

Each polycrystalline silicon layer is connected with the third matching metal layer through a second type through hole positioned at the end part of the polycrystalline silicon layer, wherein the second type through hole is a through hole for electrically connecting the polycrystalline silicon layer and the third matching metal layer.

15. The resistor array structure of claim 9, wherein:

Each first metal layer connected to a modulation potential is disconnected in the vicinity of the second type via, and the length of each first metal layer connected to a modulation potential is smaller than the length of the polysilicon layer, so that no electrical connection exists between the second type via and the first metal layer connected to a modulation potential.

16. The resistor array structure of claim 5, wherein:

When the number of the polysilicon layers forming the same resistor in the same row is greater than 2, two first matching units connected with the same polysilicon layer are respectively distributed at two ends of the polysilicon layer.

17. The resistor array structure of claim 5, wherein:

and the resistance values of the matching paths in the first matching unit are equal.

18. The resistor array structure of claim 17, wherein:

the lengths of the matching paths in the first matching unit are equal.

19. The resistor array structure of claim 5, wherein:

The second matching unit comprises matching paths positioned above the rectangular area and matching paths positioned outside the rectangular area, wherein the resistance values of the matching paths positioned above the rectangular area in each matching path are equal; the rectangular region is a region formed by the polysilicon layers in the same row.

20. The resistor array structure of claim 19, wherein:

the lengths of the respective matching paths located above the rectangular region in the second matching unit are equal.

21. The resistor array structure of claim 19, wherein:

and the resistance values of the matching paths outside the rectangular area in the second matching unit are equal.

22. The resistor array structure of claim 19, wherein:

And the lengths of the matching paths outside the rectangular area in each matching path in the second matching unit are equal.

23. The resistor array structure of claim 7, wherein:

When the number of the polysilicon layers forming the same resistor in the same row is greater than 2, a spacing area is further arranged between the first matching units positioned at the first side edge and the second side edge of the rectangular area along the length direction of the polysilicon layers, and the spacing area comprises second spacing metal layers with the number equal to that of the resistors;

the first metal layers on the polysilicon layers forming the same resistor are electrically connected with the same second interval metal layer, and the second interval metal layer is the second metal layer positioned in the interval region.

24. The resistor array structure of claim 23, wherein:

and third modulation metal layers with the number equal to that of resistors are arranged on two sides or one side of the rectangular area and are used for being electrically connected with the second interval metal layers respectively.

25. The resistor array structure of claim 1, wherein:

Virtual resistors are further arranged on two sides of a rectangular area formed by the polycrystalline silicon layers in the same row, and each virtual resistor comprises a polycrystalline silicon layer, a first metal layer and a third metal layer.

26. The resistor array structure of claim 25, wherein:

The virtual resistor further includes a second metal layer.

27. The resistor array structure of claim 26, wherein:

The polysilicon layer forming the virtual resistor and the first metal layer forming the virtual resistor are connected with ground potential, the second metal layer forming the virtual resistor and the third metal layer forming the virtual resistor are arranged in a suspending mode, and no potential is connected.