CN117936539A - Resistor array structure - Google Patents

Resistor array structure Download PDF

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Publication number
CN117936539A
CN117936539A CN202311449776.7A CN202311449776A CN117936539A CN 117936539 A CN117936539 A CN 117936539A CN 202311449776 A CN202311449776 A CN 202311449776A CN 117936539 A CN117936539 A CN 117936539A
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China
Prior art keywords
matching
metal layer
layers
resistor
polysilicon
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CN202311449776.7A
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Chinese (zh)
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魏亚丽
姚锋鹏
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Hangzhou Silergy Semiconductor Technology Ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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Priority to CN202311449776.7A priority Critical patent/CN117936539A/en
Publication of CN117936539A publication Critical patent/CN117936539A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The embodiment of the invention discloses a resistor array structure, which comprises a plurality of polysilicon layers, a plurality of first metal layers, a plurality of second metal layers and a plurality of third metal layers; each resistor in the resistor array structure is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching unit, and the resistance and the impedance of different matching paths in the same matching unit are equal; the first metal layer on each polysilicon layer is connected with a specific modulation potential, so that the purpose of stabilizing the resistance value of the polysilicon is achieved; the resistor array structure is also provided with a second suspended metal layer and a third suspended metal layer, so that the metal layers above the polysilicon layers can be ensured to be consistent, and the temperature gradient distribution of the polysilicon layers forming each resistor is uniform.

Description

Resistor array structure
Technical Field
The invention relates to the technical field of microelectronics, in particular to a resistor array structure.
Background
Digital-to-analog converters (DACs) are used as a ligament in the digital and analog domains and are widely used in electronic products, while high-precision DACs play an extremely important role in the high-resolution digital-to-analog conversion process, and the quality of resistance matching performance is very important. As shown in fig. 1, the 3-bit thermometer code DAC structure (shown in fig. 1) is provided, wherein the resistors U0 to U6 are matched and equal to each other. The common resistor array is shown in fig. 2, the resistors U0 to U6 are sequentially arranged in sequence, fine matching is not performed, the occupied layout area is large, the power loss is serious, the noise is increased, the signal to noise ratio is reduced, the sensitivity of the circuit is affected, and the frequency response is uneven. Therefore, the high-precision resistor module is particularly important for obtaining stable performance indexes and long service life, and the theoretical performance of the circuit components can be better exerted only through reasonable matching.
Disclosure of Invention
In view of the above, the invention provides a layout design of a resistor array structure to solve the technical problems caused by the fact that resistors cannot be finely matched in the prior art.
The embodiment of the invention provides a resistor array structure, which comprises a plurality of polysilicon layers, a plurality of first metal layers, a plurality of second metal layers and a plurality of third metal layers, wherein the polysilicon layers are arranged in parallel with each other; the polysilicon layer is arranged in at least one row; the lengths of the polysilicon layers are equal, and the polysilicon layers are distributed at the same intervals; the first metal layer is laminated above the polysilicon layer; the second metal layer is laminated above the first metal layer; the third metal layer is laminated above the second metal layer; the extending directions of the polysilicon layer, the first metal layer and the third metal layer are the same, and the extending direction of the second metal layer is perpendicular to the extending direction of the polysilicon layer; the resistor array structure comprises a plurality of resistors, each resistor is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching path in a matching unit; each matching unit comprises the matching paths with the same number of resistors; each matching path comprises a second matching metal layer and a third matching metal layer, wherein the ends of the second matching metal layer and the third matching metal layer are electrically connected; the second matching metal layer is a second metal layer forming a matching unit in the second metal layer, and the third matching metal layer is a third metal layer forming a matching unit in the third metal layer.
Preferably, the first metal layer on the polysilicon layer is connected with a corresponding modulation potential to reduce the influence of the substrate voltage on the resistance value.
Preferably, the first metal layers on the plurality of polysilicon layers constituting the same resistor are connected to the same modulation potential.
Preferably, the same modulation potential is equal to the voltage at the input of the resistor.
Preferably, when the polysilicon layers are distributed in the same row, the matching unit includes a first matching unit; when the polysilicon layers are distributed in different rows, the matching units comprise a first matching unit and a second matching unit, wherein the first matching unit is a matching unit for realizing electric connection between the polysilicon layers in the same row, and the second matching unit is a matching unit for realizing electric connection between the polysilicon layers in different rows.
Preferably, the number of the polysilicon layers positioned in the same row is 2k times of the number of the resistors, wherein k is any positive integer; the polysilicon layers which are positioned in the same row and form the same resistor are electrically connected through 2k-1 first matching units.
Preferably, k first matching units in the 2k-1 first matching units are located at a first side edge of a rectangular area, the other k-1 first matching units are located at a second side edge of the rectangular area, the rectangular area is an area formed by a polysilicon layer located in the same row, and the first side and the second side are opposite and located at two ends of the polysilicon layer respectively.
Preferably, when the polysilicon layers are distributed in different rows, the number of polysilicon layers in each row is equal.
Preferably, the first matching unit is symmetrical about a symmetry axis, and the two polysilicon layers electrically connected through the matching paths in the first matching unit are located at two sides of the symmetry axis and are axisymmetrical;
Each matching path of the first matching unit comprises two third matching metal layers and one second matching metal layer, the two third matching metal layers are located on two sides of the symmetrical axis and are axisymmetric, two ends of the second matching metal layers are respectively and electrically connected with one end of the two third matching metal layers, and the other ends of the two third matching metal layers are respectively and electrically connected with two axisymmetric polysilicon layers.
Preferably, the third matching metal layer and the second matching metal layer are connected through a first type through hole; wherein the first type of via is a via that enables electrical connection between the second metal layer and the third metal layer.
Preferably, a second suspended metal layer is disconnected from the second matching metal layer near the first type through hole, wherein the second suspended metal layer is a second metal layer which is not connected with any potential in the second metal layer, and is not connected with the first metal layer, the third metal layer or the polysilicon layer;
And the third suspended metal layer is disconnected from the third matching metal layer near the first type through hole, wherein the third suspended metal layer is a third metal layer which is not connected with any potential in the third metal layer and is not connected with the first metal layer, the second metal layer or the polycrystalline silicon layer.
Preferably, the first type of through holes in the same first matching unit exhibit an isosceles arrangement, i.e. the lengths of the second matching metal layers in the respective matching paths in the same first matching unit are in an arithmetic progression.
Preferably, the lengths of the second matching metal layers in the respective matching paths in the same first matching unit are in equal differential increment to the edges parallel to the first direction, which are close to the rectangular area; wherein the first direction is a direction parallel to the extending direction of the second metal layer.
Preferably, each polysilicon layer is connected to the third matching metal layer through a second type via located at an end of the polysilicon layer, where the second type via is a via electrically connected between the polysilicon layer and the third matching metal layer.
Preferably, each first metal layer connected to the modulation potential is disconnected in the vicinity of the second type via, and the length of each first metal layer connected to the modulation potential is smaller than the length of the polysilicon layer, so that there is no electrical connection between the second type via and the first metal layer connected to the modulation potential.
Preferably, when the number of polysilicon layers constituting the same resistor in the same row is greater than 2, two first matching units connected to the same polysilicon layer are respectively distributed at both ends of the polysilicon layer.
Preferably, the resistances of the respective matching paths in the first matching unit are equal.
Preferably, lengths of the respective matching paths in the first matching unit are equal.
Preferably, the second matching unit includes a matching path located above the rectangular area and a matching path located outside the rectangular area, wherein the resistance values of the matching paths located above the rectangular area in the respective matching paths are equal; the rectangular region is a region formed by the polysilicon layers in the same row.
Preferably, lengths of respective matching paths located above the rectangular region in the second matching unit are equal.
Preferably, the resistances of the matching paths in the second matching unit located outside the rectangular area are equal.
Preferably, lengths of matching paths located outside the rectangular area in the respective matching paths in the second matching unit are equal.
Preferably, when the number of polysilicon layers constituting the same resistor in the same row is greater than 2, a spacing region is further provided between the first matching units located at the first side edge and the second side edge of the rectangular region in the length direction of the polysilicon layers, the spacing region including a second spacing metal layer equal to the number of resistors;
the first metal layers on the polysilicon layers forming the same resistor are electrically connected with the same second interval metal layer, and the second interval metal layer is the second metal layer positioned in the interval region.
Preferably, third modulating metal layers with the same number as the resistors are further arranged on two sides or one side of the rectangular area and are used for being electrically connected with the second interval metal layers respectively.
Preferably, virtual resistors are further arranged on two sides of a rectangular area formed by the polycrystalline silicon layers in the same row, and each virtual resistor comprises the polycrystalline silicon layer, the first metal layer and the third metal layer.
Preferably, the virtual resistor further comprises a second metal layer.
Preferably, the polysilicon layer forming the virtual resistor and the first metal layer forming the virtual resistor are connected with ground potential, the second metal layer forming the virtual resistor and the third metal layer forming the virtual resistor are suspended, and no potential is connected.
Compared with the prior art, the invention adopts the common centroid matching mode of the upgrade version, and has the following advantages:
1. The first metal layer on each polysilicon layer forming the resistor is connected with a specific modulation potential, and the electric deviation of the resistance value of the polysilicon resistor caused by the substrate can be reduced or offset by utilizing the reverse modulation action of the first metal layer, so that the purpose of stabilizing the resistance value of the polysilicon resistor is achieved;
2. The resistor array structure is also provided with a second suspended metal layer and a third suspended metal layer, and each second suspended metal layer and each third suspended metal layer are not connected with the second matched metal layer and the third matched metal layer, so that the metal layers above each polysilicon layer can be ensured to be consistent, the temperature gradient distribution of the polysilicon layers forming each resistor is uniform, the wiring distribution is uniform, and the impedance matching consistency of each resistor is better ensured;
3. the resistances and the impedances of different matching paths in the same matching unit are equal, so that the impedance of each resistor is consistent;
4. The endpoints of the second matching metal layer and the third matching metal layer in the first matching unit are cut off near the through holes of the first type, so that the influence of the parasitic capacitance caused by resistance matching, which is caused by the fact that the second matching metal layer and the third matching metal layer are not cut off near the through holes of the first type, is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a prior art digital-to-analog converter;
FIG. 2 is a schematic diagram of a prior art resistor array structure;
FIG. 3 is a first schematic diagram of a resistor array structure according to the present embodiment;
Fig. 4 is an enlarged view of the vicinity of the second type via hole of the resistor array structure in the present embodiment;
Fig. 5 is a schematic diagram of a matching unit in the present embodiment;
FIG. 6 is a second schematic diagram of the resistor array structure in the present embodiment;
fig. 7 is an enlarged schematic diagram of the second matching unit in fig. 6 in the present embodiment.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
The embodiment discloses a resistor array structure of a DAC, which comprises a plurality of polysilicon layers which are arranged in parallel, a plurality of first metal layers which are arranged in parallel, a plurality of second metal layers which are arranged in parallel and a plurality of third metal layers which are arranged in parallel; the polysilicon layer is arranged in at least one row; insulating medium isolation layers are respectively arranged between the polysilicon layer and the first metal layer, between the first metal layer and the second metal layer and between the second metal layer and the third metal layer; the lengths of the polysilicon layers are equal, and the polysilicon layers are distributed at the same intervals; the first metal layer is laminated above the polysilicon layer; the second metal layer is laminated above the first metal layer; the third metal layer is laminated above the second metal layer; the polysilicon layers of the composition resistors arranged in the same row are sequentially arranged in parallel in a rectangular area at the same interval, and the lengths and the widths of the first metal layers are the same; the second metal layer and the first metal layer are vertically arranged, and the third metal layer and the second metal layer are vertically arranged. The polysilicon layer, the first metal layer, and the third metal layer overlap in the direction of lamination.
The resistor array structure comprises a plurality of resistors, each resistor is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching path in a matching unit, so that the plurality of polysilicon layers forming the same resistor can be electrically connected; the matching unit comprises a second matching metal layer and a third matching metal layer, wherein the end parts of the second matching metal layer and the third matching metal layer are electrically connected; the second matching metal layer is a second metal layer forming a matching unit in the second metal layer, and the third matching metal layer is a third metal layer forming a matching unit in the third metal layer.
The matching units comprise a first matching unit and a second matching unit, the first matching unit is a matching unit for realizing electric connection between the polysilicon layers positioned in the same row, and the second matching unit is a matching unit for realizing electric connection between the polysilicon layers positioned in different rows. Each matching unit comprises matching paths with the same number as the resistors, and the resistance values of the matching paths in the same matching unit are the same.
The number of the polysilicon layers positioned in the same row is even times of the number of the resistors, namely the number of the polysilicon layers positioned in the same row is 2k times of the number of the resistors, wherein k is any positive integer; the polysilicon layers which are positioned in the same row and form the same resistor are electrically connected through 2k-1 first matching units. The k first matching units in the 2k-1 first matching units are located at the first side edge of a rectangular area, the other k-1 first matching units are located at the second side edge of the rectangular area, the rectangular area is an area formed by a polycrystalline silicon layer located in the same row, and the first side and the second side are opposite and located at two ends of the polycrystalline silicon layer respectively.
In order to symmetrically arrange the wirings (the first metal layer, the second metal layer, and the third metal layer) on the polysilicon layers in the same row, the number of polysilicon layers in the same row is set to be even.
As an example, fig. 3 is a schematic diagram of a resistor array structure of a 3bit DAC, and 2 3 -1=7 resistors in total: u0, U1, U2, U3, U4, U5 and U6, each resistor is formed by connecting 4 polysilicon layers 14, two adjacent polysilicon layers 14 forming the same resistor are connected through one matching path in the first matching unit, and all polysilicon layers 14 are arranged in a row side by side, so the resistor array structure comprises 3 first matching units: the first matching unit 1, the first matching unit 2 and the first matching unit 3, each polysilicon layer 14 establishes connection with the third matching metal layer 13 in the first matching unit through the second type through hole Via3p, that is, the polysilicon layer 14 establishes connection with the first matching unit through the second type through hole Via3p, so that the polysilicon layers 14 are connected through the first matching unit. As shown in FIG. 3, the resistor U0 is formed by electrically connecting four polysilicon layers U0<0>, U0<1>, U0<2> and U0<3>, the resistor U1 is formed by electrically connecting four polysilicon layers U1<0>, U1<1>, U1<2> and U1<3>, the resistor U2 is formed by electrically connecting four polysilicon layers U2<0>, U2<1>, U2<2> and U2<3>, the resistor U3 is formed by electrically connecting four polysilicon layers U3<0>, U3<1>, U3<2> and U3<3>, the resistor … … is formed by electrically connecting four polysilicon layers U6<0>, U6<1>, U6<2> and U6<3>, wherein the connection between U0<0> and U0 > is established by one of the matching paths in the first matching unit 1, the connection between U0<1> and U0<2> is established by one of the matching paths in the first matching unit 2 and the matching unit 0 by one of the matching paths in the first matching unit 2 and the matching unit 3; seven matching paths in the first matching unit 1 establish electrical connections between U0<0> and U0<1>, between U1<0> and U1<1>, between U2<0> and U2<1>, … … U6<0> and U6<1>, respectively, and seven matching paths in the first matching unit 2 establish electrical connections between U0<1> and U0<2>, between U1<1> and U1<2>, between U2<1> and U2<2>, … … U6<1> and U6<2>, respectively; seven matching paths in the first matching unit 3 establish electrical connections between U0<2> and U0<3>, between U1<2> and U1<3>, between U2<2> and U2<3>, … … U6<2> and U6<3>, respectively. Wherein one end of U0<0>, U1<0>, U2<0>, U3<0>, U4<0>, U5<0> and U6<0> is used as an input end, and the other end is connected with the first matching unit 1; one end of U0<1>, U1<1>, U2<1>, U3<1>, U4<1>, U5<1> and U6<1> is connected with the first matching unit 1, and the other end is connected with the first matching unit 2; one end of U0<2>, U1<2>, U2<2>, U3<2>, U4<2>, U5<2> and U6<2> is connected with the first matching unit 2, and the other end is connected with the first matching unit 3; one end of U0<3>, U1<3>, U2<3>, U3<3>, U4<3>, U5<3> and U6<3> is connected with the first matching unit 3, and the other end is taken as an output end Vout.
The connection paths of the resistors are described below with reference to fig. 3, taking the resistor U0 as an example, and include U0<0>, U0<1>, U0<2> and U0<3> electrically connected in this order. The input end of the resistor U0 is connected with SW0 through one end of U0<0 >; the other end of U0<0> is connected with a third matching metal layer in a matching path of the first matching unit 1 through a second type through hole Via3p, and one end of the other third matching metal layer in the matching path is connected with one end of U0<1> through the second type through hole Via3 p; the other end of U0<1> is connected with a third matching metal layer in a matching path in the first matching unit 2 through a second type through hole Via3p, and one end of the other third matching metal layer in the matching path is connected with one end of U0<2> through the second type through hole Via3 p; the other end of U0<2> is connected with a third matching metal layer in a matching path in the first matching unit 3 through a second type through hole Via3p, one end of the other third matching metal layer in the matching path is connected with one end of U0<3> through a second type through hole Via3p, and the other end of U0<3> is output as an output end Vout.
As can be seen from fig. 3, one of the first matching units 2 is located at a first side edge of a rectangular area, wherein 2 first matching units (the first matching unit 1 and the first matching unit 3) are located at a second side edge of the rectangular area, and the rectangular area is an area formed by polysilicon layers located in the same row, and the first side and the second side are opposite and are respectively located at two ends of the polysilicon layer 14.
As shown in fig. 4, which is an enlarged view of the vicinity of the second type Via hole Via3p in fig. 3, it can be seen from fig. 4 that the length of each first metal layer 11 connected to the modulation potential is smaller than the length of the polysilicon layer 14, and the first metal layers 11 are disconnected in the vicinity of the second type Via hole Via3p, so that the second type Via hole Via3p is not electrically connected to each first metal layer 11 connected to the modulation potential.
As shown in fig. 5, each first matching unit is an axisymmetric pattern (the direction of the symmetry axis Z L is the trend of the first metal layer 11/polysilicon layer 14), two polysilicon layers electrically connected by the matching path in the first matching unit are located at two sides of the symmetry axis and are axisymmetric, that is, U0<0> and U0<1> are symmetric about the symmetry axis Z L, U1<0> and U1<1> are symmetric about the symmetry axis Z L, U2<0> and U2<1> are symmetric about the symmetry axis Z L, U3<0> and U3<1> are symmetric about the symmetry axis Z L, U4<0> and U4<1> are symmetric about the symmetry axis Z L, U5<0> and U5<1> are symmetric about the symmetry axis Z L, and U6<0> and U6<1> are symmetric about the symmetry axis Z L. Each first matching unit comprises matching paths with the same number as the resistors, each matching path comprises two axisymmetric third matching metal layers 131 positioned on two sides of the symmetry axis, and a second matching metal layer 121 connected with the two axisymmetric third matching metal layers 131. Two third matching metal layers forming each matching path are located on two sides of the symmetry axis and are axisymmetric, two ends of each second matching metal layer are respectively and electrically connected with one end of each third matching metal layer, and the other ends of each third matching metal layer are respectively and electrically connected with two axisymmetric polysilicon layers. Two symmetrical third matching metal layers 131 positioned on two sides of the symmetry axis Z L are connected with one second matching metal layer 121 through a first type through hole Via 23; as can be seen from fig. 5, the resistance values formed by connecting the two symmetrical second matching metal layers 121 located on both sides of the symmetry axis in series with the third matching metal layer 131 connected thereto in each first matching unit are equal, so that each matching path in each first matching unit can be matched. As an example, in the present embodiment, the widths of all the second metal layers 12 and all the third metal layers 13 are equal, and the lengths of the respective matching paths are equal, that is, the sum of the lengths of the two mutually symmetrical third matching metal layers 131 in each matching path and the second matching metal layer 121 connected thereto is equal. As shown in fig. 5, the matching paths L0 connecting U0<0> and U0<1> and the matching paths L6 connecting U6<0> and U6<1> are shown, the lengths of L0 and L6 are equal, and the resistances of the matching paths L0 and L6 are equal.
As shown in fig. 3 and fig. 5, the resistor array structure is further provided with a second suspended metal layer 122 and a third suspended metal layer 132, the second suspended metal layer 122 is disconnected from the second matching metal layer 121 near the first type Via23, the third suspended metal layer 132 is disconnected from the third matching metal layer 131 near the first type Via23, the second suspended metal layer 122 is a second metal layer which is not connected with any electric potential, is not connected with the first metal layer, the third metal layer or the polysilicon layer, and the third suspended metal layer 132 is a metal layer which is not connected with any electric potential, is not connected with the first metal layer, the second metal layer or the polysilicon layer, so that the metal layers above the polysilicon layers 14 can be ensured to be kept consistent, the temperature gradient distribution of the polysilicon layers 14 forming the resistors is uniform, and the distribution of the wires is ensured to be even, so that the impedance matching of the resistors is better ensured. The end points of the second matching metal layer 121 and the third matching metal layer 131 in each matching unit are arranged near each first type through hole Via23, so that the influence of the parasitic capacitance caused by resistance matching caused by the fact that the second metal layer 12 and the third metal layer 13 are not cut off near each first type through hole Via23 is reduced; that is, the second suspended metal layers 122 and the second matching metal layers 121 in the matching unit are disconnected by a smaller distance in the vicinity of the first type through holes Via23 connected with the second matching metal layers 121 and the third matching metal layers 131 in the connecting matching path, and the third suspended metal layers 132 and the third matching metal layers 131 in the matching path are disconnected by a smaller distance in the vicinity of the first type through holes Via23 connected with the second matching metal layers 121 and the third matching metal layers 131 in the connecting matching path, so that the uniform distribution of the metals of each layer is ensured to the greatest extent, the uniform distribution of the metal layers on each polysilicon layer 14 is ensured, and the uniform distribution of the temperature gradients is ensured.
As shown in fig. 5, the first type vias Via23 in each first matching unit exhibit isosceles arrangement, the number is 2 times the number of resistors, that is, the number is 14, and the symmetrical arrangement is exhibited at both sides of the symmetry axis Z L. The lengths of the second matching metal layers 121 in the same first matching unit are represented as an arithmetic progression, and the arithmetic progression is represented in a direction approaching the edge of the rectangular region parallel to the first direction (also in a direction approaching the second type Via3p where the polysilicon layer 14 is electrically connected to the third matching metal layer 131 in the matching unit), so that the shorter the length of the third matching metal layer 131 approaching the edge of the rectangular region (also approaching the second type Via3 p), the longer the length of the second matching metal layer 121 electrically connected thereto; wherein the first direction is a direction parallel to the extending direction of the second metal layer.
When the number of polysilicon layers forming the same resistor in the same row is greater than 2, two first matching units connected with the same polysilicon layer 14 are respectively distributed at two ends of the polysilicon layer 14, namely, near two parallel edges of the rectangular region. That is, as shown in fig. 3, each resistor is formed by connecting 4 polysilicon layers 14, two ends of the polysilicon layers U0<1> to U6<1> are respectively connected with the first matching unit 1 and the first matching unit 2, and two ends of the polysilicon layers U0<2> to U6<2> are respectively connected with the first matching unit 2 and the first matching unit 3; the first matching unit 1 and the first matching unit 3 are in an inverted triangle shape and are close to the upper edge of the rectangular area; the first matching unit 2 appears as a right triangle near the lower edge of a rectangular region formed by polysilicon layers located in the same row.
As shown in fig. 3, when the number of polysilicon layers in the same row for forming the same resistor is greater than 2, a spacing region 15 is further disposed between two matching units connected to the same polysilicon layer 14 along the length direction of the polysilicon layer 14, that is, a spacing region is further disposed between the first matching units located at the first side edge and the second side edge of the rectangular region, the spacing region 15 includes a second spacing metal layer 123 equal to the number of resistors, and the second spacing metal layer 123 is a second metal layer located in the spacing region; wherein each second spacer metal layer 123 having the same number of resistors in the spacer region is electrically connected to the first metal layer 11 on each polysilicon layer 14 constituting the same resistor; specifically, electrical connection is made through the third type Via 12; the third type Via hole Via12 is a Via hole for electrically connecting the first metal layer 11 and the second metal layer 12. As shown in fig. 3, two matching units connected to the same polysilicon layer 14 are spaced apart from 7 second spaced apart metal layers 123 of the same number as the resistors in the direction along the length of the polysilicon layer 14, each second spaced apart metal layer 123 being connected to 4 first metal layers 11 on 4 polysilicon layers 14 constituting the same resistor through 4 third type vias Via 12; each second interval metal layer 123 is connected with one third modulation metal layer 133 through one first type through hole Via23, the first type through hole Via23 connected with the second interval metal layer 123 and the third modulation metal layer 133 is positioned outside a rectangular area formed by arrangement of the polysilicon layers 14, each third modulation metal layer 133 is connected with one corresponding modulation potential Vuo-Vu 6, the modulation potential corresponds to the voltage of the input end of each resistor, and the third modulation metal layer 133 is a metal layer connected with the modulation potential in the third metal layer; specifically, as shown in fig. 3, in this embodiment, the input end of each resistor is a port where the polysilicon layers U0<0> to U0<6> are connected to the switching transistors SW0 to SW6, i.e. the voltage at the input end of each resistor corresponds to the voltage at the port labeled SW0 to SW6 in the figure. The output ports of the resistors are the ports electrically connected to each other by polysilicon layers U0<3> to U6<3>, i.e., the ports identified as VOUT in FIG. 3.
As shown in fig. 3, 7 third modulating metal layers 133 connecting modulating potentials Vuo to Vu6 are located on both sides of the rectangular region; in other embodiments, the third modulating metal layer 133 connected to the modulating potential may be located on the same side of the rectangular area, and the two matching units connected to the same polysilicon layer 14 may be separated by the second spacer metal layer 123 greater than the number of resistors in the direction along the length of the polysilicon layer 14, which is not limited herein, and may be flexibly set according to specific applications and layout designs.
In this embodiment, the polysilicon layer 14 is used as the resistor, and the polysilicon layer 14 has carriers therein, so that when the resistor is affected by the electric field of the substrate, the distribution of carriers in the resistor is changed, the resistance value is slightly changed, and the resistance value changes more significantly as the electric field is stronger. In this embodiment, the first metal layer 11 on each polysilicon layer 14 is connected to a specific modulation voltage, and the electrical deviation of the polysilicon resistance caused by the substrate can be reduced or offset by using the reverse modulation effect of the first metal layer 11, so as to achieve the purpose of stabilizing the polysilicon resistance.
As shown in fig. 3, polysilicon layer 14, first metal layer 11 and third metal layer 13 are further disposed on the left and right sides of the rectangular region, and serve as a dummy resistor, so that deviation of the resistance caused by the chip process can be relieved. In other embodiments, virtual resistors may be disposed around the rectangular area, and virtual (dummy) resistors may be disposed above or below the rectangular area, and the number and shape of the dummy resistors are not limited. In other embodiments, a second metal layer may also be disposed between the first metal layer and the second metal layer that act as virtual resistances; as an example, the polysilicon layer 14 serving as a dummy resistor and the first metal layer serving as a dummy resistor are connected and connected to the ground potential, and the second metal layer serving as a dummy resistor and the third metal layer serving as a dummy resistor are provided in a floating manner.
The embodiment shown in fig. 3 is exemplified by 3 bits, and 2 3 -1=7 resistors are totally formed by connecting 4 polysilicon layers 14, all the polysilicon layers are distributed in one row, in other embodiments, any ibit (i is a positive integer), the number of corresponding resistors is 2 i -1, the number of polysilicon layers 14 forming each resistor can be set according to specific requirements, all the polysilicon layers can be distributed in multiple rows, and when the polysilicon layers are distributed in different rows, the number of polysilicon layers in each row is equal.
As shown in fig. 6, the polysilicon layer 14 is arranged in a plurality of rows. Taking 3bit as an example, the resistor comprises 2 3 -1=7 resistors, each resistor is formed by connecting 8 polysilicon layers 14, 7*8 =56 polysilicon layers 14 are divided into two rows of arrangement, each row comprises 7*4 =28 polysilicon layers 14, the polysilicon layers 14 in the same row are electrically connected through first matching units, and the polysilicon layers 14 in the same row comprise 3 first matching units. As shown in fig. 6, the first matching unit 1, the first matching unit 2 and the first matching unit 3 are included on the polysilicon layer of the lower row, the first matching unit 5, the first matching unit 6 and the first matching unit 7 are included on the polysilicon layer of the upper row, and the electrical connection is performed between the U0<3> to U6<3> and the U0<4> to U6<4> of different rows through the second matching unit 4. The second matching unit is identical to the first matching unit and comprises 7 matching paths with the same number of resistors. As shown in fig. 6, as an example, each of the matching paths of the second matching unit 4 includes 3 third matching metal layers 131 and 2 second matching metal layers 121, and each of the matching paths of the second matching unit 4 is composed of the second matching metal layers 121 and the third matching metal layers 131 alternately connected. As shown in fig. 6, the second matching unit 4 is divided into three parts: 41. 42 and 43, wherein 41,43 are located above the rectangular area, and 42 is located outside the rectangular area and between 41 and 43 for connecting 41 and 43. As the embodiment shown in fig. 6, the matching path resistances above the rectangular area in each matching path in the second matching unit 4 are equal due to the limitation of space; preferably, the lengths of the matching paths located above the rectangular area in each matching path are equal, i.e. the sum of the lengths in 41 and 43, which constitute the same matching path, between different matching paths is equal; as shown in fig. 6 and 7, the lengths of the different matching paths located in 42 are in an arithmetic progression, so that the lengths of the respective matching paths of the second matching unit 4 are in an arithmetic progression. As shown in fig. 7, which is an enlarged view of the second matching unit in fig. 6, two matching paths in 41,43 are shown in fig. 7, which are located above a rectangular area, wherein the sum of the lengths of L01, L02 is equal to the sum of the lengths of L61, L62, and the lengths of the different matching paths in 42 are equal difference columns. In addition, a spacer region is included on the polysilicon layer 14 of each row, the spacer region includes a number of second spacer metal layers 123 equal to the resistance, and each second spacer metal layer 123 is electrically connected to a corresponding third modulation metal layer 133.
It should be noted that, preferably, the impedance of each matching path of the second matching unit 4 is equal, and the corresponding lengths are also equal. Fig. 6 shows an arithmetic series of the lengths of each matching path due to space limitation, and as another embodiment, the lengths of each matching path in the second matching unit 4 can be equal by equalizing the lengths of each matching path in the 42 by adding bends to the shorter matching path in the 42, so that the lengths of the corresponding impedances are also equal. As shown in fig. 6, the polysilicon layer 14 of each row of the composition resistor further includes polysilicon layers serving as dummy resistors, and the lengths of L01, L02, L61, and L62 in fig. 6 and 7 each include lengths over the polysilicon layers serving as dummy resistors, but since the lengths of L01 and L02, or L61 and L6, are equal over the polysilicon layers serving as dummy resistors, the sum of the lengths of L01 and L02 over the rectangular areas of the composition resistor is also equal to the sum of the lengths of L61 and L62 over the rectangular areas of the composition resistor. The shape of the matching paths of the second matching unit and the number of the included metal layers include, but are not limited to, those shown in fig. 6 and fig. 7, so that the matching paths with the impedance differences corresponding to the matching paths within an acceptable range can be ensured to be all the protection ranges of the present invention.
For example, taking ibit as an example, the resistor comprises 2 i -1 resistors, when each resistor is formed by connecting m polysilicon layers 14, the number of the polysilicon layers is (2 i -1) ×m, all the polysilicon layers 14 are divided into n rows, each row comprises (2 i -1) ×m/n polysilicon layers 14, the polysilicon layers 14 in adjacent rows are electrically connected through second matching units, and the polysilicon layers in the same row of the other same resistors are electrically connected through first matching units, so that the number of the first matching units is m-n, and the number of the second matching units is n-1; the first matching units (m-n)/n are arranged on the polysilicon layer in the same row.
In the examples of fig. 3 to 7, the width of the polysilicon layer 14 is larger than the width of the first metal layer 11, and the widths of the first metal layer 11, the second metal layer 12, and the third metal layer 13 are all equal for convenience of illustration. In practical applications, the widths of the polysilicon layer 14, the first metal layer 11 and the third metal layer 13 are all equal, and the width of the second metal layer is enough to satisfy the length of the polysilicon layer 14 in the length direction of the polysilicon layer 14 and to fully spread the length of the polysilicon layer 14 on the basis of satisfying the minimum pitch of the second metal layer.
In summary, the present embodiment discloses a resistor array structure of a DAC, including a plurality of polysilicon layers disposed parallel to each other, a plurality of first metal layers disposed parallel to each other, a plurality of second metal layers disposed parallel to each other, and a plurality of third metal layers disposed parallel to each other; the polysilicon layer is arranged in at least one row; the lengths of the polysilicon layers are equal, and the polysilicon layers are distributed at the same intervals; the first metal layer is laminated above the polysilicon layer; the second metal layer is laminated above the first metal layer; the third metal layer is laminated above the second metal layer; the extending directions of the polysilicon layer, the first metal layer and the third metal layer are the same, and the extending direction of the second metal layer is perpendicular to the extending direction of the polysilicon layer; the resistor array structure comprises a plurality of resistors, each resistor is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching unit; the matching unit comprises a second matching metal layer and a third matching metal layer, wherein the end parts of the second matching metal layer and the third matching metal layer are electrically connected; the second matching metal layer is a second metal layer forming a matching unit in the second metal layer, and the third matching metal layer is a third metal layer forming a matching unit in the third metal layer. The first metal layer on each polysilicon layer is connected with a specific modulation potential, and the reverse modulation effect of the first metal layer is utilized to reduce or offset the electrical deviation of the resistance value of the polysilicon caused by the substrate, so that the purpose of stabilizing the resistance value of the polysilicon is achieved; the resistor array structure of the embodiment is also provided with the suspended second metal layer and the suspended third metal layer, and the suspended second metal layer and the suspended third metal layer are not connected with the second metal layer and the suspended third metal layer in the matching unit, so that the metal layers above the polycrystalline silicon layers can be ensured to be consistent, the temperature gradient distribution of the polycrystalline silicon layers forming the resistors is uniform, the wiring distribution is uniform, and the impedance matching consistency of the resistors is better ensured; the resistances and the impedances of different matching paths in the same matching unit in the embodiment are equal, so that the impedance of each resistor can be ensured to be consistent.
Although the embodiments or implementations have been illustrated and described separately above, and in relation to the techniques that are partially common, it will be apparent to those of ordinary skill in the art that alternatives and integration may be made between the embodiments or implementations, reference being made to one embodiment or implementation without explicit recitation being made to another embodiment or embodiments described.
In accordance with embodiments of the present invention, as described above, these embodiments are not exhaustive of all details, nor are they intended to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (27)

1. A resistor array structure, characterized in that:
the semiconductor device comprises a plurality of polysilicon layers which are arranged in parallel, a plurality of first metal layers which are arranged in parallel, a plurality of second metal layers which are arranged in parallel and a plurality of third metal layers which are arranged in parallel; the polysilicon layer is arranged in at least one row;
The lengths of the polysilicon layers are equal, and the polysilicon layers are distributed at the same intervals; the first metal layer is laminated above the polysilicon layer; the second metal layer is laminated above the first metal layer; the third metal layer is laminated above the second metal layer; the extending directions of the polysilicon layer, the first metal layer and the third metal layer are the same, and the extending direction of the second metal layer is perpendicular to the extending direction of the polysilicon layer;
The resistor array structure comprises a plurality of resistors, each resistor is formed by electrically connecting a plurality of polysilicon layers, and two adjacent polysilicon layers forming the same resistor are electrically connected through a matching path in a matching unit; each matching unit comprises the matching paths with the same number of resistors; each matching path comprises a second matching metal layer and a third matching metal layer, wherein the ends of the second matching metal layer and the third matching metal layer are electrically connected; the second matching metal layer is a second metal layer forming a matching unit in the second metal layer, and the third matching metal layer is a third metal layer forming a matching unit in the third metal layer.
2. The resistor array structure of claim 1, wherein:
the first metal layer on the polysilicon layer is connected with a corresponding modulation potential to reduce the influence of the substrate voltage on the resistance value.
3. The resistor array structure of claim 2, wherein:
the first metal layers on the polysilicon layers forming the same resistor are connected with the same modulation potential.
4. A resistor array structure according to claim 3 wherein:
the same modulation potential is equal to the voltage at the input of the resistor.
5. The resistor array structure of claim 1, wherein:
when the polysilicon layers are distributed in the same row, the matching units comprise first matching units;
When the polysilicon layers are distributed in different rows, the matching unit comprises a first matching unit and a second matching unit; the first matching units are matching units for realizing electrical connection between the polysilicon layers in the same row, and the second matching units are matching units for realizing electrical connection between the polysilicon layers in different rows.
6. The resistor array structure of claim 5, wherein:
the number of the polysilicon layers positioned in the same row is 2k times of the number of the resistors, wherein k is any positive integer;
The polysilicon layers which are positioned in the same row and form the same resistor are electrically connected through 2k-1 first matching units.
7. The resistor array structure of claim 6, wherein:
k first matching units in the 2k-1 first matching units are located at the first side edge of a rectangular area, the other k-1 first matching units are located at the second side edge of the rectangular area, the rectangular area is an area formed by a polycrystalline silicon layer located in the same row, and the first side and the second side are opposite and located at two ends of the polycrystalline silicon layer respectively.
8. The resistor array structure of claim 5, wherein:
When the polysilicon layers are distributed in different rows, the number of polysilicon layers in each row is equal.
9. The resistor array structure of claim 5, wherein:
The first matching unit is symmetrical about a symmetry axis, and two polysilicon layers electrically connected through a matching path in the first matching unit are positioned at two sides of the symmetry axis and are axisymmetrical;
Each matching path of the first matching unit comprises two third matching metal layers and one second matching metal layer, the two third matching metal layers are located on two sides of the symmetrical axis and are axisymmetric, two ends of the second matching metal layers are respectively and electrically connected with one end of the two third matching metal layers, and the other ends of the two third matching metal layers are respectively and electrically connected with two axisymmetric polysilicon layers.
10. The resistor array structure of claim 1, wherein:
The third matching metal layer is connected with the second matching metal layer through the first type through hole; wherein the first type of via is a via that enables electrical connection between the second metal layer and the third metal layer.
11. The resistor array structure of claim 10, wherein:
the second suspended metal layer is disconnected from the second matching metal layer near the first type through hole, wherein the second suspended metal layer is a second metal layer which is not connected with any potential in the second metal layer and is not connected with the first metal layer, the third metal layer or the polycrystalline silicon layer;
And the third suspended metal layer is disconnected from the third matching metal layer near the first type through hole, wherein the third suspended metal layer is a third metal layer which is not connected with any potential in the third metal layer and is not connected with the first metal layer, the second metal layer or the polycrystalline silicon layer.
12. The resistor array structure of claim 10, wherein:
The first type through holes in the same first matching unit are in isosceles arrangement, so that the lengths of the second matching metal layers in the matching paths in the same first matching unit are in an arithmetic progression.
13. The resistor array structure of claim 7, wherein:
The lengths of the second matching metal layers in the matching paths in the same first matching unit are in equal difference increment to the edge, parallel to the first direction, of the rectangular area; wherein the first direction is a direction parallel to the extending direction of the second metal layer.
14. The resistor array structure of claim 9, wherein:
Each polycrystalline silicon layer is connected with the third matching metal layer through a second type through hole positioned at the end part of the polycrystalline silicon layer, wherein the second type through hole is a through hole for electrically connecting the polycrystalline silicon layer and the third matching metal layer.
15. The resistor array structure of claim 9, wherein:
Each first metal layer connected to a modulation potential is disconnected in the vicinity of the second type via, and the length of each first metal layer connected to a modulation potential is smaller than the length of the polysilicon layer, so that no electrical connection exists between the second type via and the first metal layer connected to a modulation potential.
16. The resistor array structure of claim 5, wherein:
When the number of the polysilicon layers forming the same resistor in the same row is greater than 2, two first matching units connected with the same polysilicon layer are respectively distributed at two ends of the polysilicon layer.
17. The resistor array structure of claim 5, wherein:
and the resistance values of the matching paths in the first matching unit are equal.
18. The resistor array structure of claim 17, wherein:
the lengths of the matching paths in the first matching unit are equal.
19. The resistor array structure of claim 5, wherein:
The second matching unit comprises matching paths positioned above the rectangular area and matching paths positioned outside the rectangular area, wherein the resistance values of the matching paths positioned above the rectangular area in each matching path are equal; the rectangular region is a region formed by the polysilicon layers in the same row.
20. The resistor array structure of claim 19, wherein:
the lengths of the respective matching paths located above the rectangular region in the second matching unit are equal.
21. The resistor array structure of claim 19, wherein:
and the resistance values of the matching paths outside the rectangular area in the second matching unit are equal.
22. The resistor array structure of claim 19, wherein:
And the lengths of the matching paths outside the rectangular area in each matching path in the second matching unit are equal.
23. The resistor array structure of claim 7, wherein:
When the number of the polysilicon layers forming the same resistor in the same row is greater than 2, a spacing area is further arranged between the first matching units positioned at the first side edge and the second side edge of the rectangular area along the length direction of the polysilicon layers, and the spacing area comprises second spacing metal layers with the number equal to that of the resistors;
the first metal layers on the polysilicon layers forming the same resistor are electrically connected with the same second interval metal layer, and the second interval metal layer is the second metal layer positioned in the interval region.
24. The resistor array structure of claim 23, wherein:
and third modulation metal layers with the number equal to that of resistors are arranged on two sides or one side of the rectangular area and are used for being electrically connected with the second interval metal layers respectively.
25. The resistor array structure of claim 1, wherein:
Virtual resistors are further arranged on two sides of a rectangular area formed by the polycrystalline silicon layers in the same row, and each virtual resistor comprises a polycrystalline silicon layer, a first metal layer and a third metal layer.
26. The resistor array structure of claim 25, wherein:
The virtual resistor further includes a second metal layer.
27. The resistor array structure of claim 26, wherein:
The polysilicon layer forming the virtual resistor and the first metal layer forming the virtual resistor are connected with ground potential, the second metal layer forming the virtual resistor and the third metal layer forming the virtual resistor are arranged in a suspending mode, and no potential is connected.
CN202311449776.7A 2023-11-01 2023-11-01 Resistor array structure Pending CN117936539A (en)

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