CN117912957B - 一种低体二极管压降的碳化硅超结沟槽栅mosfet的制造方法 - Google Patents
一种低体二极管压降的碳化硅超结沟槽栅mosfet的制造方法 Download PDFInfo
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Abstract
本发明提供了一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，取设有漂移层的碳化硅衬底，在碳化硅衬底上淀积金属，形成漏极金属层，之后在漂移层上形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成超结区；通过离子注入方式依次形成掩蔽层、沟道区；通过淀积方式，形成第一源极金属区、隔离区、源区、第二源极金属区、栅极绝缘层以及栅极金属层，去除阻挡层，完成制造；采用了碳化硅超结结构，将器件的纵向耐压结构变为横向，相同厚度下，提高了器件的耐压能力。
Description
技术领域
本发明涉及半导体领域，特别涉及一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法。
背景技术
碳化硅(SiC)材料作为宽禁带半导体，在高压大功率领域已经有了较为广泛的应用，但是其厚外延的成本一直不能有效控制，限制了SiC MOSFET的进一步扩大应用。
碳化硅由于其材料特性，其纵向MOSFET寄生pn结体二极管的导通压降大，使得器件在未开启时的续流损耗大，这是碳化硅损耗不得不考虑的一个问题，也是亟需解决的问题。
发明内容
本发明要解决的技术问题，在于提供一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，采用了碳化硅超结结构，将器件的纵向耐压结构变为横向，相同厚度下，提高了器件的耐压能力。
本发明是这样实现的：一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，包括如下步骤：
步骤1、取设有漂移层的碳化硅衬底，在碳化硅衬底上淀积金属，形成漏极金属层，之后在漂移层上形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成超结区；
步骤2、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成掩蔽层；
步骤3、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成沟道区；
步骤4、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔进行金属淀积，形成第一源极金属区；
步骤5、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔淀积，依次形成隔离区、源区以及第二源极金属区，源极金属层包括所述第一源极金属区以及第二源极金属区；
步骤6、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔淀积栅极绝缘层；
步骤7、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，并蚀刻栅极绝缘层形成沟槽，之后通过通孔在沟槽上淀积金属，形成栅极金属层，去除阻挡层，完成制造。
进一步地，所述碳化硅衬底、漂移层、沟道区以及源区均为n型；所述超结区、掩蔽层以及隔离区均p型。
进一步地，所述碳化硅衬底的掺杂浓度为1×1020cm-3~6×1020cm-3，所述漂移层的掺杂浓度为1×1016cm-3~2×1016cm-3，所述超结区的掺杂浓度为1×1017cm-3~2×1017cm-3，所述沟道区的掺杂浓度为3×1016cm-3~6×1016cm-3，所述掩蔽层的掺杂浓度为0.6×1017cm-3~1.2×1017cm-3，所述隔离区的掺杂浓度为1×1016cm-3~2×1016cm-3，所述源区的掺杂浓度为1×1020cm-3~6×1020cm-3。
本发明的优点在于：本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，采用了碳化硅超结结构，将器件的纵向耐压结构变为横向，相同厚度下，提高了器件的耐压能力；采用了L型源极金属，构建了寄生体肖特基二极管，降低了原本pn结体二极管的压降，降低MOS续流时的损耗；采用了掩蔽层结构，保护了沟槽栅拐角处电场集中导致的栅易被击穿问题。
附图说明
下面参照附图结合实施例对本发明作进一步的说明。
图1为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法的流程图。
图2为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图一。
图3为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图二。
图4为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图三。
图5为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图四。
图6为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图五。
图7为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图六。
图8为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图七。
图9为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图八。
图10为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图九。
图11为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图十。
图12为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的工序剖视图十一。
图13为本发明一种低体二极管压降的碳化硅超结沟槽栅MOSFET的原理图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...接触”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所述的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所述的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
如图1至13所示，本申请实施例通过提供一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，包括如下步骤：
步骤1、取设有漂移层21的碳化硅衬底1，在碳化硅衬底1上淀积金属，形成漏极金属层9，之后在漂移层21上形成阻挡层a，并对阻挡层a刻蚀形成通孔，通过通孔对漂移层21进行离子注入，形成超结区2；
步骤2、去除阻挡层a后重新形成阻挡层a，并对阻挡层a刻蚀形成通孔，通过通孔对漂移层21进行离子注入，形成掩蔽层31；
步骤3、去除阻挡层a后重新形成阻挡层a，并对阻挡层a刻蚀形成通孔，通过通孔对漂移层21进行离子注入，形成沟道区3；
步骤4、去除阻挡层a后重新形成阻挡层a，并对阻挡层a刻蚀形成通孔，通过通孔进行金属淀积，形成第一源极金属区71；
步骤5、去除阻挡层a后重新形成阻挡层a，并对阻挡层a刻蚀形成通孔，通过通孔淀积，依次形成隔离区4、源区5以及第二源极金属区72，源极金属层7包括所述第一源极金属区71以及第二源极金属区73；
步骤6、去除阻挡层a后重新形成阻挡层a，并对阻挡层a刻蚀形成通孔，通过通孔淀积栅极绝缘层6；
步骤7、去除阻挡层a后重新形成阻挡层a，并对阻挡层a刻蚀形成通孔，并蚀刻栅极绝缘层6形成沟槽61，之后通过通孔在沟槽61上淀积金属，形成栅极金属层8，去除阻挡层a，完成制造。
所述碳化硅衬底1、漂移层21、沟道区3以及源区5均为n型；所述超结区2、掩蔽层31以及隔离区4均p型。
所述碳化硅衬底1的掺杂浓度为1×1020cm-3~6×1020cm-3，所述漂移层21的掺杂浓度为1×1016cm-3~2×1016cm-3，所述超结区2的掺杂浓度为1×1017cm-3~2×1017cm-3，所述沟道区3的掺杂浓度为3×1016cm-3~6×1016cm-3，所述掩蔽层31的掺杂浓度为0.6×1017cm-3~1.2×1017cm-3，所述隔离区4的掺杂浓度为1×1016cm-3~2×1016cm-3，所述源区5的掺杂浓度为1×1020cm-3~6×1020cm-3。
碳化硅衬底1采用高掺杂，是为了与漏极金属层9形成欧姆接触并降低器件的导通电阻；漂移层21掺杂浓度是器件的耐压特性和器件的导通电阻的折中。超结区2掺杂浓度是为了使器件耐压时空间电荷区分布，保证器件的耐压能力；隔离区4掺杂是为了保护器件栅极金属层8拐角处的栅极绝缘层6，以提高器件栅极可靠性，该浓度与源区5形成的空间电荷区可以形成对栅氧拐角处的保护；沟道区3掺杂浓度是为了降低导通电阻又不影响耐压，源区5掺杂浓度是为了形成欧姆接触。
各区域掺杂浓度设置了的范围，可以兼容工艺误差，浓度波动范围对器件整体性能影响不大。
本发明将器件的耐压结构从纵向变为横向（现有的碳化硅VDMOS器件耐压结构均为纵向），器件主要通过漂移层和超结区之间的pn结来保证耐压特性，能在保证器件耐压能力的前提下，降低器件漂移层厚度，减低成本（漂移层厚度越大成本越高）。
采用了L型源极金属层，源极金属层在完成与超结区进行欧姆接触的同时与沟道区形成肖特基接触，构建了寄生体肖特基二极管，降低了原本pn结体二极管的压降，降低器件在为导通时续流的损耗。
采用了掩蔽层结构，将器件在沟槽栅拐角处电场集中导致的栅极绝缘层易被击穿问题进行了保护。
本发明器件导电沟道完全为纵向，电流方向不发生变化，这就使得器件的响应速度更快。
如图13所示，上述制造方法得到的碳化硅MOSFET，包括：
碳化硅衬底1，
超结区2，所述超结区2的下侧面连接至所述碳化硅衬底1上侧面；所述超结区2内设有漂移层21，所述漂移层21下侧面连接至所述碳化硅衬底1上侧面；
沟道区3，所述沟道区3下侧面连接至所述漂移层21的上侧面，所述沟道区3内设有掩蔽层31，所述掩蔽层31的下侧面连接至所述漂移层21的上侧面；
隔离区4，所述隔离区4下侧面连接至所述掩蔽层31上侧面；
源区5，所述源区5下侧面连接至所述隔离区4上侧面；
栅极绝缘层6，所述栅极绝缘层6下侧面连接至所述掩蔽层31的上侧面，所述栅极绝缘层6上设有沟槽61；
源极金属层7，所述源极金属层7分别连接超结区2、沟道区3、隔离区4、源区5以及栅极绝缘层6；
栅极金属层8，所述栅极金属层8设于所述沟槽61内；
以及，漏极金属层9，所述漏极金属层9的上侧面连接至所述碳化硅衬底1的下侧面；
所述碳化硅衬底1、漂移层21、沟道区3以及源区5均为n型；所述超结区2、掩蔽层31以及隔离区4均p型。
虽然以上描述了本发明的具体实施方式，但是熟悉本技术领域的技术人员应当理解，我们所描述的具体的实施例只是说明性的，而不是用于对本发明的范围的限定，熟悉本领域的技术人员在依照本发明的精神所作的等效的修饰以及变化，都应当涵盖在本发明的权利要求所保护的范围内。
Claims (3)
1.一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，其特征在于，包括如下步骤：
步骤1、取设有漂移层的碳化硅衬底，在碳化硅衬底上淀积金属，形成漏极金属层，之后在漂移层上形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成超结区；
步骤2、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成掩蔽层；
步骤3、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔对漂移层进行离子注入，形成沟道区；
步骤4、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔进行金属淀积，形成第一源极金属区；
步骤5、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔淀积，依次形成隔离区、源区以及第二源极金属区，源极金属层包括所述第一源极金属区以及第二源极金属区；
步骤6、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，通过通孔淀积栅极绝缘层；
步骤7、去除阻挡层后重新形成阻挡层，并对阻挡层刻蚀形成通孔，并蚀刻栅极绝缘层形成沟槽，之后通过通孔在沟槽上淀积金属，形成栅极金属层，去除阻挡层，完成制造。
2.如权利要求1所述的一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，其特征在于，所述碳化硅衬底、漂移层、沟道区以及源区均为n型；所述超结区、掩蔽层以及隔离区均p型。
3.如权利要求1所述的一种低体二极管压降的碳化硅超结沟槽栅MOSFET的制造方法，其特征在于，所述碳化硅衬底的掺杂浓度为1×1020cm-3~6×1020cm-3，所述漂移层的掺杂浓度为1×1016cm-3~2×1016cm-3，所述超结区的掺杂浓度为1×1017cm-3~2×1017cm-3，所述沟道区的掺杂浓度为3×1016cm-3~6×1016cm-3，所述掩蔽层的掺杂浓度为0.6×1017cm-3~1.2×1017cm-3，所述隔离区的掺杂浓度为1×1016cm-3~2×1016cm-3，所述源区的掺杂浓度为1×1020cm-3~6×1020cm-3。
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