CN117912956A - Manufacturing method of low-resistance planar gate silicon carbide MOSFET - Google Patents
Manufacturing method of low-resistance planar gate silicon carbide MOSFET Download PDFInfo
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- CN117912956A CN117912956A CN202410302613.4A CN202410302613A CN117912956A CN 117912956 A CN117912956 A CN 117912956A CN 202410302613 A CN202410302613 A CN 202410302613A CN 117912956 A CN117912956 A CN 117912956A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 238000002407 reforming Methods 0.000 claims abstract description 10
- 238000001465 metallisation Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of a low-resistance planar gate silicon carbide MOSFET, which comprises the following steps: depositing metal on one side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the other side of the silicon carbide substrate to form a well region; depositing a barrier layer, etching, and performing ion implantation to form a body diode region; etching the barrier layer and the well region to form an isolation region, and depositing an isolation medium layer in the isolation region; removing the barrier layer, and depositing a transverse conductive channel region with the same doping concentration as the well region; etching, and ion implantation to form a longitudinal conductive channel region; etching, and performing ion implantation to form a source region; removing the barrier layer and depositing to form a gate dielectric layer; etching the barrier layer and the transverse conductive channel region, and performing metal deposition to form a source metal layer; removing the barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, depositing metal on the through hole to form a gate metal layer, and further reducing the on-resistance of the power device.
Description
Technical Field
The invention relates to a manufacturing method of a low-resistance planar gate silicon carbide MOSFET.
Background
Silicon carbide (SiC) materials are used as wide bandgap semiconductors, have good characteristics, and are widely applied to the field of power devices. The power MOSFET made of the material has the advantages of high input impedance, good temperature characteristic, strong voltage resistance, excellent frequency characteristic and high switching speed, and is widely applied to various fields.
The silicon carbide VDMOS is used as a representative device in SiC power devices, and has wide application in the fields of electric automobiles, aerospace, power conversion and the like. Particularly, under the condition of high-current application, the on-resistance of the high-voltage power supply is reduced, so that the device loss can be effectively reduced, and the high-voltage power supply has important significance for improving the energy utilization efficiency and realizing a double-carbon target. Therefore, there is a need to further reduce the resistance of the power device.
Disclosure of Invention
The invention aims to solve the technical problem of providing a manufacturing method of a low-resistance planar gate silicon carbide MOSFET, which can further reduce the on-resistance of a power device and effectively reduce the loss of the device.
The invention is realized in the following way: a manufacturing method of a low-resistance planar gate silicon carbide MOSFET comprises the following steps:
step 1, depositing metal on one side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the other side surface of the silicon carbide substrate to form a well region;
Step 2, a barrier layer is deposited above the well region, a through hole is formed by etching the barrier layer, and ion implantation is carried out on the through hole to form a body diode region;
Step 3, removing the barrier layer, reforming the barrier layer, etching the barrier layer and the well region to form an isolation region, and depositing an isolation medium layer in the isolation region;
Step 4, removing the barrier layer, and depositing a transverse conductive channel region with the same doping concentration as the well region;
step 5, forming a barrier layer, etching to form a through hole, and performing ion implantation on the well region through the through hole to form a longitudinal conductive channel region;
Step 6, removing the barrier layer, reforming the barrier layer, etching to form a through hole, and carrying out ion implantation on the transverse conductive channel region to form a source region;
Step 7, removing the barrier layer, and depositing to form a gate dielectric layer;
Step 8, forming a barrier layer again, etching the barrier layer and the transverse conductive channel region to form a source metal region, and performing metal deposition to form a source metal layer;
and 9, removing the barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing metal on the through hole to form a gate metal layer.
The invention has the advantages that: the invention discloses a manufacturing method of a low-resistance planar gate silicon carbide MOSFET, which adopts the matching of a transverse conductive channel region and a longitudinal conductive channel region, ensures a low-resistance path when current flows longitudinally, the transverse conductive channel region is symmetrically distributed on two sides of the longitudinal conductive channel region, the width of a gate metal layer is equal to that of the transverse conductive channel region, the potential of the gate metal layer can realize the complete control of the transverse conductive channel region, the gate control capability is enhanced, carriers in the transverse conductive channel region are inverted when the gate metal layer is pressurized and positive, namely, when a device is conducted, a low-resistance transverse conductive channel is formed, and the transverse conductive channel is directly connected with the longitudinal conductive channel, so that the low impedance of the full conductive channel of the device is realized, and the on resistance of the device is reduced.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method of fabricating a low resistance planar gate silicon carbide MOSFET according to the present invention.
Fig. 2 is a process cross-sectional view of a low resistance planar gate silicon carbide MOSFET according to the present invention.
Fig. 3 is a second cross-sectional view of a low-resistance planar gate silicon carbide MOSFET according to the present invention.
Fig. 4 is a cross-sectional view of a process step three of a low resistance planar gate silicon carbide MOSFET of the present invention.
Fig. 5 is a cross-sectional view of a process for forming a low resistance planar gate silicon carbide MOSFET according to the present invention.
Fig. 6 is a cross-sectional view of a process step five of a low resistance planar gate silicon carbide MOSFET of the present invention.
Fig. 7 is a process cross-sectional view of a low resistance planar gate silicon carbide MOSFET according to the present invention.
Fig. 8 is a cross-sectional view of a process step seven of a low resistance planar gate silicon carbide MOSFET of the present invention.
Fig. 9 is a process cross-sectional view eight of a low resistance planar gate silicon carbide MOSFET of the present invention.
Fig. 10 is a cross-sectional view of a process step nine of a low resistance planar gate silicon carbide MOSFET of the present invention.
Fig. 11 is a cross-sectional view of a process of a low resistance planar gate silicon carbide MOSFET of the present invention.
Fig. 12 is a cross-sectional view of a low resistance planar gate silicon carbide MOSFET in accordance with the present invention.
Fig. 13 is a schematic diagram of a low resistance planar gate silicon carbide MOSFET according to the present invention.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
As shown in fig. 1 to 12, an embodiment of the present application provides a method for manufacturing a low-resistance planar gate silicon carbide MOSFET, including the steps of:
step 1, depositing metal on one side surface of a silicon carbide substrate 1 to form a drain metal layer 10, and epitaxially growing on the other side surface of the silicon carbide substrate 1 to form a well region 2;
step 2, a barrier layer a is deposited above the well region 2, a through hole is formed by etching the barrier layer, and ion implantation is carried out on the through hole to form a body diode region 4;
step 3, removing the barrier layer a, reforming the barrier layer a, etching the barrier layer a and the well region 2 to form an isolation region b, and depositing an isolation medium layer 3 in the isolation region b;
Step 4, removing the barrier layer a, and depositing a transverse conductive channel region 5 with the same doping concentration as the well region 2;
Step 5, forming a barrier layer a, etching to form a through hole, and performing ion implantation on the well region 2 through the through hole to form a longitudinal conductive channel region 6;
Step 6, removing the barrier layer a, reforming the barrier layer a, etching to form a through hole, and performing ion implantation on the transverse conductive channel region 5 to form a source region 51;
step 7, removing the barrier layer a, and depositing to form a gate dielectric layer 7;
step 8, re-forming a barrier layer a, etching the barrier layer a and the transverse conductive channel region 5 to form a source metal region c, and performing metal deposition to form a source metal layer 8;
And 9, removing the barrier layer a, reforming the barrier layer a, etching the barrier layer to form a through hole, and depositing metal on the through hole to form the gate metal layer 9.
The doping concentration of the silicon carbide substrate 1 is 2e18cm -3, and the silicon carbide substrate is of an N+ type; the doping concentration of the well region 2 is 3e16 cm -3 and the well region is P-type; the doping concentration of the longitudinal conductive channel region 6 is 5e17cm -3 and is of an N+ type; the doping concentration of the body diode region 4 is 6e18 cm -3, the doping concentration of the source region 51 is 2e18cm -3, and the body diode region is N+ type; the doping concentration of the transverse conductive channel region 5 is 3e16 cm -3, and the transverse conductive channel region is P-type; the high doping is adopted in the longitudinal conductive channel region 6, so that the on-resistance can be reduced, the inversion conductive layer is low in doping and easy to invert, the driving voltage is reduced, the voltage-resistant structure is low in doping, and the voltage resistance is improved.
The gate dielectric layer 7 is silicon dioxide or a high-k dielectric.
The isolation medium layer 3 is intrinsic diamond, has high breakdown field strength while having no conductivity, realizes isolation of the transverse conductive channel region 5 and the well region 2, verifies the flow of the transverse conductive channel and the longitudinal conductive channel when the control device is conducted, avoids the current flowing to other high-resistance directions, and the intrinsic diamond material can ensure the voltage-withstanding characteristic, can dissipate heat, can realize high resistance and control the current flow direction.
The gate metal layer 9 is located right above the lateral conduction channel region 5, the lateral conduction channel region 5 is matched with the longitudinal conduction channel region 6, the longitudinal conduction channel region 6 is heavily doped in an N type, a low resistance path when current flows longitudinally is guaranteed, the lateral conduction channel region 5 is symmetrically distributed on two sides of the longitudinal conduction channel region 6, the lateral conduction channel region 5 is covered by the gate metal layer 9, namely, the width of the gate metal layer 9 is equal to that of the lateral conduction channel region 5, the potential of the gate metal layer 9 can realize complete control of the lateral conduction channel region 5, gate control capability is enhanced, carriers in the lateral conduction channel region 5 are inverted when the gate metal layer 9 is positive-pressure-applied, namely, when the device is conducted, a low resistance lateral conduction channel is formed, the lateral conduction channel is directly connected with the longitudinal conduction channel, and therefore the device is low in resistance and the conduction channel is fully conductive, and the conduction resistance of the device is reduced.
Below the source metal layer 8 there is a P + type body diode region 4 for forming the body diode of the device, which is used to complete the freewheeling of current from source to drain when the device is not conducting.
As shown in fig. 13, the silicon carbide MOSFET obtained by the above-described manufacturing method includes:
a silicon carbide substrate 1 is provided,
A well region 2, wherein the lower side surface of the well region 2 is connected to the upper side surface of the silicon carbide substrate 1;
The lower side surface of the isolation medium layer 3 is connected to the well region 2;
A body diode region 4, wherein the lower side surface of the body diode region 4 is connected to the well region 2, and the inner side of the body diode region 4 is connected to the outer side of the isolation medium layer 3;
the lower side surface of the transverse conductive channel region 5 is connected to the upper side surface of the isolation medium layer 3 and the upper side surface of the body diode region 4; a source region 51 is arranged on the transverse conductive channel region 5, and the lower side surface of the source region 51 is connected to the upper side surface of the isolation medium layer 3;
A longitudinal conductive channel region 6, wherein the longitudinal conductive channel region 6 sequentially passes through the transverse conductive channel region 5, the isolation dielectric layer 3 and the well region 2; the lower side of the longitudinal conductive channel region 6 is connected to the upper side of the silicon carbide substrate 1;
The lower side surface of the gate dielectric layer 7 is connected to the upper side surface of the transverse conductive channel region 5 and the upper side surface of the source region 51;
A source metal layer 8, wherein a side surface of the source metal layer 8 is connected to a side surface of the source region 51, and a lower side surface of the source metal layer 8 is connected to an upper side surface of the body diode region 4 and an upper side surface of the isolation medium layer 3;
The gate metal layer 9 is connected to the gate dielectric layer 7, and the gate metal layer 9 is located right above the transverse conductive channel region 5 and above the longitudinal conductive channel region 6 is hollowed out;
And a drain metal layer 10, an upper side of the drain metal layer 10 being connected to a lower side of the silicon carbide substrate 1.
The isolation medium layer 3 is intrinsic diamond; the doping concentration of the well region 2 is equal to the doping concentration of the lateral conductive channel region 5.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (5)
1. A manufacturing method of a low-resistance planar gate silicon carbide MOSFET is characterized in that: the method comprises the following steps:
step 1, depositing metal on one side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the other side surface of the silicon carbide substrate to form a well region;
Step 2, a barrier layer is deposited above the well region, a through hole is formed by etching the barrier layer, and ion implantation is carried out on the through hole to form a body diode region;
Step 3, removing the barrier layer, reforming the barrier layer, etching the barrier layer and the well region to form an isolation region, and depositing an isolation medium layer in the isolation region;
Step 4, removing the barrier layer, and depositing a transverse conductive channel region with the same doping concentration as the well region;
step 5, forming a barrier layer, etching to form a through hole, and performing ion implantation on the well region through the through hole to form a longitudinal conductive channel region;
Step 6, removing the barrier layer, reforming the barrier layer, etching to form a through hole, and carrying out ion implantation on the transverse conductive channel region to form a source region;
Step 7, removing the barrier layer, and depositing to form a gate dielectric layer;
Step 8, forming a barrier layer again, etching the barrier layer and the transverse conductive channel region to form a source metal region, and performing metal deposition to form a source metal layer;
and 9, removing the barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing metal on the through hole to form a gate metal layer.
2. A method of manufacturing a low resistance planar gate silicon carbide MOSFET as claimed in claim 1, wherein: the doping concentration of the silicon carbide substrate is 2e18cm -3, the doping concentration of the well region is 3e16 cm -3, the doping concentration of the longitudinal conductive channel region is 5e17cm -3, the doping concentration of the body diode region is 6e18 cm -3, the doping concentration of the source region is 2e18cm -3, and the doping concentration of the lateral conductive channel region is 3e16 cm -3.
3. A method of manufacturing a low resistance planar gate silicon carbide MOSFET as claimed in claim 1, wherein: the gate dielectric layer is silicon dioxide or high-k dielectric.
4. A method of manufacturing a low resistance planar gate silicon carbide MOSFET as claimed in claim 1, wherein: the isolation medium layer is intrinsic diamond.
5. A method of manufacturing a low resistance planar gate silicon carbide MOSFET as claimed in claim 1, wherein: the gate metal layer is located directly over the lateral conductive channel region.
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Citations (8)
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|---|---|---|---|---|
| KR970008422A (en) * | 1995-07-18 | 1997-02-24 | 김주용 | Manufacturing method of semiconductor device |
| US5930630A (en) * | 1997-07-23 | 1999-07-27 | Megamos Corporation | Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure |
| KR20030097344A (en) * | 2002-06-20 | 2003-12-31 | 주식회사 하이닉스반도체 | Method for fabrication of cmos transistor |
| CN106098763A (en) * | 2016-07-26 | 2016-11-09 | 电子科技大学 | A kind of RC LIGBT device and preparation method thereof |
| CN106449727A (en) * | 2015-08-04 | 2017-02-22 | 英飞凌科技奥地利有限公司 | Avalanche-rugged quasi-vertical HEMT |
| US20220131015A1 (en) * | 2020-10-28 | 2022-04-28 | Semiconductor Components Industries, Llc | Sic mosfet with built-in schottky diode |
| CN114512535A (en) * | 2022-04-18 | 2022-05-17 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of double-channel SiC transverse LDMOS power device |
| WO2023142393A1 (en) * | 2022-01-26 | 2023-08-03 | 成都蓉矽半导体有限公司 | High-speed flyback diode-integrated silicon carbide split gate mosfet and preparation method |
-
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- 2024-03-18 CN CN202410302613.4A patent/CN117912956B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970008422A (en) * | 1995-07-18 | 1997-02-24 | 김주용 | Manufacturing method of semiconductor device |
| US5930630A (en) * | 1997-07-23 | 1999-07-27 | Megamos Corporation | Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure |
| KR20030097344A (en) * | 2002-06-20 | 2003-12-31 | 주식회사 하이닉스반도체 | Method for fabrication of cmos transistor |
| CN106449727A (en) * | 2015-08-04 | 2017-02-22 | 英飞凌科技奥地利有限公司 | Avalanche-rugged quasi-vertical HEMT |
| CN106098763A (en) * | 2016-07-26 | 2016-11-09 | 电子科技大学 | A kind of RC LIGBT device and preparation method thereof |
| US20220131015A1 (en) * | 2020-10-28 | 2022-04-28 | Semiconductor Components Industries, Llc | Sic mosfet with built-in schottky diode |
| WO2023142393A1 (en) * | 2022-01-26 | 2023-08-03 | 成都蓉矽半导体有限公司 | High-speed flyback diode-integrated silicon carbide split gate mosfet and preparation method |
| CN114512535A (en) * | 2022-04-18 | 2022-05-17 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of double-channel SiC transverse LDMOS power device |
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