CN117912418A - Driving method of asymmetric gamma liquid crystal display panel - Google Patents
Driving method of asymmetric gamma liquid crystal display panel Download PDFInfo
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- CN117912418A CN117912418A CN202410109269.7A CN202410109269A CN117912418A CN 117912418 A CN117912418 A CN 117912418A CN 202410109269 A CN202410109269 A CN 202410109269A CN 117912418 A CN117912418 A CN 117912418A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000000694 effects Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 19
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000004064 recycling Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- 102100033830 Amphiphysin Human genes 0.000 description 1
- 101000779845 Homo sapiens Amphiphysin Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Abstract
The invention relates to the technical field of liquid crystal display panels, and discloses a driving method of an asymmetric gamma liquid crystal display panel, wherein for a certain source chip, gray-scale data transmitted to two adjacent rows of pixel units by a certain source line of the source chip are D 1 and D 2 respectively; if D 1≠D2, the source line CH 1 is called a gray scale varying source line; the external charge sharing judging conditions are as follows: the gray scale change source line of the source chip CH occupies more than one third of all source lines of the source chip CH; if the external charge sharing judgment condition is met, performing the following charge sharing actions: then charge sharing is performed among all source lines of the source chip CH and charge sharing is performed among source lines of other source chips; the asymmetric gamma liquid crystal display panel can achieve better charge sharing effect.
Description
Technical Field
The invention relates to the technical field of liquid crystal display panels, in particular to a driving method of an asymmetric gamma liquid crystal display panel.
Background
Liquid crystal panel displays have been developed for decades so far, and due to the characteristics of liquid crystals, the driving voltage of liquid crystal molecules must be subjected to polarity inversion, and charge sharing (CHARGE SHARING) technology is widely applied to liquid crystal displays to reduce power consumption and shorten charging time.
Fig. 1 is a schematic diagram of a conventional display driving circuit, which is generally divided into a positive polarity voltage driving Amplifier (AMPH) and a negative polarity driving Amplifier (AMPL), wherein during polarity switching, the panel loads of positive and negative polarities are shorted to perform charge sharing (CHARGE SHARING) so as to accelerate the charging speed of the next line and reduce unnecessary power consumption.
Fig. 2 is a conventional charging waveform; FIG. 3 is a schematic diagram of a display panel and a source chip; in the prior art, charge sharing is generally performed only at the output ends of a single source chip, see fig. 4; or charge sharing is performed at all the outputs of a single source chip, as shown in fig. 5.
That is, at present, the charge sharing method is mostly that any two output pins of the same chip share charge with each other, or all pins of a single chip share charge together, but the above charge sharing scheme can obtain a better effect on the premise that positive and negative polarities of Gamma of the liquid crystal display panel are symmetrical with each other.
However, in practical situations, the positive and negative polarities of Gamma are generally not completely symmetrical, so the final effects of charge sharing, such as power saving effect and charging effect, are poor by applying the above charge sharing scheme.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a driving method of an asymmetric gamma liquid crystal display panel, which combines the control of a timing controller (Timing Controller) and the winding between chips, and completes the charge sharing of all source chips together through dummy output pads (dummy output pads) of the source chips and switches, so as to achieve better charge sharing effect.
In order to solve the technical problems, the invention adopts the following technical scheme:
a driving method of an asymmetric gamma liquid crystal display panel comprises a pixel array area, a plurality of source chips and a timing controller; the pixel array area comprises pixel units which are arranged in rows and columns, each row of pixel units is connected with each other through a grid line, each column of pixel units is connected with each other through a source line, and the source line is connected with the source chip;
For a certain source chip CH, gray-scale data transmitted to two adjacent rows of pixel units by a certain source line CH 1 of the source chip CH are D 1 and D 2 respectively; if D 1≠D2, the source line CH 1 is called a gray scale varying source line;
The external charge sharing judging conditions are as follows: the gray scale change source line of the source chip CH occupies more than one third of all source lines of the source chip CH; if the external charge sharing judgment condition is met, performing the following charge sharing actions: charge sharing is performed between the source lines of the source chip CH and charge sharing is performed between the source lines of the other source chips.
Further, the external charge sharing judgment condition is replaced by: the most significant bit of the gray scale data transferred from the source chip a to the adjacent two rows of pixel units is changed.
Further, the external charge sharing judgment condition is replaced by: the source chip a changes any one of the most significant bits to the least significant bits of the gray scale data transferred to the adjacent two rows of pixel units.
Compared with the prior art, the invention has the beneficial technical effects that:
The invention judges whether the gray-scale data transmitted to two adjacent rows of pixel units by a certain source line changes or not, and judges whether the source line belongs to a gray-scale conversion source line or not; if the number of gray scale change source lines of a certain source chip is more than one third of the number of all source lines of the source chip, the source chip is subjected to external charge sharing, namely at least one source line of the source chip is connected with at least one source line of other source chips, so that external charge sharing is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional display driving circuit;
FIG. 2 is a schematic diagram of a conventional charging waveform;
FIG. 3 is a schematic diagram of a display panel and a source chip;
FIG. 4 is a schematic diagram of charge sharing between two single source chip outputs in the prior art;
FIG. 5 is a schematic diagram of charge sharing at all output terminals of a single source chip in the prior art;
FIG. 6 is a symmetrical gamma curve chart of a liquid crystal display panel;
FIG. 7 is an asymmetric gamma curve of a liquid crystal display panel;
FIG. 8 is a schematic diagram showing a specific pattern of a liquid crystal display panel;
FIG. 9 is a gamma curve chart of a liquid crystal display panel when a specific pattern is displayed;
FIG. 10 is a schematic diagram showing a specific pattern displayed on a liquid crystal display panel with polarity inversion by dot inversion;
Fig. 11 is a waveform diagram of charge sharing and charging of the source chips C and E of the lcd panel of fig. 10 at X;
fig. 12 is a waveform diagram of charge sharing and charging at X of the source chip D of the lcd panel of fig. 10;
FIG. 13 is a schematic diagram showing a specific pattern displayed on a liquid crystal display panel;
FIG. 14 is a schematic diagram of a charge sharing circuit according to a first embodiment of the invention;
FIG. 15 is a schematic diagram of a charge sharing circuit according to a first embodiment of the present invention;
FIG. 16 is a schematic diagram of a charge sharing circuit according to a second embodiment of the present invention;
FIG. 17 is a schematic diagram of a charge sharing circuit according to a second embodiment of the present invention;
fig. 18 is a schematic diagram of a charge sharing circuit according to a third embodiment of the invention;
fig. 19 is a schematic diagram of a charge sharing circuit in a third embodiment of the present invention;
fig. 20 is a schematic diagram of a level shift unit used in various embodiments of the present invention.
Detailed Description
A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
In the drawings of the invention, DVDD represents digital voltage, VSSD represents digital ground, VSSA represents analog working negative voltage, HAVDD represents half-value analog voltage, VDDA represents analog voltage, R represents resistor, and C represents capacitor; OP (Output) represents an analog voltage Output to the display panel; COF means a flip chip film; y 1,Y2,…,Yn denotes the 1 st to nth source lines of the source chip (S-IC) output. GS (Gray Scale) denotes a gray scale, gs255+ denotes a positive 255 gray scale voltage, gs255-denotes a negative 255 gray scale voltage, gs0+ denotes a positive 0 gray scale voltage, GS 0-denotes a negative 0 gray scale voltage, Δv255+ denotes an absolute value of a voltage difference between the positive 255 gray scale voltage and VCOM (display panel common voltage), and Δv255-denotes an absolute value of a voltage difference between the negative 255 gray scale voltage and VCOM (display panel common voltage); deltaV0+ represents the absolute value of the voltage difference between the positive 0 gray scale voltage and VCOM (display panel common voltage), deltaV 0-represents the absolute value of the voltage difference between the negative 0 gray scale voltage and VCOM (display panel common voltage); CS level (CHARGE SHARING LEVEL) represents the voltage after charge sharing; CS level ① represents the first charge-sharing voltage, CS level ② represents the second charge-sharing voltage; S-IC C represents source chip C, S-IC D represents source chip D, and S-IC E represents source chip E. TP1 is a control signal for controlling the display panel to share and charge, and TCON represents a time schedule controller.
Example 1
As shown in fig. 6 and 7, by way of example, when the liquid crystal display panel has a symmetrical gamma curve, Δv255+ is equal to Δv255-, - Δv0-is equal to Δv0+; when the liquid crystal display panel has an asymmetric gamma curve, deltaV255+ is greater than DeltaV255-, -DeltaV0-is greater than DeltaV0+. The 8-bit signal, also called 8-bit data, is the data size of each pixel, i.e. the power of 2 to the power of 8, and can form 256 gray-scale signals corresponding to the previous 0-255 gray-scales.
As shown in fig. 8 and 9, when the liquid crystal display panel has a gray level difference between two regions in the vertical direction, since the liquid crystal display panel has an asymmetric gamma curve, after polarity inversion, CS level ① is biased positive, whereas CS level ② is biased negative. The following analysis was performed:
As shown in fig. 10, 11 and 12, taking a liquid crystal display panel with polarity inversion by a dot inversion method as an example, after charge sharing is performed between two source lines output by a source chip C at an X position of the liquid crystal display panel, voltage is biased positive compared with a common Voltage (VCOM) of the display panel, half of the lower line is output to charge positive G0, and the other half is output to negative G0, which may cause a difference in charging voltage difference required by positive and negative polarities, resulting in a difference in charging completion time, and an poor charge recycling effect; the above analysis is equally applicable to the source chip E. For the source chip D, after charge sharing, compared with VCOM, half of the lower line is output to charge positive G255, and the other half is output to negative G255; similarly, the charging voltage difference required by the positive and negative polarities is different, so that the charging completion time is different, and the charge recycling effect is poor. The CS levels generated by the asymmetric gamma curves of the two chips are different and are averaged, so that the CS levels are closer to VCOM, the charge sharing utilization is more efficient, and the charging of the next line is more even.
As shown in fig. 13, the gray levels of two adjacent pixel units in the vertical direction in the dashed line frame in fig. 13 are not changed, even if Gamma is asymmetric, the generated CS level is not close to VCOM, but is in the middle, so that the method is more suitable for charge sharing in a single chip.
In summary, in general, the gamma curves of the lcd panel are asymmetric, so long as there is a polarity inversion in the vertical direction and a gray level change occurs, if the conventional scheme is adopted, only a single chip is used to output charge sharing, the problem of poor charge sharing effect will occur, and even if the output charging capability is not sufficiently perceived in most cases, the charge recycling effect is poor, the power consumption will also increase, and the chip temperature will also increase.
As shown in fig. 14, in this embodiment, by adding a judging circuit to TCON, a pattern judging control signal (TP 2) is generated, and when the external charge sharing of the chip is not needed, the pattern judging control signal controls the external charge sharing switch SW to be turned off through the level conversion unit, and at this time, only the charge sharing is performed between the source lines of the outputs of the source chip.
When the external charge sharing judgment condition is met, the pattern judgment control signal controls the external charge sharing switch SW to be closed through the level conversion unit, at the moment, the source chips not only share charges among the source lines, but also share charges with other chips, and the wiring mode of the charge sharing among the source chips comprises panel wiring and film wiring. As shown in fig. 15, specifically, the source chip is connected to other source chips through an external charge sharing switch SW and dummy pads (dummy pads), and a panel wiring or a thin film wiring.
As shown in fig. 20, the level shift unit (LEVEL SHIFTER) includes a first level shift module and a second level shift module. The first level conversion module is a dual-level inverter circuit for converting the pattern judgment control signal TP2 into the supply voltage VINB.
The second level conversion module comprises: MOS tubes N3, N4, N5, N6, P3, P4, P5 and P6; MOS tubes N3, N4, N5 and N6 are NMOS; MOS transistors P3, P4, P5, P6 are PMOS.
The grid electrode of the MOS tube N3 is connected with the power supply voltage VIN, the drain electrode of the MOS tube N3 is connected with the source electrode of the voltage VOUT1B, MOS tube P3 and the grid electrode of the MOS tube P4, and the source electrode of the MOS tube N3 is connected with the source electrode of the MOS tube N4; the drain electrode of the MOS tube P3 is connected with the drain electrode of the MOS tube P4, and the grid electrode of the MOS tube P3 is connected with the drain electrode of the MOS tube N4; the source electrode of the MOS tube P4 is connected with the voltage VOUT1 and the drain electrode of the MOS tube N4; the gate of MOS transistor N4 outputs voltage VINB.
The drain electrode of the MOS tube N5 is connected with the source electrode of the MOS tube P5 and the grid electrode of the MOS tube N6, the grid electrode of the MOS tube N5 is connected with the source electrode of the MOS tube P6, the voltage VCTRL and the drain electrode of the MOS tube N6, and the source electrode of the MOS tube N5 is connected with the source electrode of the MOS tube N6; the grid electrode of the MOS tube P5 is connected with the voltage VOUT1, and the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube P6; the gate of MOS transistor P6 is connected to voltage VOUT 1B.
The external charge sharing switch SW is a MOS tube, and the voltage VCTRL is used as the output of the level conversion unit and is connected with the grid electrode of the MOS tube SW.
Example two
As shown in fig. 16 and 17, the second embodiment differs from the first embodiment in that: in the second embodiment, two source chips are connected to each other by a thin film wiring manner and perform external charge sharing, and the source chips are connected to each other by a panel wiring manner and perform external charge sharing.
Example III
As shown in fig. 18 and 19, the third embodiment differs from the first embodiment in that: one source line of one source chip is connected with one source line of the other source chip through an external charge sharing switch SW, and external charge sharing is performed.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a single embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to specific embodiments, and that the embodiments may be combined appropriately to form other embodiments that will be understood by those skilled in the art.
Claims (3)
1. A driving method of an asymmetric gamma liquid crystal display panel comprises a pixel array area, a plurality of source chips and a timing controller; the pixel array area comprises pixel units which are arranged in rows and columns, each row of pixel units is connected with each other through a grid line, each column of pixel units is connected with each other through a source line, and the source line is connected with the source chip; the method is characterized in that:
For a certain source chip CH, gray-scale data transmitted to two adjacent rows of pixel units by a certain source line CH 1 of the source chip CH are D 1 and D 2 respectively; if D 1≠D2, the source line CH 1 is called a gray scale varying source line;
The external charge sharing judging conditions are as follows: the gray scale change source line of the source chip CH occupies more than one third of all source lines of the source chip CH; if the external charge sharing judgment condition is met, performing the following charge sharing actions: charge sharing is performed between the source lines of the source chip CH and charge sharing is performed between the source lines of the other source chips.
2. The method for driving an asymmetric gamma liquid crystal display panel according to claim 1, wherein the external charge sharing determination condition is replaced with: the most significant bit of the gray scale data transferred from the source chip a to the adjacent two rows of pixel units is changed.
3. The method for driving an asymmetric gamma liquid crystal display panel according to claim 2, wherein the external charge sharing determination condition is replaced with: the source chip a changes any one of the most significant bits to the least significant bits of the gray scale data transferred to the adjacent two rows of pixel units.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410109269.7A CN117912418A (en) | 2024-01-25 | 2024-01-25 | Driving method of asymmetric gamma liquid crystal display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410109269.7A CN117912418A (en) | 2024-01-25 | 2024-01-25 | Driving method of asymmetric gamma liquid crystal display panel |
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