CN117911235A - Image acquisition low-delay caching method and system - Google Patents

Image acquisition low-delay caching method and system Download PDF

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CN117911235A
CN117911235A CN202410313794.0A CN202410313794A CN117911235A CN 117911235 A CN117911235 A CN 117911235A CN 202410313794 A CN202410313794 A CN 202410313794A CN 117911235 A CN117911235 A CN 117911235A
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fifo
data
memory
fifo memory
ddr
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CN117911235B (en
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魏志龙
张帆
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Hubei Xinqing Technology Co ltd
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Hubei Xinqing Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Input (AREA)

Abstract

An image acquisition low-delay caching method and system relate to the technical field of image processing, wherein the image acquisition low-delay caching method comprises the following steps: writing data into a first-in first-out (FIFO) memory in the Buffer until the FIFO memory is full, and switching to writing data into a double-rate synchronous dynamic random access memory (DDR); when certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory. The application can reduce the DDR memory space and DDR access bandwidth while reducing the low delay of image transmission.

Description

Image acquisition low-delay caching method and system
Technical Field
The application relates to the technical field of image processing, in particular to a low-delay caching method and system for image acquisition.
Background
Image processing is a technique in which images are analyzed by a computer to achieve a desired result, and in the course of which reading and storing of images is important.
One way adopted at present is through ping pong storage, namely after the image acquisition module finishes writing frame_ Bufer, informing the image processing module to read frame_ Bufer, and then after the image acquisition module finishes writing frame_ Bufer1, informing the image processing module to read frame_ Bufer1, and sequentially circulating. This approach not only occupies a large amount of DDR (Double DATA RATE SDRAM, double rate synchronous dynamic random access memory) bandwidth, but also requires 2 frames of DDR memory space and also has a large latency.
The other mode is that a certain storage space is opened up at the DDR, the DDR storage threshold value is set by calculating the ratio between the writing bandwidth of the image acquisition module and the reading bandwidth of the image processing module, and the image processing module starts to read after the writing of the image acquisition module reaches the change threshold value. The scheme saves a certain DDR storage space and reduces image delay. However, in a non-exclusive DDR system, the throughput of the image acquisition module and the image processing module to DDR cannot be ensured, so that the method cannot be fully ensured to function.
Disclosure of Invention
The application provides an image acquisition low-delay caching method and system, which can reduce DDR storage space and DDR access bandwidth while reducing image transmission low-delay.
In a first aspect, an embodiment of the present application provides an image capturing low-latency caching method, where the image capturing low-latency caching method includes:
Writing data into a first-in first-out (FIFO) memory in the Buffer until the FIFO memory is full, and switching to writing data into a double-rate synchronous dynamic random access memory (DDR);
When certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory.
With reference to the first aspect, in an implementation manner, the writing data to the FIFO memory in the Buffer until the FIFO memory is full, switching to writing data to the DDR, and when certain data is read from the FIFO memory so that the depth of the remaining storage space in the FIFO memory is greater than the read FIFO threshold value, switching to writing data to the FIFO memory includes:
In the beginning stage, a control unit of a Buffer controls a channel of strobe write FIFO to directly write data into a FIFO memory;
after the FIFO memory is fully written, the control unit controls the access of the strobe write DDR to switch to write data to the DDR;
When certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the control unit controls the access of the strobe write FIFO and then switches to write the data into the FIFO memory.
With reference to the first aspect, in an implementation manner, the method further includes:
the control unit of Buffer gates between read FIFO and read DDR, and outputs data according to the first-in first-out order to read data.
With reference to the first aspect, in an implementation manner, the method further includes:
when the FIFO memory in Buffer has no data, the read behavior is blocked.
With reference to the first aspect, in one implementation, the read FIFO threshold value is adjustably set between 25% and 75% of FIFO depth.
In a second aspect, an embodiment of the present application provides an image capturing low-latency buffer system, including:
Double rate synchronous dynamic random access memory DDR;
a Buffer comprising a first-in first-out FIFO memory;
the image acquisition module is alternatively connected with the FIFO memory and the DDR;
An image processing module, which is alternatively connected with the FIFO memory and the DDR;
and the FIFO memory and DDR are configured to:
When the image acquisition module writes data into the FIFO memory, if the FIFO memory is full, the image acquisition module is switched to write data into the DDR memory, and when the image processing module reads certain data in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the image acquisition module is switched to write data into the FIFO memory.
With reference to the second aspect, in one embodiment, the Buffer further includes a control unit, where the control unit is configured to control strobe of the write FIFO and the write DDR channel.
With reference to the second aspect, in one implementation, the control unit is further configured to gate between a read FIFO and a read DDR, and output data in a first-in first-out order for reading data.
With reference to the second aspect, in one implementation manner, the control unit is further configured to block the read behavior when the FIFO memory in the Buffer has no data.
With reference to the second aspect, in one embodiment, the read FIFO threshold value is adjustably set between 25% and 75% of FIFO depth.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
The application discloses an image acquisition low-delay caching method, which adopts a special state machine scheduling method, namely, data is written into a first-in first-out FIFO memory in a cache Buffer until the FIFO memory is full, and the method is switched to write data into a double-rate synchronous dynamic random access memory DDR; when certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory. In this way, while low latency is guaranteed, DDR storage and DDR bandwidth access requirements are reduced because a large amount of image data is stored in the FIFO.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for image acquisition low-latency caching according to the present application;
FIG. 2 is a block diagram illustrating an embodiment of an image acquisition low-latency cache system according to the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "comprising" and "having" and any variations thereof in the description and claims of the application and in the foregoing drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and "third," etc. are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order, and are not limited to the fact that "first," "second," and "third" are not identical.
In describing embodiments of the present application, "exemplary," "such as," or "for example," etc., are used to indicate by way of example, illustration, or description. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.
In the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: the three cases where a exists alone, a and B exist together, and B exists alone, and furthermore, in the description of the embodiments of the present application, "plural" means two or more than two.
In some of the processes described in the embodiments of the present application, a plurality of operations or steps occurring in a particular order are included, but it should be understood that the operations or steps may be performed out of the order in which they occur in the embodiments of the present application or in parallel, the sequence numbers of the operations merely serve to distinguish between the various operations, and the sequence numbers themselves do not represent any order of execution. In addition, the processes may include more or fewer operations, and the operations or steps may be performed in sequence or in parallel, and the operations or steps may be combined.
First, some technical terms in the present application are explained so as to facilitate understanding of the present application by those skilled in the art.
DDR: double DATA RATE SDRAM, double rate synchronous dynamic random access memory;
Frame_ Bufer: caching frame images;
FIFO: FIRST IN FIRST Out, first in first Out;
fifo_domain_depth: the depth of the remaining memory space in the FIFO;
RD_FIFO_TH: read FIFO threshold.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
In a first aspect, an embodiment of the present application provides a method for caching an image acquired with low latency, including:
Writing data into a first-in first-out (FIFO) memory in the Buffer until the FIFO memory is full, and switching to writing data into a double-rate synchronous dynamic random access memory (DDR);
When certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory.
In view of the defects of the prior art, the application adopts special state machine scheduling to realize an image acquisition low-delay caching method. The DDR memory space and the DDR access bandwidth are reduced while the low delay of image transmission is reduced.
Specifically, the embodiment improves the scheme in the prior art, and adopts a special state machine scheduling method to realize controllable storage of image frame data in the FIFO memory and the DDR. That is, if the FIFO memory is full, the next image data is stored in the DDR; if there is excess memory fifo_remain_depth in the FIFO and greater than the threshold read_fifo_th, the image data is restored in the FIFO. In this way, while low latency is guaranteed, DDR storage and DDR bandwidth access requirements are reduced because a large amount of image data is stored in the FIFO.
In particular, in one embodiment, as shown in fig. 1, data is written into a first-in first-out FIFO memory in a Buffer until the FIFO memory is full, and the writing is switched to writing data into a double-rate synchronous dynamic random access memory DDR; when certain data is read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory comprises the following steps:
s1, in the beginning stage, a control unit of a Buffer controls a passage of strobe write FIFO to directly write data into a FIFO memory;
s2, after the FIFO memory is fully written, the control unit controls the access of the strobe write DDR to switch to write data to the DDR;
And S3, when certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than a read FIFO threshold value, the control unit controls the access of gating write FIFO and then switches to write data into the FIFO memory.
For ease of understanding, the write Buffer procedure and the read Buffer procedure are described below with reference to fig. 2 at the same time:
the image acquisition module writes the Buffer process:
the image acquisition module writes data into the Buffer. In the beginning stage, the data are directly written into the FIFO memory in the Buffer, and if the FIFO memory is full, the image acquisition module writes the data in the Buffer, and the data are turned from the Buffer to be written into the DDR.
When the image processing module READs certain data from the FIFO, and the residual free space (fifo_domain_depth) in the FIFO is larger than the configuration threshold value (READ_FIFO_TH), the data written into the Buffer by the image acquisition module continues to be written into the FIFO.
The above-mentioned channel selection for writing FIFO and DDR is controlled by control unit of Buffer, i.e. the image acquisition module can be alternatively connected with the described FIFO memory and DDR.
The image processing module reads the Buffer process:
The Buffer control unit sends data to the image processing module in a first-in first-out order. The process is controlled by a Buffer control unit, and is gated between FIFO reading and DDR reading, that is, the image processing module can be alternatively connected with the FIFO memory and the DDR, and sequentially reads data from the FIFO memory and the DDR according to the writing sequence of the image acquisition module.
In addition, if there is no data in Buffer, the read behavior of the image processing module will be blocked. This means that the read behavior of the image processing module is anytime to achieve that the image transmission and image processing can be done simultaneously or with low latency.
In some embodiments, the read FIFO threshold value is adjustably set between 25% and 75% of FIFO depth.
It can be understood that the FIFO threshold value needs to be set reasonably, if the setting is too small, the FIFO and DDR will be switched frequently, and if the setting is too large, the effect of saving DDR buffer space and DDR access bandwidth will not be achieved, so the application comprehensively considers that the read FIFO threshold value is set adjustably between 25% and 75% of the FIFO depth. It should be noted that, the size of the FIFO threshold depends on the processing performance of the device, i.e. the FIFO threshold can be selected according to the actual device performance, and can be adjusted according to different reading and storing speeds to increase the reading and storing speeds, so that in the application, the highest performance is achieved by setting the flexibility of the FIFO threshold.
In summary, the image acquisition low-delay caching method of the application adopts a special state machine scheduling method, namely, the method is switched to write data into the double-rate synchronous dynamic random access memory DDR by writing the data into the first-in first-out FIFO memory in the cache Buffer until the FIFO memory is full; when certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory. In this way, while low latency is guaranteed, DDR storage and DDR bandwidth access requirements are reduced because a large amount of image data is stored in the FIFO.
In a second aspect, the embodiment of the application further provides an image acquisition low-delay cache system.
In an embodiment, referring to fig. 2, fig. 2 is a schematic functional block diagram of an embodiment of an image capturing low-latency buffer system according to the present application. As shown in fig. 2, the image acquisition low-latency buffer system includes:
Double rate synchronous dynamic random access memory DDR;
a Buffer comprising a first-in first-out FIFO memory;
the image acquisition module is alternatively connected with the FIFO memory and the DDR;
An image processing module, which is alternatively connected with the FIFO memory and the DDR;
and the FIFO memory and DDR are configured to:
When the image acquisition module writes data into the FIFO memory, if the FIFO memory is full, the image acquisition module is switched to write data into the DDR memory, and when the image processing module reads certain data in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the image acquisition module is switched to write data into the FIFO memory.
DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory ) is commonly referred to as DDR, is SDRAM with double data rate, and has twice the system clock frequency.
The FIFO memory is a first-in first-out dual-port buffer, i.e., the first data entered therein is first shifted out, with one port being the input port of the memory and the other port being the output port of the memory.
The image acquisition low-delay buffer system in the embodiment adopts special state machine scheduling, and reduces DDR storage space and DDR access bandwidth while reducing image transmission low-delay.
In particular, it may enable controllable storage of image frame data in FIFO memories and DDR. That is, if the FIFO memory is full, the next image data is stored in the DDR; if there is excess memory fifo_remain_depth in the FIFO and greater than the threshold read_fifo_th, the image data is restored in the FIFO. In this way, while low latency is guaranteed, DDR storage and DDR bandwidth access requirements are reduced because a large amount of image data is stored in the FIFO.
Further, in an embodiment, the Buffer further includes a control unit, where the control unit is configured to control the strobe of the write FIFO and the write DDR.
In this embodiment, controllable storage of image frame data is realized in FIFO memories and DDR, mainly by gating of the control unit.
Specifically, in the beginning stage, a control unit of the Buffer controls a passage of strobe write FIFO to directly write data into the FIFO memory; after the FIFO memory is fully written, the control unit controls the access of the strobe write DDR to switch to write data to the DDR; when certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the control unit controls the access of the strobe write FIFO and then switches to write the data into the FIFO memory.
Further, in an embodiment, the control unit is further configured to gate between the read FIFO and the read DDR, and output data in a first-in first-out order for reading data.
The Buffer control unit sends data to the image processing module in a first-in first-out order. The data is sequentially read from the FIFO memory and the DDR in the order written by the image acquisition module.
Further, in an embodiment, the control unit is further configured to block the read behavior when the FIFO memory in the Buffer has no data.
Further, in an embodiment, the read FIFO threshold value is adjustably set between 25% and 75% of FIFO depth.
It should be noted that the size of the FIFO threshold depends on the processing performance of the device, i.e. it can be selected according to the actual device performance, and can be adjusted according to different reading and storing speeds to increase the reading and storing speeds.
In summary, the image acquisition low-delay buffer system in the application comprises a double rate synchronous dynamic random access memory DDR; a Buffer comprising a first-in first-out FIFO memory; the image acquisition module is alternatively connected with the FIFO memory and the DDR; an image processing module, which is alternatively connected with the FIFO memory and the DDR; and the FIFO memory and DDR are configured to: when the image acquisition module writes data into the FIFO memory, if the FIFO memory is full, the image acquisition module is switched to write data into the DDR memory, and when the image processing module reads certain data in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the image acquisition module is switched to write data into the FIFO memory.
Namely, the image acquisition low-delay Buffer system adopts a special state machine scheduling method, and data is written into a first-in first-out FIFO memory in a Buffer until the FIFO memory is full, and the data is switched to be written into a double-rate synchronous dynamic random access memory DDR; when certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory. In this way, while low latency is guaranteed, DDR storage and DDR bandwidth access requirements are reduced because a large amount of image data is stored in the FIFO.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (10)

1. The image acquisition low-delay caching method is characterized by comprising the following steps of:
Writing data into a first-in first-out (FIFO) memory in the Buffer until the FIFO memory is full, and switching to writing data into a double-rate synchronous dynamic random access memory (DDR);
When certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, switching to writing the data into the FIFO memory.
2. The method for low-latency image capture Buffer according to claim 1, wherein said writing data to the FIFO memory in the Buffer until the FIFO memory is full, switching to writing data to the DDR memory, and when a certain data is read from the FIFO memory such that the depth of the remaining memory space in the FIFO memory is greater than the read FIFO threshold value, switching to writing data to the FIFO memory comprises:
In the beginning stage, a control unit of a Buffer controls a channel of strobe write FIFO to directly write data into a FIFO memory;
after the FIFO memory is fully written, the control unit controls the access of the strobe write DDR to switch to write data to the DDR;
When certain data are read in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the control unit controls the access of the strobe write FIFO and then switches to write the data into the FIFO memory.
3. The image acquisition low-latency caching method according to claim 2, further comprising:
the control unit of Buffer gates between read FIFO and read DDR, and outputs data according to the first-in first-out order to read data.
4. The image acquisition low-latency caching method according to claim 2, further comprising:
when the FIFO memory in Buffer has no data, the read behavior is blocked.
5. The image acquisition low-latency caching method according to claim 1, wherein:
The read FIFO threshold value is adjustably set between 25% and 75% of FIFO depth.
6. An image acquisition low-latency caching system, comprising:
Double rate synchronous dynamic random access memory DDR;
a Buffer comprising a first-in first-out FIFO memory;
the image acquisition module is alternatively connected with the FIFO memory and the DDR;
An image processing module, which is alternatively connected with the FIFO memory and the DDR;
and the FIFO memory and DDR are configured to:
When the image acquisition module writes data into the FIFO memory, if the FIFO memory is full, the image acquisition module is switched to write data into the DDR memory, and when the image processing module reads certain data in the FIFO memory so that the depth of the residual storage space in the FIFO memory is larger than the read FIFO threshold value, the image acquisition module is switched to write data into the FIFO memory.
7. The image acquisition low-latency caching system of claim 6, wherein:
the Buffer further comprises a control unit for controlling the gating of the write FIFO and the write DDR channels.
8. The image acquisition low-latency caching system of claim 7, wherein:
the control unit is also used for gating between the read FIFO and the read DDR, and outputting data according to the first-in first-out sequence to read the data.
9. The image acquisition low-latency caching system of claim 6, wherein:
The control unit is further configured to block the read behavior when the FIFO memory in the Buffer has no data.
10. The image acquisition low-latency caching system of claim 6, wherein:
The read FIFO threshold value is adjustably set between 25% and 75% of FIFO depth.
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