JP2005222180A - Image data arrangement method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image data arrangement method enabling continuous data access and high-speed data transfer to effectively practically use a band width. <P>SOLUTION: A cycle number (time) necessary for the continuous data access by a bank changeover is determined on the basis of the number of banks of a frame memory, an access interval (an access inability time) taken until data access becomes possible after prescribed setting such as precharge setting is performed, and a cycle number (an access time) taken for data access to one line of a rectangular area such as a macro block determined by a bus width (the band width). An image is divided along a scanning line such that lines of the rectangular area of an accessable number within the determined cycle number are included in the vertical direction of the area obtained by dividing the image, and is arranged in each page. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for arranging image data in a frame memory in a video device such as a video disc player that performs image processing.

Recently, MPEG (M oving P icture E xperts G roup) 2, an image processing spread of technology such as MPEG4 proceeds, the image processing even in ordinary devices such as mobile phones and personal computers is not limited to video equipment such as a video disc player There has been a lot to do.

  When performing image processing, an expensive and high-speed dedicated SRAM such as a VRAM (Video RAM) has been conventionally used as a frame memory. ) Because of the low cost of high-speed and large-capacity memories such as RAMBUS-DRAM, image processing devices using these memories have entered the popular stage, and fields such as video disc players, digital broadcast set boxes, and personal computers However, LSIs that perform image processing using these memories have been actively developed.

  Image transfer access to the frame memory can be divided into the following two types. One is data access when decompressing an image compressed by the MPEG standard or the like. When an image compressed according to the MPEG standard or the like is expanded, differential image processing and motion prediction processing are performed. Usually, this processing is performed on a rectangular area of 16 pixels × 16 rows (256 pixels) called a macroblock. Separate them. Therefore, when performing differential image processing and motion prediction processing, an image is read in units of macroblocks. The reading method of the macroblock is a reading method of reading out one line at a time along the scanning line in the range of the macroblock. This data access is called macroblock access. The other is scanning line access for displaying an image, which reads the entire image. The reading method is a reading method in which the entire image is read line by line along the scanning line. Schematic diagrams of macroblock access and scanning line access are shown in FIGS.

  On the other hand, as described above, SDRAM or the like has recently been used as a frame memory. These memories can be accessed at high speed by bank switching or burst mode technology.

  The bank switching technique is a technique in which divided data is arranged in a plurality of banks provided in one memory, and data access is performed while sequentially switching the banks when accessing the data. Yes, it can be realized by a memory capable of independent memory control for each bank. Further, the bank is divided into pages of a certain size, and after a predetermined setting is made in the bank, data can be continuously accessed within the predetermined page (page mode). The burst mode technique is a technique for continuously accessing the data of the next address by simply designating one address. Since the address designation can be omitted, the access speed is improved.

  Conventionally, using this technology, an image is divided into rectangular areas of a specific size, such as macroblocks or blocks of M pixels × N rows, and one line is continuous along the scanning line within the rectangular area. A rectangular area is arranged on each page in each bank so that data can be transferred. However, adjacent rectangular areas are arranged in different banks in both the vertical and horizontal directions. A schematic diagram of this data arrangement is shown in FIG.

  With this arrangement, data access within the same page is performed during macroblock access, so high-speed data transfer is possible with only one precharge setting and active setting described later. In scanning line access, data placed in different banks is accessed every time a rectangular area is crossed, but continuous data transfer can be performed using bank switching and burst mode techniques, and high-speed data transfer is possible ( For example, see Patent Documents 1 and 2.)

  Hereinafter, as conventional SDRAM and DDR-SDRAM, MICRON MT48LC4M16A2, MT48LC8M16A2 and MT46V8M16 as of April 2003 are taken as examples (refer to the data sheet of each product), and scanning lines in the conventional image data arrangement described above are used. The access will be described. The SDRAM is a DRAM that can input and output data in synchronization with the rising edge of the clock, and the DDR-SDRAM is a DRAM that can input and output data in synchronization with both the rising and falling edges of the clock.

  In this memory, in the operation of 113 [MHz], 3 cycles after precharge setting (Precharge), 2 to 3 cycles after page setting (Active) (2 cycles when operating at low speed, 3 cycles when operating at high speed) If the cycle does not elapse, the next instruction cannot be executed. The restriction time required until the next instruction is executed after this precharge setting or page setting is called an access restriction value.

  First, the case of accessing data arranged on different pages in the same bank in the SDRAM will be described with reference to FIGS. FIG. 13A schematically shows a state in which data arranged on different pages in the bank 0 is accessed.

  FIG. 13B shows the execution timing of each access. As shown in FIG. 13 (b), in this case, after the previous read / write command (Read / Write) is completed, the precharge setting and page setting of the next page must be performed again. An access interval (inaccessible time) occurs.

  FIG. 13C shows signals appearing on the control signal bus and the data bus. As described above, after the previous read / write command is completed, the precharge setting and page setting of the next page must be performed again, so that the signals generated on the control signal bus and the data bus are scattered. . Similar results can be obtained with the DDR-SDRAM.

  Next, in the SDRAM, a case where data arranged on different pages in different banks is accessed while switching banks will be described with reference to FIGS. FIG. 14A schematically shows a state in which data arranged on different pages in the banks 0 to 3 is accessed while switching banks.

  FIG. 14B shows the execution timing of each access. As shown in FIG. 14 (b), in this case, data access is performed while switching the bank. Therefore, while waiting after performing precharge setting and page setting for one bank, for another bank. Precharge setting and page setting can be executed.

  FIG. 14C shows signals appearing on the control signal bus and the data bus. As described above, the precharge setting and the page setting can be executed for another bank during the standby after the precharge setting and the page setting for the certain bank. The signal generated in is active compared to FIG. Similar results can be obtained with the DDR-SDRAM.

  15 (a) to 15 (c) show that the data at the address following the address specified by a single read / write command is continuously accessed by the burst mode technique. ) Is different. Here, as shown in FIG. 15B, four cycles of data (data of four burst transfer lengths) are continuously accessed by one read / write instruction (that is, four consecutive transfers are accessed). . By continuously accessing data for a certain number of cycles as described above, signals can be continuously generated on the data bus as shown in FIG. Similar results can be obtained with the DDR-SDRAM.

  As described above, by using the bank switching and burst mode techniques, it is possible to continuously access data even if the divided data is arranged in different banks.

  Therefore, as described above, if an image is arranged on each page in each bank in units of a rectangular area, and data access is continuously performed on one line of the rectangular area by the burst mode technique, scanning line access is performed. In addition, the bank switching technique enables continuous data access and enables high-speed data transfer.

  Recently, however, the price of video disc players and set-top boxes has been declining and the number of parts has tended to decrease. When reducing the number of parts, a solution is often taken to reduce the number of parts by sharing a memory. In this case, the memory is often integrated with the bus width of the system that requires the most bandwidth.

  In addition, in an LSI sharing a memory, in order to expand a function accompanied by an increase in bandwidth, the bandwidth is often expanded by expanding the bus width. In such a case, there arises a case where the image processing apparatus must be configured with a bus width wider than that originally used for image processing.

  As the bus width increases, the amount of data transferred by one access increases. Image data is often composed of 1 pixel = 8 bits. Also, image processing for images compressed according to the MPEG2 and MPEG4 standards is performed in units of macroblocks (16 pixels × 16 rows (256 pixels)) or block units (8 pixels × 8 rows ( The processing is often performed at 64 pixels)).

  When one line (16 bytes) of one macroblock is transferred continuously, 16 cycles when the bus width is 8 bits, 8 cycles when it is 16 bits, 4 cycles when it is 32 bits, 2 cycles when it is 64 bits, etc. The number of required transfer cycles (access time) is reduced. Hereinafter, conventional scanning line access when a macroblock is used as a rectangular area will be described.

  First, the case where the bus width is expanded so that data transfer of one line of one macroblock can be performed in about three cycles in the SDRAM will be described with reference to FIGS. This is a case where the bus width is about 48 bits. FIG. 16A schematically shows a state in which data arranged on different pages in the banks 0 to 3 is accessed while switching banks.

  FIG. 16 (b) shows the execution timing of each access, and FIG. 16 (c) shows signals appearing on the control signal bus and the data bus. In this way, a single read / write command takes three cycles. When data for one minute (3 burst transfer length data) is continuously accessed, the data bus operates without interruption.

  On the other hand, FIGS. 17A to 17C show a case where the bus width is extended so that data transfer of one line of one macroblock can be performed in about two cycles as compared to FIGS. In this case, the data bus is interrupted to operate. This is due to the number of banks of the SDRAM and the access interval (inaccessible time).

  As described above, when an image is divided into rectangular areas and arranged in different blocks, depending on the number of banks of the memory to be used and the access interval, there is a gap in data transfer during scanning line access depending on the bandwidth (bus width). Open and you will not be able to make effective use of available bandwidth.

  Further, in the DDR-SDRAM, when the length is 5 burst transfer length or less, a gap is opened for data transfer, and the available bandwidth cannot be used effectively. FIGS. 18A to 18C show the case where the bus width is expanded in the DDR-SDRAM so that data transfer of one line of one macro block can be performed in about five cycles. The data bus operates without interruption. However, if the burst transfer length (the number of cycles for continuous access by one read / write command (access time)) becomes shorter due to the number of banks and the access interval of the DDR-SDRAM, data transfer is performed during scanning line access. The gap becomes wide and the available bandwidth cannot be used effectively.

In recent years, MPEG4 technology has begun to spread. In MPEG4, the small transfer bit rate is supplemented by processing such as an image filter. Some image filter techniques are performed in units of blocks, but many are processed in units of scan lines, and the importance of scan line access is increasing.
JP-A-8-55060 JP-A-9-106374

  In view of the above problems, the present invention divides an image along a scanning line as shown in FIGS. 1 and 2 when the page size is sufficient for the number X of pixels in the scanning line direction of the image. Place on each page. That is, the number of cycles (time) required for continuous data access by bank switching is determined from the number of banks in the frame memory and the predetermined setting such as precharge setting until data access becomes possible. This is determined based on the access interval (access inaccessible time) and the number of cycles (access time) required to access data in one line of a rectangular area such as a macro block determined by the bus width (band width). Then, the image is divided along the scanning line so that the lines of the rectangular area that can be accessed within the determined number of cycles are included in the vertical direction of the divided area. By arranging this divided image on each page, scanning line access can be performed on a page basis, and when macroblock access is performed by bank switching, data can be continuously accessed to macroblocks. An object of the present invention is to provide an image data arrangement method capable of realizing access and high-speed data transfer and effectively utilizing the bandwidth.

  Further, according to the present invention, when the page size is insufficient with respect to the number X of pixels in the scanning line direction of an image, the number of cycles (time) required for continuous data access by bank switching is set in the frame memory. Of the rectangular area such as a macro block determined by the number of banks and the access interval (inaccessible time) required for data access after a predetermined setting such as precharge setting and the bus width (bandwidth) This is determined based on the number of cycles (access time) required for data access to one line. Then, the image is divided so that the lines of the rectangular area that can be accessed within the determined number of cycles are included in the scanning line direction and the vertical direction of the divided area. By arranging the divided images on each page, it is possible to continuously access data when scanning line access and macroblock access are performed by bank switching, realizing continuous data access and high-speed data transfer. An object of the present invention is to provide an image data arrangement method capable of effectively utilizing the width.

  Further, the number of lines of the number of blocks that can be accessed within the determined number of cycles (within time) is determined, and the vertical direction of the area in which the macroblock lines equal to or greater than the number of lines of the determined block divide the image By dividing the image as shown in Figure 3, image data that can effectively use the bandwidth by realizing continuous data access and high-speed data transfer even during data access (block access) in block units by bank switching An object is to provide an arrangement method.

  The image data arrangement method according to claim 1 of the present invention includes a plurality of banks that can be controlled independently, the banks are divided into pages of a certain size, and each bank has a predetermined setting. For a frame memory that can be randomly accessed continuously in each predetermined page later, the image is divided along the scanning line and arranged on each page, and a specific size set in the image An image data arrangement method in which data access along a scanning line for each rectangular area is performed while switching the bank, and the time required for continuous data access while switching the bank is reduced. The number of banks, the inaccessible time required for data access after the predetermined setting is made, and the scanning of the rectangular area The number of lines in the rectangular area that can be accessed within the determined time is included in the vertical direction of the area into which the image is divided. As described above, the image is divided, and the divided image is arranged on each page.

According to a second aspect of the present invention, there is provided the image data arrangement method according to the first aspect, wherein the image is divided in accordance with a page size.
The image data arrangement method according to claim 3 of the present invention is the image data arrangement method according to claim 1 or 2, wherein the rectangular area is a macroblock.

  The image data arrangement method according to claim 4 of the present invention is the image data arrangement method according to claim 3, wherein the image processing unit is smaller than the number of macroblocks accessible within the determined time. The number of lines in the scanning line direction of the block is determined, and the image is divided so that the macroblock lines equal to or greater than the determined number of lines of the block are included in the vertical direction of the region into which the image is divided. It is characterized by doing.

  The image data arrangement method according to claim 5 of the present invention is composed of a plurality of banks that can be controlled independently, the banks are divided into pages of a certain size, and each bank has a predetermined setting. An image data arrangement method in which an image is divided and arranged on each page with respect to a frame memory that can be randomly accessed continuously in each predetermined page after being made, while switching the bank The time required for continuous data access includes the number of banks, the inaccessible time from when the predetermined setting is made until data access is possible, and the specific set for the image It is determined on the basis of the access time required to access data in one line in the scanning line direction of the rectangular area of the size, and within the determined time The image is divided so that an accessible number of lines of the rectangular area are included in a scanning line direction and a vertical direction of the divided area, and the divided image is arranged on each page. To do.

According to a sixth aspect of the present invention, there is provided the image data arranging method according to the fifth aspect, wherein the image is divided in accordance with a page size.
The image data arrangement method according to claim 7 of the present invention is the image data arrangement method according to claim 5 or 6, wherein the rectangular area is a macroblock.

  The image data arrangement method according to claim 8 of the present invention is the image data arrangement method according to claim 7, wherein the image processing unit is smaller than the number of macroblocks accessible within the determined time. The number of lines in the scanning line direction of the block is determined, and the image is divided so that the macroblock lines equal to or greater than the determined number of lines of the block are included in the vertical direction of the region into which the image is divided. It is characterized by doing.

  According to the present invention, continuous data access and high-speed data transfer can be realized in macroblock access and scanning line access, and the bandwidth can be effectively utilized. Also, by dividing the image according to the page size, the memory area can be used without waste. In addition, continuous data access and high-speed data transfer can be realized even during image processing in units of blocks, and bandwidth can be used effectively.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, the data size of image data is 720 pixels × 420 rows, and the data size of one macroblock is 16 pixels × 16 rows = 256 bytes. Further, the case where the above-described MT48LC4M16A2, MT48LC8M16A2 and MT46V8M16 (SDRAM, DDR-SDRAM) manufactured by MICRON are used as the frame memory will be described as an example. It is assumed that the frame memory is composed of a plurality of banks that can be controlled independently, can be randomly accessed in the page mode, and shares the control means of each bank with one port.

(Embodiment 1)
Hereinafter, an image data arrangement method according to the first embodiment will be described. The image data arrangement method according to the first embodiment is an arrangement method when the page size is sufficient for the number of pixels X in the scanning line direction of the image.

  In the image data arrangement method, an image is divided along a scanning line and arranged on each page of a certain size, scanning line access is performed in the page mode, and a specific size set in the image is set. Data access (macroblock access) along a scanning line for each rectangular area (macroblock which is an image processing target here) is continuously performed while switching banks.

  In other words, the number of cycles (time) required for continuous data access while switching banks is the number of banks (here, four), and access caused by precharge setting or active setting (predetermined setting). Interval (inaccessible time. Here, 3 cycles after precharge setting and 3 cycles after page setting are required, the access interval is 6 cycles) and the number of cycles required to access data in one line of the rectangular area ( This is determined based on the access time (here, 2 cycles as will be described later). Then, the image is divided and arranged on each page so that the number of lines of the rectangular area that can be accessed within the determined number of cycles is included in the vertical direction of the divided area. FIG. 1 shows an example of dividing an image by the above method. FIG. 2 shows an example in which image data divided by the above method is arranged on each page.

  This image data division / arrangement is executed by the image processing apparatus according to the execution program. For example, when it is determined that the image is divided along the scanning line every 5 lines and 496 bytes as described later, the image processing apparatus divides the image data to be processed into every 5 lines and 496 bytes. The macro block access is arranged on each page so that it can be executed by switching the bank.

  In the first embodiment, as shown in FIG. 3, a frame memory using four SDRAMs or four DDR-SDRAMs in parallel as the memory cell array 301 will be described as an example. Each memory cell array 301 is connected in parallel to an image processing apparatus (image processing LSI) 302 that performs memory control. The capacity of one memory cell array 301 is 64 Mbits, and the bus width is 16 bits. That is, when viewed as one frame memory, it has a bus width of 4 × 16 = 64 bits. Further, the data size of one page of each memory cell array 301 is 1024 bytes, and when viewed as one frame memory, the data size of one page is 4 × 1024 = 4096 bytes.

  Here, since one line of the image is 720 bytes, a maximum of 5 lines and 496 bytes of image data can be arranged on one page. Therefore, when 5 lines and 496 bytes of image data are arranged on one page, the image data is divided as shown in FIG.

  On the other hand, since the bus width is 64 bits, 16-byte data, that is, one line of data in a macroblock (rectangular area) can be transferred in two cycles (two burst transfer lengths). However, as described with reference to FIGS. 16 and 17 (a) to (c), in the above SDRAM, the number of banks (here, four) and the access interval (access inaccessible time), the two burst transfer length is the bank. Data access by switching cannot be performed continuously. Therefore, here, the image is divided so that data can be accessed in at least two lines of the macroblock in one page.

  With reference to FIGS. 5A to 5C, description will be given of macroblock access when image data is arranged so that two lines of a macroblock can be transferred from the same page in the SDRAM. FIG. 5A schematically shows a state in which data arranged on different pages in the banks 0 to 3 is accessed while switching banks.

  FIG. 5B shows the execution timing of each access. In this case, two lines of the macro block are continuously transferred from the same page by two read commands (Read). In this way, it is possible to perform precharge setting and active setting for another bank during data access in a certain bank, and the data bus operates without interruption as shown in FIG. Thus, high-speed data transfer becomes possible. In this way, if data access can be made to two lines of a macroblock within one page, macroblock access by bank switching can be made continuous access. Since scanning line access is data access within the same page, continuous access is always possible and data can be transferred at high speed.

  On the other hand, when the DDR-SDRAM is used as a memory cell array, similarly, as shown in FIGS. 6A to 6C, image data can be arranged so that at least three lines of a macroblock can be transferred from the same page. The data bus can be operated without interruption, and high-speed data transfer is possible. Similarly, scanning line access is data access within the same page, so continuous access is always possible and data can be transferred at high speed.

  In this example, a frame memory capable of storing 4096 bytes of data per page has been described as an example. However, if the image size is 720 pixels × 480 rows, 1440 bytes and 3 lines are stored instead of 2 lines. Therefore, the capacity of one page may be set to 1440 bytes or 2160 bytes. When the image size is, for example, 1080 pixels × 720 rows, a capacity of at least 1080 × 2 to 3 bytes per page is required. On the other hand, if the image data is divided in accordance with the page size (4096 bytes) as described above (if divided into 5 lines and 496 bytes), the memory space can be used effectively.

  Also, the number of accessible block lines is determined within the number of cycles required for continuous data access by bank switching, and the number of macroblock lines equal to or greater than the determined block line number divides the image. It may be included in the vertical direction of the region. In this way, continuous data access and high-speed data transfer can be realized even during data access (block access) in block units by bank switching, and the bandwidth can be used effectively.

(Embodiment 2)
Subsequently, an image data arrangement method according to the second embodiment will be described. The image data arrangement method according to the second embodiment is an arrangement method when the page size is insufficient with respect to the number of pixels X in the scanning line direction of the image.

  In the image data arrangement method, both scanning line access and macroblock access are continuously performed while switching banks. In other words, the number of cycles (time) required for continuous data access while switching banks is the number of banks (here, four), and access caused by precharge setting or active setting (predetermined setting). Interval (inaccessible time. Here, 3 cycles after precharge setting and 3 cycles after page setting are required, the access interval is 6 cycles) and the number of cycles required to access data in one line of the rectangular area ( This is determined based on the access time (here, 2 cycles as will be described later). Then, the image is divided and arranged on each page so that the number of lines in the rectangular area accessible within the determined number of cycles is included in the scanning line direction and the vertical direction of the divided area. FIG. 7 shows an example of dividing an image by the above method. FIG. 8 shows an example in which the image data divided by the above method is arranged on each page.

  This image data division / arrangement is executed by the image processing apparatus according to the execution program. For example, as shown in FIG. 7, Mpixel in the scanning line direction, N line (Nline) first divided region in the vertical direction, Mpixel in the scanning line direction adjacent to the first divided region, and Z in the vertical direction When it is determined to divide the image into step-like areas composed of the second divided areas of the row (Zline), the image processing apparatus divides the image data to be processed into the step-like areas. These are arranged on each page so that scanning line access and macroblock access can be executed by bank switching.

  In the second embodiment, a case where one SDRAM or DDR-SDRAM is used as a memory cell array will be described as an example. The memory cell array is connected to an image processing apparatus that performs memory control, and has a capacity of 64 Mbit and a bus width of 64 bits. The data size of one page of the memory cell array is 1024 bytes.

  Here, since one line of the image is 720 bytes, only about one line of image data can be arranged on each page. Therefore, the image data arrangement method for dividing the image along the scanning line as in the first embodiment is not suitable. .

  Therefore, in the second embodiment, as shown in FIG. 9, one line of the image is divided in units of 16 × Jbytes (pixels). The value of J at this time is a value necessary for at least data access by bank switching to be continuous access. Further, at least N lines are included in the vertical direction of the divided area of the image. The value of N at this time is also set to a value necessary for at least data access by bank switching to be continuous access. Then, it is arranged on each page so that the scanning line access and the macroblock access are executed by bank switching.

  That is, when the frame memory is the above-mentioned SDRAM, if the values of “J” and “N” are 2 or more, at least two read instructions can be executed continuously in one page. As explained, scanning line access and macroblock access can be made continuous data access (however, 2 burst transfer length).

  Similarly, when the frame memory is the DDR-SDRAM, if the values of “J” and “N” are 3 or more, at least three read commands can be executed continuously in one page. As described above, scanning line access and macroblock access can be made continuous data access (however, 2 burst transfer length).

If the image data is divided in accordance with the page data size (1024 bytes), the memory space can be used effectively.
In addition, the number of accessible block lines is determined within the number of cycles required for continuous data access by bank switching, and the image is divided by 16 × Jbyte lines greater than the determined block line number. It may be included in the vertical direction of the region. In this way, continuous data access and high-speed data transfer can be realized even during data access (block access) in block units by bank switching, and the bandwidth can be used effectively.

  As described above, according to the image data arrangement method in the first and second embodiments, continuous data access and high-speed data transfer can be realized in scanning line access, macroblock access, and block access, and the bandwidth can be effectively utilized. . Therefore, the present invention is effective for an image processing apparatus such as an LSI that performs image processing, a device or system including the image processing apparatus, and the like.

  According to the image data arrangement method according to the present invention, it is possible to realize continuous data access and high-speed data transfer in scanning line access, macroblock access, block access, effectively utilize bandwidth, and perform processing such as LSI that performs image processing. It is effective for an image processing apparatus, a device or system including the image processing apparatus, and the like.

The figure which shows the example of a division | segmentation of the image data in Embodiment 1 of this invention The figure which shows the example of arrangement | positioning to each page of the image data in Embodiment 1 of this invention The figure which shows the example of a connection of the image processing apparatus and frame memory in Embodiment 1 of this invention The figure which shows the example of a division | segmentation in the case of arrange | positioning the image data of 720 pixels x 480 rows in Embodiment 1 of this invention in the frame memory whose 1 page is 4096 bytes. The figure for demonstrating the macroblock access at the time of SDRAM use in Embodiment 1 of this invention (a) It represents typically changing a bank and accessing the data arrange | positioned at the different page in the banks 0-3. (B) Diagram showing execution timing of each access (c) Diagram showing signals appearing on control signal bus and data bus The figure for demonstrating the macroblock access at the time of DDR-SDRAM use in Embodiment 1 of this invention (a) A mode that it accesses while switching the bank to the data arrange | positioned at the different page in the banks 0-3 (B) Diagram showing execution timing of each access (c) Diagram showing signals appearing on control signal bus and data bus The figure which shows the example of a division | segmentation of the image data in Embodiment 2 of this invention The figure which shows the example of arrangement | positioning to each page of the image data in Embodiment 2 of this invention The figure which shows the example of a division | segmentation in the case of arrange | positioning the image data of 720 pixels x 480 rows in Embodiment 2 of this invention in the frame memory whose 1 page is 1024 bytes. Diagram for explaining scanning line access and macroblock access Diagram for explaining scanning line access and macroblock access The figure for demonstrating the conventional image data arrangement method The figure for demonstrating the data access with respect to the data arrange | positioned at the different page in the same bank of SDRAM. (A) The figure showing typically a mode that the data arrange | positioned at the different page in the bank 0 are accessed. Diagram showing access execution timing (c) Diagram showing signals appearing on control signal bus and data bus The figure for demonstrating the data access with respect to the data arrange | positioned in the different page in a different bank of SDRAM (a) A mode that it accesses, switching a bank to the data arrange | positioned in the different page in the bank 0-3 (B) Diagram showing execution timing of each access (c) Diagram showing signals appearing on control signal bus and data bus FIG. 4 is a diagram for explaining data access using a burst mode for data arranged on different pages in different banks of the SDRAM. (A) While switching banks to data arranged on different pages in banks 0 to 3, (B) Diagram showing access timing with burst transfer length (b) Diagram showing execution timing of each access (c) Diagram showing signals appearing on control signal bus and data bus The figure for demonstrating the data access using the burst mode with respect to the data arrange | positioned at the different page in the different bank of SDRAM. (A) While switching the bank to the data arrange | positioned at the different page in the bank 0-3, 3 (B) Diagram showing access timing with burst transfer length (b) Diagram showing execution timing of each access (c) Diagram showing signals appearing on control signal bus and data bus The figure for demonstrating the data access using the burst mode with respect to the data arrange | positioned at the different page in the different bank of SDRAM. (A) While switching the bank to the data arrange | positioned at the different page in the bank 0-3 (B) Diagram showing access timing with burst transfer length (b) Diagram showing execution timing of each access (c) Diagram showing signals appearing on control signal bus and data bus The figure for demonstrating the data access using the burst mode with respect to the data arrange | positioned at the different page in a different bank of DDR-SDRAM. (A) While switching the bank to the data arrange | positioned at the different page in the bank 0-3 (B) Diagram showing the access timing of each access (c) Diagram showing signals appearing on control signal bus and data bus

Explanation of symbols

301 memory cell array 302 image processing apparatus

Claims (8)

Each bank is composed of a plurality of banks that can be controlled independently, and the banks are divided into pages of a certain size. After a predetermined setting is made for each bank, random access is continuously performed within each predetermined page. For a frame memory capable of being divided, an image is divided along a scanning line and arranged on each page, and data access along a scanning line for each rectangular area of a specific size set in the image is performed as described above. An image data arrangement method that is performed while switching banks,
The time required for continuous data access while switching the banks is defined as the number of banks, the inaccessible time required for data access after the predetermined setting is made, and the rectangular It is determined based on the access time required for data access to one line in the scanning line direction of the area,
Dividing the image so that a number of lines of the rectangular area accessible within the determined time are included in a vertical direction of the divided area;
Placing the divided images on each page;
An image data arrangement method characterized by the above.   2. The image data arrangement method according to claim 1, wherein the image is divided in accordance with a page size.   The image data arrangement method according to claim 1, wherein the rectangular area is a macroblock. The image data arrangement method according to claim 3,
Determining the number of lines in the scanning line direction of a block which is an image processing unit smaller than the number of macroblocks accessible in the determined time;
The image data arrangement method, wherein the image is divided so that macroblock lines equal to or larger than the determined line number of the block are included in a vertical direction of the divided area of the image. Each bank consists of a plurality of banks that can be controlled independently. The banks are divided into pages of a certain size, and after a predetermined setting is made for each of the banks, random access is continuously performed within each predetermined page. An image data arrangement method in which an image is divided and arranged on each page with respect to a frame memory capable of
The time required for continuous data access while switching the bank is the number of banks, the inaccessible time required for data access after the predetermined setting is made, and the image Determined based on the access time required to access data in one line in the scanning line direction of a rectangular area of a specific size set to
Dividing the image such that the number of lines of the rectangular area accessible within the determined time are included in the scan line direction and the vertical direction of the area into which the image is divided;
Placing the divided images on each page;
An image data arrangement method characterized by the above.   6. The image data arrangement method according to claim 5, wherein the image is divided in accordance with a page size.   7. The image data arrangement method according to claim 5, wherein the rectangular area is a macro block. The image data arrangement method according to claim 7, wherein
Determining the number of lines in the scanning line direction of a block which is an image processing unit smaller than the number of macroblocks accessible in the determined time;
The image data arrangement method, wherein the image is divided so that macroblock lines equal to or larger than the determined line number of the block are included in a vertical direction of the divided area of the image.

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