JP2007299211A - Memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device which can shorten the read time of data from a memory by storing data in the memory so as to accelerate an access to the memory. <P>SOLUTION: The memory control device has: an allocation means for dividing image data in each prescribed macroblock and determining memory banks for storing respective data so that the data of a luminance block and the data of a color difference block are stored in respectively different memory banks; a specifying means 12 for specifying a memory cell included in the memory bank specified for each data of the luminance block and the color difference block by the allocation means 11 by using a memory bank address, a row address and a column address, outputting a first address including the memory bank address and the row address and outputting the memory bank address and the row address as a second address; and a writing means for outputting the data of the luminance block or the data of the color difference block which are to be written in the memory cell specified by the address specified by the specification means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory control device that controls access of image data to a memory.

  In recent years, a memory having a plurality of memory banks has been used. As described above, in a memory having a plurality of memory banks, data is stored in any one of the memory banks. A typical example of a memory having a plurality of memory banks is SDRAM (Synchronous Dynamic Random Access Memory). The SDRAM may be inexpensive, and is widely used in a main memory such as a personal computer, a frame memory of a compressed image decoder, and the like. DDR-SDRAM (Double Data Rate-SDRAM), which is a kind of SDRAM, can read and write data at twice the speed of SDRAM by accessing the memory in synchronization with both rising and falling edges of the clock. There is a feature that can be done.

  FIG. 8 shows a basic configuration of the DDR-SDRAM. As shown in FIG. 8A, the DDR-SDRAM includes four memory banks MB0 to MB3, a control circuit 21, and an I / O control circuit 22. Each of the memory banks MB0 to MB3 is an independently controllable memory, and data is stored in each memory bank.

  As shown in FIG. 8B, the memory bank MB0 has a plurality of memory cells 200 that are divided by a row address (row address) and a column address (column address). The memory bank MB0 shown in FIG. 8B is composed of (m + 1) × (n + 1) memory cells. A page 201 is constituted by memory cell groups having the same row address in the memory bank MB0. In the memory bank MB0 of FIG. 8B, a page 201 composed of (n + 1) memory cells whose row address is k is set as a page k. The other memory banks MB1 to MB3 also have the same plurality of memory cells as the memory bank MB0 shown in FIG. 8B (not shown).

  The control circuit 21 of the SDRAM receives “address” and “command” from an external memory control device. The control circuit 21 specifies a “bank address” for identifying a memory bank by an input address and a command, a “row address” for identifying a row, and a “column address” for identifying a column. Access a memory cell.

  In SDRAM, it is necessary to handle row addresses and column addresses in a time-sharing manner. In SDRAM, a delay cycle called “activation” is required when a row address is specified, and a delay cycle called “precharge” is required when moving to a different row address. Therefore, there is a limit to increasing the access speed in that different pages in the same memory bank cannot be accessed at high speed. This point has the same problem even in a DDR-SDRAM that allows high-speed access.

  2. Description of the Related Art Conventionally, when data is accessed in units of macroblocks in an SDRAM used as a frame memory of a compressed image decoder, there is a technology that devises a data storage method corresponding to each macroblock so as to control each memory bank independently. Yes (see, for example, Patent Document 1). In the technique described in Patent Document 1, a plurality of memory cells are partitioned corresponding to a rectangular block, and a continuous address is assigned to a memory cell in one block and stored. Access is fast.

  On the other hand, a compressed image such as MPEG uses a macroblock unit composed of a luminance block and a color difference block as a processing unit, and it is necessary to use the luminance data Y and the color difference data C when encoding or decoding the image. For example, in the case of the 4: 2: 0 format which is one of the image formats, as shown in FIG. 9A, the macroblock has a horizontal direction for luminance data Y of 16 pixels in the horizontal direction and 16 pixels in the vertical direction. It consists of color difference data Cb and Cr of 8 pixels and 8 pixels in the vertical direction. Further, as shown in FIG. 9B, in the case of a 4: 2: 2 macro block, the luminance data Y of 16 pixels in the horizontal direction and 16 pixels in the vertical direction are respectively set to 8 pixels in the horizontal direction and 16 pixels in the vertical direction. It consists of color difference data Cb and Cr.

  When compressing / decoding an image, it is necessary to read and write both the luminance data Y and the color difference data C corresponding to the same macroblock as described above. On the other hand, in the technique described in Patent Document 1 described above, if the luminance data Y and the color difference data C corresponding to one macroblock are stored in the same memory bank with the corresponding luminance data and color difference data, there is no delay cycle. Therefore, these data cannot be read out. That is, the access speed to the memory decreases.

In addition, when image data is decoded and displayed as an image, it is necessary to continuously access the data of each pixel constituting the image in the horizontal direction, so that the memory can be easily accessed in the horizontal direction. It is desirable to memorize.
Japanese Patent Laid-Open No. 11-137052

  Conventionally, even when the luminance data Y and the color difference data C are stored in the same memory bank even by the technique described in Patent Document 1, a delay cycle is required to read both data when decoding the image data. There was a problem that the access speed decreased.

  In view of the above problems, an object of the present invention is to provide a memory control device that shortens the reading time of image data including luminance data and color difference data from a memory having a plurality of memory banks.

  In order to solve the above-described problem, according to the first aspect of the present invention, a plurality of memory banks each including a plurality of memory cells specified by a memory bank address, a row address, and a column address are provided and supplied. A memory control device for controlling the storage of image data including luminance data and color difference data for a memory that obtains a memory bank address, a row address, and a column address from a first address and a second address and stores the data in a memory cell. The image data is divided into predetermined macroblock units as image areas, and the luminance block data and the color difference block data constituting the macroblocks of the divided image areas are stored in different memory banks. Allocation means for determining a memory bank for storing data, a luminance block, and a color difference block The memory cells included in the memory bank determined by the allocating means are designated by the memory bank address, the row address, and the column address, and the first address including the memory bank address and the row address is stored in the memory. The output means outputs the memory bank address and column address to the memory as the second address, and the luminance block data and color difference to be written in the memory cell specified by the bank address, row address and column address specified by the specifying means It is characterized by having writing means for outputting the data of the block to the memory and writing the respective data into each specified memory cell.

  According to the present invention, it is possible to provide a memory control device that shortens the reading time of image data including luminance data and color difference data from a memory having a plurality of memory banks.

<Memory control device>
Hereinafter, a memory control device 1 according to the preferred embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the memory control device 1 includes an allocation unit 11, a designation unit 12, a writing unit 13, and a reading unit 14. The memory control device 1 is connected to the memory 2 by a transmission path.

  When the memory control device 1 receives the write operation request, the memory control device 1 writes the image data in the memory area at the designated address in the memory 2. In addition, when a read operation request is input, the memory control device 1 reads image data from the memory area at the specified address in the memory 2. For example, the memory control device 1 is provided in a device such as a television or a video recorder having a function of writing or reading image data in a memory.

  The allocating means 11 divides the image data into predetermined macroblock units as image areas, and the luminance block data and the color difference block data constituting the macroblocks of the divided image areas are stored in different memory banks. The memory bank for storing each data is determined.

  The designation means 12 designates the memory cells included in the memory bank determined by the assignment means with respect to the data of each pixel of the luminance block and the color difference block by the memory bank address, the row address, and the column address. The designation unit 12 outputs a first address including a memory bank address and a row address, and outputs a second address including a memory bank address and a column address.

  The writing means 13 causes the luminance block data and the color difference block data to be written in the memory cells specified by the bank address, the row address, and the column address specified by the specifying means 12, respectively.

  The reading unit 14 reads luminance data and color difference data from the memory cell specified by the bank address, the row address, and the column address specified by the specifying unit 12.

  Since the data stored in the memory 2 by the memory control device 1 according to the preferred embodiment of the present invention is image data, “image data” is hereinafter simply referred to as “data”.

<Memory>
The memory 2 includes memory banks MB0 to MB3, a control circuit 21, and an I / O control circuit 22. The memory 2 has the same configuration as that of the DDR-SDRAM described above with reference to FIG. 8, and each of the memory banks MB0 to MB3 has the same configuration as that of the memory bank MB0 described above with reference to FIG. Therefore, description of each memory bank is omitted. The memory cell of each memory bank of the memory 2 is specified by “bank address”, “row address”, and “column address”. The control circuit 21 specifies a memory cell to be accessed from an address and a command output from the designation unit 12 of the memory control device 1. Thereafter, the control circuit 21 accesses the specified memory cell via the I / O control circuit 22.

  When specifying the memory cell to be accessed, the control circuit 21 specifies “bank address” and “row address” by the first address output from the memory control device 1, and sets “bank address” and “bank address” by the second address. Specify the “column address”. The “command” includes data for identifying whether the address is the first address or the second address, and the control circuit 21 of the memory 2 determines that the address is the first address or the address according to the command input together with the address. It is determined which of the second addresses.

  When the command identifies the first address (when the command is a so-called “bank active command”), the control circuit 21 determines that the address input together with the command is the first address. Therefore, the control circuit 21 obtains a “bank address” and a “row address” from this address (first address), specifies a bank and a page including a memory cell to be accessed, and activates this page. .

  When the command identifies the second address (when the command is a so-called “write command” or “read command”), the control circuit 21 determines that the address input together with the command is the second address. Judge that there is. Therefore, the control circuit 21 obtains the “bank address” and “column address” from this address (second address), specifies the column of the memory cell to be accessed from the activated page, and executes the access. To do.

  Similarly to the SDRAM described in FIG. 8B, the memory 2 to be accessed can access different memory banks without a delay cycle, but there is no delay cycle for different pages in the same memory bank. Cannot be accessed.

<Processing in memory control device>
As shown in the flowchart of FIG. 2, the allocating unit 11 of the memory control device 1 divides the image area of data to be stored in the memory 2 into predetermined macroblock units (1). After that, the allocating unit 11 determines a memory bank in which each data is stored so that the data of the luminance block and the color difference block of the macro block of each divided image area are stored in different memory banks (2).

  When the memory bank for storing each data of each luminance block and chrominance block is determined, the designating unit 12 stores the memory included in the memory bank determined by the allocating unit 11 for the data of each pixel of the luminance block and chrominance block. A cell address is designated (3). Thereafter, the writing means 13 or the reading means 14 transmits an address together with the command to access the memory location specified by the address of the memory 2 (4). In the memory 2, the row address or column address transmitted from the memory control device 1 is received together with the command, and data is written or read according to the received address and command.

<< Image area classification >>
Here, the process of classifying the image area executed in the assigning unit 11 will be described. For example, the data handled is H.264. When compression is performed using the H.246 / AVC compression method, the allocating unit 11 needs to divide a predetermined image area into macroblock units corresponding to the following conditions (1) to (3).

(1) H. In H.264 / AVC, a predicted image is generated based on data of 21 pixels in the horizontal direction and 21 pixels in the vertical direction at the maximum. For this reason, the image data of 21 pixels in the horizontal direction and 21 pixels in the vertical direction is allocated so that it can fit in at least four different memory banks.

(2) H. In H.264 / AVC, a mechanism called a macroblock pair is used, so that multiples of 2 macroblocks are allocated in one page in the vertical direction.

(3) In order to prevent an access penalty (delay cycle) from occurring at the time of reading, data of adjacent image areas are stored in different memory banks.

  In the image area divided in accordance with the above conditions (1) to (3), two or more macroblocks are secured in the horizontal direction in the image area of data stored in one memory bank, and the vertical direction is It is necessary to include 4 macroblocks or more. The reason why two or more macro blocks are required in the horizontal direction is that 21 pixels need to be contained within two banks. The reason why four or more macroblocks are required in the vertical direction is that it is necessary to fit a field line of 21 pixels within two banks in the vertical direction.

  FIG. 3 shows the correspondence in one frame between the luminance data Y and the color difference data C of the image in the 4: 2: 0 system. In FIG. 3A, the luminance data Y is indicated by ● and the color difference data C is indicated by ■. In FIG. 3A, Y [0] [0] represents the luminance data Y with the vertical line number 0 and the horizontal pixel address 0, and Cb [0] [0] and Cr [0] [0] are vertical. It represents color difference data C (Cb, Cr) having a line number of 0 and a horizontal pixel address of 0. As described above, in the data of one frame, the luminance data Y is 4 and the color difference data C (Cb, Cr) is 1 in proportion to the luminance data Y, and the color difference data C is 1/2 of the luminance data Y. It becomes the amount of data.

  As shown in FIG. 3B, the data is divided into luminance data Y, color difference data Cb, and color difference data Cr. When encoding, the luminance data Y of the luminance block and the color difference data C (Cb, Cb, Cr) and individually managed (FIG. 3C). Therefore, the color difference data Cb and the color difference data Cr are stored in the same memory area as shown in FIG.

Referring to FIG. An example in which the horizontal direction corresponding to H.246 / AVC is divided into a plurality of image areas having 2 macroblocks in the horizontal direction and 4 macroblocks in the vertical direction will be described.
In the example shown in FIG. 4A, in order to store the luminance data Y, it is divided into regions of 32 pixels in the horizontal direction and 64 lines in the vertical direction. In the following description, when the vertical line number y is 0 to 63, the horizontal pixel number x is 0 to 31, and the horizontal pixel number x is 32 to 63. The horizontal pixel number x is from 64 to 95 as region 3, and the horizontal pixel number x is from 96 to 127 as region 4. When the vertical line number y is from 64 to 127, the horizontal pixel number x is from 0 to 31 in the region 5, the horizontal pixel number x is from 32 to 63 in the region 6, and the horizontal pixel is It is assumed that the number x is from 64 to 95 as the region 7 and the horizontal pixel number x is from 96 to 127 as the region 8.

  By defining the image area for the luminance data Y as shown in FIG. The image area data corresponding to H.246 / AVC can be stored in the memory.

  FIG. 4B is an example in which the color difference data C (Cb, Cr) in the 4: 2: 0 format is divided. In the following description, in the 4: 2: 0 system, the color difference data C (Cb, Cr) of an image is divided into regions of 32 pixels in the horizontal direction and 128 lines in the vertical direction. In this way, the number of lines in the vertical direction is twice that in the case of the luminance data Y, as described with reference to FIG. 3, the ratio of the color difference data C is 4 with respect to the luminance data Y. This is because it is composed of 2 (1/2).

  In the following description, when the vertical line number y is 0 to 127, the horizontal pixel number x is 0 to 31, the region 9 is horizontal, and the horizontal pixel number x is 32 to 63, the region 10 is horizontal. A region 11 is a pixel number x in the direction from 64 to 95, and a region 12 is a pixel number x in the horizontal direction from 96 to 127. By defining the image area of the color difference data C as shown in FIG. Data can be stored in the memory corresponding to H.246 / AVC.

  FIG. 4C shows an example in which the color difference data C (Cb, Cr) in the 4: 2: 2 format is divided. In the following description, in the case of the 4: 2: 2 system, the color difference data C (Cb, Cr) of the image is divided into regions of 32 pixels in the horizontal direction and 64 lines in the vertical direction. In the case of the 4: 2: 2 system, since the luminance data Y is 4 and the ratio of the color difference data C is 4, the data amount of the luminance data Y and the color difference data C is the same. Therefore, the area is divided into 32 pixels in the horizontal direction and 64 lines in the vertical direction.

  In the following description, when the vertical line number y is 0 to 63, the horizontal pixel number x is 0 to 31, the region 13 is horizontal, and the horizontal pixel number x is 32 to 63, the region 14 is horizontal. A region 15 is a pixel number x in the direction from 64 to 95, and a region 16 is a pixel number x in the horizontal direction from 96 to 127. When the vertical line number y is from 64 to 127, the horizontal pixel number x is from 0 to 31 in the region 17, the horizontal pixel number x is from 32 to 63 in the region 18, and the horizontal pixel. It is assumed that the number x is from 64 to 95 as the region 19 and the horizontal pixel number x is from 96 to 127 as the region 20.

<< Determining the memory bank for each macroblock >>
With reference to FIG. 5, an example will be described in which the allocating unit 11 determines a memory bank for storing the luminance data Y and the color difference data C corresponding to each image area including a predetermined macroblock divided as shown in FIG. .

  In FIG. 5A, the allocation means 11 writes the luminance data Y of area 1 to the memory bank MB0, the luminance data Y of area 2 to the memory bank MB1, and the luminance data Y of area 3 to the memory bank MB2. The luminance data Y of the area 4 indicates that the memory bank is determined to be written in the memory bank MB3. Also, the allocation means 11 writes the luminance data Y of the area 5 into the memory bank MB2, writes the luminance data Y of the area 6 into the memory bank MB3, writes the luminance data Y of the area 7 into the memory bank MB0, and Data Y indicates that the memory bank is determined to be written in the memory bank MB1.

  In FIG. 5B, in the 4: 2: 0 format, the allocating unit 11 writes the color difference data C in the area 9 to the memory bank MB3, and writes the color difference data C in the area 10 to the memory bank MB0. 11 indicates that the memory bank is determined so that the color difference data C of 11 is written in the memory bank MB1 and the color difference data C of the area 12 is written in the memory bank MB2. Comparing the memory bank for the luminance data Y shown in FIG. 5A with the memory bank for the color difference data C shown in FIG. 5B, the luminance data Y and the color difference data C corresponding to the same pixel are different from each other. It can be seen that the decision was made to correspond to.

  In FIG. 5C, in the case of the 4: 2: 2 format, the allocating means 11 writes the color difference data C in the area 13 to the memory bank MB3, and writes the color difference data C in the area 14 to the memory bank MB0. 15 indicates that the memory bank is determined so that the color difference data of 15 is written to the memory bank MB1 and the color difference data C of the area 16 is written to the memory bank MB2. Comparing the memory bank for the luminance data Y shown in FIG. 5A with the memory bank for the color difference data C shown in FIG. 5C, the luminance data Y and the color difference data C corresponding to the same pixel are different from each other. It can be seen that the decision was made to correspond to.

In the 4: 2: 0 system, when the memory bank for each macroblock is determined as shown in FIGS. 4 (a), 4 (b), 5 (a) and 5 (b), the write A case in which the insertion unit 13 writes data will be described.
First, a case where the writing unit 13 writes data of pixel numbers 64 to 95 in the horizontal direction and line numbers 64 to 127 in the vertical direction will be described. Since the memory bank MB0 corresponds to the area 7 corresponding to the pixel numbers 64 to 95 in the horizontal direction and the line numbers 64 to 127 in the vertical direction, and the memory bank MB3 corresponds to the area 11, the writing means 13 writes the luminance data Y into the memory bank MB0 and writes the color difference data C into the memory bank MB3.

Next, a case where the writing unit 13 writes data of pixel numbers 96 to 127 in the horizontal direction and line numbers 64 to 127 in the vertical direction will be described. The memory bank MB1 corresponds to the region 8 corresponding to the pixel numbers 96 to 127 in the horizontal direction and the line numbers 64 to 127 in the vertical direction, and the memory bank MB0 corresponds to the region 12, so that the writing means 13 writes data to the memory bank MB1, and writes color difference data C to the memory bank MB0.
When the reading means 14 reads data, the writing means 13 reads the data written in this way.

In the case of the 4: 2: 2 method, when the memory bank for each macroblock is determined as shown in FIGS. 4 (a), 4 (c), 5 (a) and 5 (c), the write A case in which the insertion unit 13 writes data will be described.
First, a case where the writing unit 13 writes data of pixel numbers 0 to 32 in the horizontal direction and line numbers 0 to 63 in the vertical direction will be described. Since the memory bank MB0 corresponds to the area 1 corresponding to the pixel numbers 0 to 32 in the horizontal direction and the line numbers 0 to 63 in the vertical direction, and the memory bank MB3 corresponds to the area 13, The means 13 writes the luminance data Y into the memory bank MB0 and writes the color difference data C into the memory bank MB3.

Next, a case where the writing unit 13 writes data of pixel numbers 0 to 32 in the horizontal direction and line numbers 64 to 127 in the vertical direction will be described. Since the memory bank MB1 corresponds to the area 5 corresponding to the pixel numbers 0 to 32 in the horizontal direction and the line numbers 64 to 127 in the vertical direction, and the memory bank MB0 corresponds to the area 17, the writing means 13 writes the luminance data Y into the memory bank MB1 and the color difference data into the memory bank MB0.
When the reading means 14 reads data, the data written in this way by the writing means 13 is read from the corresponding memory cell.

  FIG. 6A shows an example in which macroblock data is determined to be stored in one page of the memory bank. Here, an example will be described in which 8 bits of data are written to one pixel in a memory bank having 32 bits of memory cells and 512 memory cells (number of column addresses) in a page.

  In FIG. 6, the unit of each memory cell is a column segment. Since there are 512 memory cells, one page consists of 512 column segments as shown in FIG. Here, since one pixel is 8 bits, data for four pixels can be written in one column segment (32 bits). Therefore, 64 column segments correspond to one macroblock (16 × 16 pixels), and data of eight macroblocks can be written in one page as shown in FIG.

  Each column segment can write luminance data or color difference data for four pixels. As shown in FIG. 6B, since luminance data for four pixels can be stored in one column segment, luminance data Y for four pixels is stored.

  Further, as shown in FIG. 6C, color difference data for four pixels can be stored in one column segment. As described in FIG. 3, a set of color difference blocks {Cb [n], Cr [n]} corresponds to luminance blocks {Y [2n], Y [2n + 1]} (n = 0, 1, 2,...). Therefore, a set of color difference blocks composed of the color difference data Cb and the color difference data Cr is written to the memory bank (FIG. 6C). In both the 4: 2: 0 format and the 4: 2: 2 format, the horizontal macroblocks in the page of the memory bank have two sets of luminance data Y and color difference data C (Cb, Cr). Regarding the vertical line direction, in the 4: 2: 0 system, 8 macroblocks that are twice the luminance data are allocated, and in the 4: 2: 2 system, the same 4 macroblocks as the luminance data are determined and allocated.

<< Address specification >>
Next, the case where the designation unit 12 designates the address of the memory 2 for the data of each pixel of the image will be described.

  The designation means 12 outputs the first address or the second address together with the command to the memory 2 to designate a memory cell to be accessed. The designation unit 12 uses (Formula 1) when outputting the first address including the row address. The designation unit 12 uses the case where the second address including the column address is output (Formula 2). The address is specified as follows:

Row address = α × Page_Y + Page_X (1)
Column address = 8 × Col_Y + Col_X (2)
Here, α in Expression (1) is determined in advance for each horizontal pixel size of an image displayed as data as shown in Table 1, and is stored in a memory (not shown) in the memory control device 1. Yes. For example, in the case of 1920 pixels of HDTV and 1088 vertical lines, α is “62” from Table 1.

Further, Page_X, Page_Y, Col_X, and Col_Y are obtained as described with reference to FIG.
Page_X and Col_X and the bank address Pel in Equation (1) or Equation (2) used when obtaining the row address and column address are obtained from the pixel numbers in the horizontal direction as shown in FIG. . According to FIG. 7A, when the horizontal pixel number is represented by 12 bits in binary notation, the upper 7 bits are used for Page_X. Also, middle 3 bits are used for Col_Y. The lower 2 bits are used as an address Pel for identifying a pixel in a segment for storing data.

  Page_Y and Col_Y in Equation (1) or Equation (2) used when obtaining the row address and column address are obtained from the line numbers in the vertical direction as shown in FIG. According to FIG. 7B, when the line number in the vertical direction is represented by 12 bits in binary notation, the upper 6 bits are used for Page_Y. Also, the lower 6 bits are used for Col_Y.

  Here, for example, when the luminance data Y having the vertical line number “117” and the horizontal pixel number “220” is written, the row address and the column address are obtained using equations (1) and (2). Will be described.

  The vertical line number “117” is “0000 — 0111 — 1101” in binary notation (12 bits). The horizontal pixel address “221” is “0000 — 1101 — 1101” in binary notation (12 bits). When the values of Expression (1) and Expression (2) are obtained based on the rules shown in FIG. 7, since Page_X is “0000 — 110”, “6” is obtained. Since Col_X is “1_11”, “7” is obtained. Since Pel is “01”, it is calculated as “1”. Since Page_Y is “0000 — 01”, “1” is obtained. Since Col_Y is “11 — 1101”, “53” is obtained.

  Here, when the horizontal size of the image is 720, referring to Table 1, the value of α is 26. Therefore, since the row address is α × Page_Y + Page_X according to the equation (1), “32” is obtained by 26 × 1 + 6. Further, since the column address is 8 × Col_Y + Col_X according to the expression (2), “431” is obtained by 8 × 53 + 7.

  As described above, the “first address” including the “bank address” which is the lower 2 bits of the “row address” obtained by the expression (1) and the upper bits of the “row address” obtained by the expression (1), and the expression ( The control circuit 21 that has input the “bank address” that is the lower 2 bits of the “row address” obtained in 1) and the “second address” including the “column address” obtained in the equation (2) from the designating unit 12, A memory cell is specified and access is performed to the specified memory cell.

  As described above, according to the preferred embodiment of the present invention, the luminance data Y of the same macro block and the color difference data C of the color difference block are stored in different memory banks, so that Efficient data access can be achieved without requiring an invalid cycle that occurs when transitioning from access to access to color difference data C.

  It goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a block diagram showing a memory control device and a memory connected to the memory control device according to the best embodiment of the present invention; FIG. It is a flowchart explaining the process of the memory control apparatus which concerns on best embodiment of this invention. The correspondence between the luminance data Y and the color difference data C of the image data in the 4: 2: 0 system format is shown. It is a figure explaining the process which classifies an image area | region with the memory control apparatus which concerns on best embodiment of this invention. It is a figure explaining an example in which the memory bank which memorize | stores the data of each image area was determined in the memory control apparatus which concerns on best embodiment of this invention. It is a figure explaining the page accessed with the memory control apparatus which concerns on best embodiment of this invention. It is a figure explaining the address utilized with the memory control apparatus which concerns on the best embodiment of this invention. It is a block diagram which shows the SDRAM which has several memory banks utilized conventionally. It is a figure which shows the macroblock conventionally utilized by image processing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory control apparatus 11 ... Allocation means 12 ... Designation means 13 ... Writing means 14 ... Reading means

Claims (1)

There are a plurality of memory banks composed of a plurality of memory cells specified by a memory bank address, a row address and a column address, and the memory bank address, the row address and the column are supplied from the supplied first address and second address. A memory control device that controls storage of image data including luminance data and color difference data for a memory that stores data in the memory cell by obtaining an address,
The image data is divided into predetermined macroblock units as image areas, and the luminance block data and color difference block data constituting the macroblocks of the divided image areas are stored in different memory banks, respectively. Allocating means for determining a memory bank for storing data; and for each data of the luminance block and the chrominance block, memory cells included in the memory bank determined by the allocating means are assigned a memory bank address, a row address, and Designating means for designating by a column address, outputting to the memory as a first address including the memory bank address and the row address, and outputting the memory bank address and the column address to the memory as a second address;
The luminance block data and the color difference block data to be written to the memory cell specified by the bank address, the row address and the column address specified by the specifying means are output to the memory, and the respective data are output to the memory. Writing means for writing to the specified memory cell;
A memory control device comprising:

Images