CN117907684A - Method and device for testing insulation resistance of multilayer chip ceramic capacitor - Google Patents
Method and device for testing insulation resistance of multilayer chip ceramic capacitor Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/025—Measuring very high resistances, e.g. isolation resistances, i.e. megohm-meters
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
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Abstract
The invention relates to the technical field of multilayer chip ceramic capacitors, in particular to a method and a device for testing the insulation resistance of a multilayer chip ceramic capacitor. According to the invention, the insulation resistance test of the multilayer chip ceramic capacitor is realized in a mode of gradually applying voltage, so that the impact on good products is reduced, the problem of potential damage to the good products caused by adopting high-voltage test in the test process is effectively avoided, the quality and reliability of products in the insulation resistance test process of the multilayer chip ceramic capacitor are ensured, the maintenance cost is reduced, and the overall efficiency of the whole equipment is improved.
Description
Technical Field
The invention relates to the technical field of multilayer chip ceramic capacitors, in particular to a method and a device for testing insulation resistance of a multilayer chip ceramic capacitor.
Background
The multilayer chip ceramic capacitor (MLCC) is a small electronic component capable of storing charges, and is widely applied to various fields of consumer electronics, vehicle-mounted, aerospace and the like, and in order to ensure the reliability of the multilayer chip ceramic capacitor in the use process, manufacturers can use a testing machine to carry out full-detection testing on products before leaving factories so as to remove defective products with unqualified capacity, loss and insulation resistance.
At present, a testing machine is generally used for directly applying high voltage which is several times or tens of times of rated voltage to a product to perform insulation resistance testing, and under the action of the high voltage, defective products with poor insulation resistance can be broken down and short-circuited or show insulation resistance which is obviously lower than good products, and then the defective products are screened out, however, the high voltage also can cause potential damage (such as layering, microcracks and the like) to the good products with normal insulation resistance, the potential damage is often difficult to discover, once the product containing the potential damage is sent to a customer, the potential defect is gradually developed in the use process of the product, so that the product is prematurely failed, and the whole machine equipment cannot normally operate, and therefore, the damage to the product caused by the high voltage in the testing process is very important to avoid.
Disclosure of Invention
The invention provides a method and a device for testing insulation resistance of a multilayer chip ceramic capacitor, which solve the technical problems that the traditional method for testing insulation resistance by MLCC high voltage can cause inconspicuous potential damage to good products with normal insulation resistance and influence normal use of products.
In order to solve the technical problems, the invention provides a method and a device for testing the insulation resistance of a multilayer chip ceramic capacitor.
In a first aspect, the present invention provides a method for testing insulation resistance of a multilayer chip ceramic capacitor, the method comprising the steps of:
Taking the electroplated multilayer chip ceramic capacitor as a multilayer chip ceramic capacitor to be tested, and progressively applying test voltages to the multilayer chip ceramic capacitor to be tested in a progressive pressurization mode according to the optimal progressive pressurization rate of each test voltage;
Performing insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage to obtain an insulation resistance value;
And comparing the insulation resistance value with a preset insulation threshold value, and determining whether the multilayer chip ceramic capacitor to be tested is good or not.
In a further embodiment, the test voltage is between 5 and 10 times the rated voltage of the multilayer chip ceramic capacitor to be tested.
In a further embodiment, the progressive pressurization mode employs linear pressurization and increases the test voltage at the optimal progressive pressurization rate, the optimal progressive pressurization rate being between 1 and 20V/ms.
In a further embodiment, the insulation threshold is calculated according to the capacitance of the multilayer chip ceramic capacitor to be measured, and the calculation formula of the insulation threshold is:
Wherein γ represents an insulation threshold; c represents the capacitance of the multilayer chip ceramic capacitor to be measured; alpha represents a time constant set point.
In a further embodiment, the time constant set point is 500mΩ·μf.
In a further embodiment, the multilayer chip ceramic capacitor to be tested is a multilayer chip ceramic capacitor of type II ceramic, and the thickness of the ceramic dielectric ranges from 1 μm to 5 μm;
the size of the multilayer chip ceramic capacitor to be tested is between British system 0603 and 1210.
In a further embodiment, the determining of the optimal progressive pressurization rate comprises:
Pre-selecting a plurality of electroplated multilayer chip ceramic capacitors as nondestructive testing samples, and determining the testing voltage of the test;
Under different progressive pressurization rates, progressively applying the test voltage of the test to the nondestructive testing sample in a progressive pressurization mode and performing insulation test to obtain the tested nondestructive testing sample;
And carrying out nondestructive testing on each tested nondestructive testing sample by different nondestructive testing methods, and determining the optimal progressive pressurization rate of the tested nondestructive testing sample under the testing voltage of the current test.
In further embodiments, the nondestructive testing method includes a breakdown voltage testing method, an ultrasonic flaw detection method, and an incipient fault detection method.
In a further embodiment, the step of determining the optimal progressive pressurization rate of each of the tested non-destructive test samples at the test voltage of the present test comprises:
When the breakdown voltage detection method is adopted, breakdown voltage tests are carried out on a first preset number of the tested nondestructive testing samples through a breakdown voltage tester, and the breakdown voltage bad proportion is determined;
When the ultrasonic flaw detection method is adopted, detecting a second preset number of nondestructive detection samples after the test by using an ultrasonic scanning microscope, and determining the poor proportion of ultrasonic flaw detection;
When the initial fault detection method is adopted, a third preset number of the tested nondestructive detection samples are placed in an oven with rated upper limit temperature, two ends of the tested nondestructive detection samples are connected with a direct current power supply and kept for a first preset connection time, an initial fault detection product is obtained, the initial fault detection product is placed in a constant-temperature constant-humidity box with the temperature of 85 ℃ and the humidity of 85%RH, the direct current power supply is connected with the second preset connection time, and the initial fault bad proportion is determined; the voltage value output by the direct current power supply is the rated voltage of a nondestructive testing sample;
and determining the optimal progressive pressurization rate of the tested nondestructive testing sample under the testing voltage of the current test according to the breakdown voltage bad proportion, the ultrasonic flaw detection bad proportion and the initial fault bad proportion.
In a second aspect, the present invention provides a test apparatus for insulation resistance of a multilayer chip ceramic capacitor, the test apparatus comprising:
The progressive pressurizing module is used for taking the electroplated multilayer chip ceramic capacitor as a multilayer chip ceramic capacitor to be tested, and progressively applying test voltages to the multilayer chip ceramic capacitor to be tested in a progressive pressurizing mode according to the optimal progressive pressurizing rate of each test voltage;
the insulation test module is used for conducting insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage to obtain an insulation resistance value;
and the good product detection module is used for comparing the insulation resistance value with a preset insulation threshold value and determining whether the multilayer chip ceramic capacitor to be detected is good or not.
The invention provides a method and a device for testing the insulation resistance of a multilayer chip ceramic capacitor, wherein the method gradually applies test voltages to the multilayer chip ceramic capacitor to be tested in a gradual pressurizing mode according to the optimal gradual pressurizing rate of each test voltage, and performs insulation test on the multilayer chip ceramic capacitor to be tested under the test voltages to obtain an insulation resistance value; and comparing the insulation resistance value with a preset insulation threshold value, and determining whether the multilayer chip ceramic capacitor to be tested is good or not. Compared with the traditional method of directly applying voltage in the testing process, the method reduces the impact on good products by adopting the gradual voltage application method, effectively avoids the problem of potential damage to good products by adopting high-voltage testing in the testing process, ensures the quality and reliability of products in the insulating resistance testing process of the multilayer chip ceramic capacitor, reduces the maintenance cost and the maintenance cost, and improves the overall efficiency of the whole equipment.
Drawings
FIG. 1 is a schematic flow chart of a method for testing insulation resistance of a multilayer chip ceramic capacitor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a progressive applied voltage provided by an embodiment of the present invention;
FIG. 3 is a block diagram of a test apparatus for insulation resistance of a multilayer chip ceramic capacitor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The following examples are given for the purpose of illustration only and are not to be construed as limiting the invention, including the drawings for reference and description only, and are not to be construed as limiting the scope of the invention as many variations thereof are possible without departing from the spirit and scope of the invention.
Referring to fig. 1, an embodiment of the present invention provides a method for testing insulation resistance of a multilayer chip ceramic capacitor, as shown in fig. 1, comprising the steps of:
s1, taking the electroplated multilayer chip ceramic capacitor as a multilayer chip ceramic capacitor to be tested, and progressively applying test voltages to the multilayer chip ceramic capacitor to be tested in a progressive pressurization mode according to the optimal progressive pressurization rate of each test voltage.
S2, performing insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage to obtain an insulation resistance value.
S3, comparing the insulation resistance value with a preset insulation threshold value, and determining whether the multilayer chip ceramic capacitor to be tested is good or not.
Because the traditional testing machine directly applies high voltage which is several times or tens of times of rated voltage to the multilayer chip ceramic capacitor (MLCC) when the MLCC is tested, and the mode of high direct voltage application can screen out defective products with poor insulation resistance, but also can cause inconspicuous layering, microcracks and other potential damages to good products with normal insulation resistance, the damages can be gradually displayed in the using process of the multilayer chip ceramic capacitor, the fault risk of the product in the using process is increased, the premature failure of the product can be caused, and the service life of the product is reduced.
In this embodiment, a plurality of electroplated multilayer chip ceramic capacitors (MLCCs) are selected as the multilayer chip ceramic capacitors to be tested, the multilayer chip ceramic capacitors to be tested are used for testing by a testing machine, as shown in fig. 2, when insulation resistance is tested, voltages at two ends of the multilayer chip ceramic capacitors to be tested are gradually pressurized from 0V to a set value of the test voltage in a gradual voltage application manner, then insulation resistance of the multilayer chip ceramic capacitors to be tested MLCCs is tested to obtain insulation resistance values, the insulation resistance values of the MLCCs are compared with a preset insulation threshold value, products with insulation resistance values higher than the insulation threshold value of the MLCCs are judged as good products, and products with insulation resistance values lower than the insulation threshold value of the MLCCs are judged as defective products.
In the insulation test process, the progressive pressurization mode adopted in the embodiment is linear pressurization, and the voltage at two ends of the multilayer chip ceramic capacitor to be tested is gradually increased to the set value of the test voltage at the optimal progressive pressurization rate, wherein the optimal progressive pressurization rate is between 1 and 20V/ms, and the set value of the test voltage is set between 5 and 10 times of the rated voltage (U0) of the MLCC of the multilayer chip ceramic capacitor to be tested.
The multilayer chip ceramic capacitor has a plurality of types of MLCC products, the MLCC can be divided into two types of products of I type porcelain (low capacitance series, secondary electricity) and II type porcelain (high capacitance series, ferroelectric), the multilayer chip ceramic capacitor to be detected selected in the embodiment is a multilayer chip ceramic capacitor of II type porcelain, the thickness range of ceramic medium is 1-5 mu m, and the size of the multilayer chip ceramic capacitor to be detected is between British system 0603-1210; in order to ensure the rationality of good product discrimination criteria, in this embodiment, an insulation resistance threshold of the MLCC is calculated according to a capacitance and a time constant set value of the multilayer chip ceramic capacitor to be tested, so as to obtain an insulation threshold, where a calculation formula of the insulation threshold is as follows:
wherein γ represents an insulation threshold; c represents the capacitance of the multilayer chip ceramic capacitor to be measured; α represents a time constant set value, which is preferably set to 500mΩ·μf in this embodiment.
In this embodiment, different nondestructive testing methods are adopted to test the tested good product (nondestructive testing sample), and the fastest pressurizing rate of the nondestructive testing sample under the condition that no bad product appears is determined as the optimal progressive pressurizing rate, and the determining process of the optimal progressive pressurizing rate includes:
The method comprises the steps of selecting a plurality of electroplated multilayer chip ceramic capacitors as nondestructive testing samples in advance, enabling the nondestructive testing samples to be the same type as the multilayer chip ceramic capacitors to be tested, determining testing voltage of the test, gradually applying the testing voltage of the test to the nondestructive testing samples in a gradual pressurizing mode under different gradual pressurizing rates, performing insulation testing to obtain tested nondestructive testing samples, performing nondestructive testing on each tested nondestructive testing sample through different nondestructive testing methods, and determining optimal gradual pressurizing rate of the tested nondestructive testing samples under the testing voltage of the test.
In this embodiment, the nondestructive testing method includes a breakdown voltage testing method, an ultrasonic flaw detection method, and an initial failure testing method, so that the step of performing nondestructive testing on each of the tested nondestructive testing samples by different nondestructive testing methods to determine an optimal progressive pressurization rate of the tested nondestructive testing samples under the test voltage of the present test includes:
When the breakdown voltage detection method is adopted, breakdown voltage tests are carried out on a first preset number of the tested nondestructive testing samples through a breakdown voltage tester, and the breakdown voltage bad proportion is determined;
When the ultrasonic flaw detection method is adopted, detecting a second preset number of nondestructive detection samples after the test by using an ultrasonic scanning microscope, and determining the poor proportion of ultrasonic flaw detection;
When the initial fault detection method is adopted, a third preset number of the tested nondestructive detection samples are placed in an oven with rated upper limit temperature, two ends of the tested nondestructive detection samples are connected with a direct current power supply and kept for a first preset connection time, an initial fault detection product is obtained, the initial fault detection product is placed in a constant-temperature constant-humidity box with the temperature of 85 ℃ and the humidity of 85%RH, the direct current power supply is connected with the second preset connection time, and the initial fault bad proportion is determined; the voltage value output by the direct current power supply is the rated voltage of a nondestructive testing sample;
and determining the optimal progressive pressurization rate of the tested nondestructive testing sample under the testing voltage of the current test according to the breakdown voltage bad proportion, the ultrasonic flaw detection bad proportion and the initial fault bad proportion.
In order to further verify the progressive pressurization test method provided in this embodiment, and analyze the optimal progressive pressurization rate determination process, this embodiment uses a multi-layer chip ceramic capacitor with a english system 0805 size, an X5R temperature characteristic, a 10V rated voltage, and a 10 μf capacitance as an example, uses a tester to test a plurality of electroplated MLCCs, uses different progressive pressurization rates to test insulation resistance of the products under each test voltage, and tests the tested MLCCs by using a breakdown voltage detection method, an ultrasonic flaw detection method, and an initial fault detection method, wherein the three non-destructive detection methods include:
Breakdown voltage: selecting 100 tested nondestructive test samples MLCC, using a breakdown voltage tester to perform breakdown voltage test, and recording the breakdown voltage bad proportion, wherein the breakdown voltage is lower than a breakdown voltage threshold value, the breakdown voltage threshold value is set to be 8 x U0, and U0 is the rated voltage of the multilayer chip ceramic capacitor MLCC.
Ultrasonic flaw detection: and selecting 2000 tested nondestructive testing samples MLCC, detecting by using an ultrasonic scanning microscope, and recording the ultrasonic flaw detection bad proportion.
Initial failure: selecting 1000 tested non-destructive testing samples MLCC, placing the MLCC in an oven with rated upper limit temperature, switching on a direct current power supply of U0 for 100h, placing the MLCC in a 85 ℃ and 85% RH box, switching on the direct current power supply of U0 for 24h, and recording the proportion of poor initial failure (after initial failure, the insulation resistance of the MLCC is less than 1 multiplied by 10 6 Ω) of the product.
In this embodiment, qualified MLCC products are divided into a plurality of different numbers of products, the different numbers of products are subjected to non-destructive testing, so as to analyze the poor proportion of the direct pressurizing mode and the progressive pressurizing mode, and determine the optimal progressive pressurizing rate according to the poor proportion of the different non-destructive testing methods, where table 1 shows different non-destructive testing methods and corresponding testing results of the MLCCs, and table 1 shows that:
TABLE 1
In comparative examples 1 and 2, the present example used the conventional direct high voltage pressurization method to perform insulation resistance test on the multilayer chip ceramic capacitor at 70V and 90V, and it can be seen from table 1 that the bad proportion of the multilayer chip ceramic capacitor at the 90V test voltage is significantly higher than that of the multilayer chip ceramic capacitor at the 70V test voltage, which indicates that the high voltage may cause potential damage to the product.
In examples 1 to 4, the insulation resistance test was performed on the multilayer chip ceramic capacitor at 70V using different progressive pressurization rates, and as can be seen from table 1, the defective proportion of the multilayer chip ceramic capacitor tested by the progressive pressurization method is better than that of the conventional direct pressurization method, which indicates that the progressive pressurization method can effectively reduce the damage of high voltage to the multilayer chip ceramic capacitor, and in addition, the multilayer chip ceramic capacitor has no defective product at a pressurization rate of 1 to 10V/ms, so that it can be determined that the pressurization rate of 10V/ms is the optimal progressive pressurization rate under the test voltage condition of 70V, and the optimal progressive pressurization rate of the chip under the test voltage of the test is obtained.
Meanwhile, in examples 5 to 8, the insulation resistance test was performed on the multilayer chip ceramic capacitor at 90V using different progressive pressurization rates, and as can be seen from table 1, the defective proportion of the multilayer chip ceramic capacitor tested by the progressive pressurization method is better than that of the conventional direct pressurization method, similar to the condition of 70V test voltage, and at the same time, the defective proportion of the multilayer chip ceramic capacitor gradually increases with increasing progressive pressurization rate, and the multilayer chip ceramic capacitor has no defective product only at a pressurization rate of 1V/ms, so that it can be determined that the pressurization rate of 1V/ms is the optimal progressive pressurization rate at the test voltage of 90V, and the optimal progressive pressurization rate of the chip at the test voltage of the test is obtained.
The embodiment of the invention provides a method for testing the insulation resistance of a multilayer chip ceramic capacitor, which comprises the steps of gradually applying test voltages to the multilayer chip ceramic capacitor to be tested in a gradual pressurizing mode according to the optimal gradual pressurizing rate of each test voltage, performing insulation test on the multilayer chip ceramic capacitor to be tested under the test voltages to obtain an insulation resistance value, comparing the insulation resistance value with a preset insulation threshold value, and determining whether the multilayer chip ceramic capacitor to be tested is good or not. Compared with the mode of directly applying high voltage in the traditional testing process, the progressive voltage applying mode adopted by the embodiment can reduce impact damage to the to-be-tested multilayer chip ceramic capacitor belonging to good products, not only improves testing accuracy, but also effectively avoids potential damage to the good products caused by high testing voltage, meanwhile, the to-be-tested multilayer chip ceramic capacitor belonging to the good products can be prevented from being misjudged as a bad product due to the potential damage, reliability of the product is ensured, faults or failure conditions caused by the potential damage to the product due to the application of high voltage in the use process of the product are avoided, maintenance cost and maintenance cost are reduced, and integral efficiency of equipment is improved.
It should be noted that, the sequence number of each process does not mean that the execution sequence of each process is determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
In one embodiment, as shown in fig. 3, an embodiment of the present invention provides a test apparatus for insulation resistance of a multilayer chip ceramic capacitor, the test apparatus comprising:
the progressive pressurization module 101 is configured to take the electroplated multilayer chip ceramic capacitor as a multilayer chip ceramic capacitor to be tested, and progressively apply test voltages to the multilayer chip ceramic capacitor to be tested in a progressive pressurization manner according to an optimal progressive pressurization rate of each test voltage;
the insulation test module 102 is configured to perform insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage, so as to obtain an insulation resistance value;
And the good product detection module 103 is used for comparing the insulation resistance value with a preset insulation threshold value to determine whether the multilayer chip ceramic capacitor to be detected is good or not.
For specific limitations on a device for testing insulation resistance of a multilayer chip ceramic capacitor, reference may be made to the above-mentioned limitations on a method for testing insulation resistance of a multilayer chip ceramic capacitor, and details thereof will not be repeated here. Those of ordinary skill in the art will appreciate that the various modules and steps described in connection with the disclosed embodiments of the application may be implemented in hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The embodiment of the application provides a device for testing the insulation resistance of a multilayer chip ceramic capacitor, which realizes progressive application of test voltage to the multilayer chip ceramic capacitor to be tested through a progressive pressurization module; performing insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage through an insulation test module to obtain an insulation resistance value; and comparing the insulation resistance value with a preset insulation threshold value through a good product detection module, and determining whether the multilayer chip ceramic capacitor to be detected is good or not. Compared with the existing direct-applied high-voltage testing technology, the method has the advantages that when the insulation resistance is tested, the voltage at the two ends of the multilayer chip ceramic capacitor is increased from 0V to the testing voltage in a gradual voltage application mode, so that the insulation resistance of a product can be more accurately detected, potential damage to the product caused by direct application of high voltage is avoided, the quality and reliability of the product are improved, normal operation of equipment is guaranteed, the service life is prolonged, meanwhile, maintenance cost and maintenance cost are reduced, and the economic benefit of the product is improved.
FIG. 4 is a diagram of a computer device including a memory, a processor, and a transceiver connected by a bus, according to an embodiment of the present invention; the memory is used to store a set of computer program instructions and data and the stored data may be transferred to the processor, which may execute the program instructions stored by the memory to perform the steps of the above-described method.
Wherein the memory may comprise volatile memory or nonvolatile memory, or may comprise both volatile and nonvolatile memory; the processor may be a central processing unit, a microprocessor, an application specific integrated circuit, a programmable logic device, or a combination thereof. By way of example and not limitation, the programmable logic device described above may be a complex programmable logic device, a field programmable gate array, general purpose array logic, or any combination thereof.
In addition, the memory may be a physically separate unit or may be integrated with the processor.
It will be appreciated by those of ordinary skill in the art that the structure shown in FIG. 4 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be implemented, and that a particular computer device may include more or fewer components than those shown, or may combine some of the components, or have the same arrangement of components.
In one embodiment, an embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above-described method.
The test method and the device for the insulation resistance of the multilayer chip ceramic capacitor provided by the embodiment of the invention have the advantages that the test voltage is applied in a gradual pressurizing mode under the optimal gradual pressurizing rate, the situation that the product is damaged or fails too early due to potential damage caused by high voltage is avoided, the fault risk of the product in the using process is reduced, the service life of the multilayer chip ceramic capacitor is prolonged, the maintenance cost is reduced, the overall efficiency of the whole equipment is improved, safety accidents are easy to generate in the traditional mode of directly applying high voltage, and the dangerous situation caused by directly applying high voltage in the operating process is reduced by the test method based on the gradual pressurizing mode, so that the operation safety is ensured, and the occurrence of accidents is avoided.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), etc.
Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed, may comprise the steps of embodiments of the methods described above.
The foregoing examples represent only a few preferred embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present application, and such modifications and substitutions should also be considered to be within the scope of the present application. Therefore, the protection scope of the patent of the application is subject to the protection scope of the claims.
Claims (10)
1. The method for testing the insulation resistance of the multilayer chip ceramic capacitor is characterized by comprising the following steps of:
Taking the electroplated multilayer chip ceramic capacitor as a multilayer chip ceramic capacitor to be tested, and progressively applying test voltages to the multilayer chip ceramic capacitor to be tested in a progressive pressurization mode according to the optimal progressive pressurization rate of each test voltage;
Performing insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage to obtain an insulation resistance value;
And comparing the insulation resistance value with a preset insulation threshold value, and determining whether the multilayer chip ceramic capacitor to be tested is good or not.
2. The method for testing insulation resistance of a multilayer chip ceramic capacitor as defined in claim 1, wherein: the test voltage is 5-10 times of the rated voltage of the multilayer chip ceramic capacitor to be tested.
3. The method for testing insulation resistance of a multilayer chip ceramic capacitor as defined in claim 1, wherein: the progressive pressurization mode adopts linear pressurization and increases the test voltage at the optimal progressive pressurization rate, and the optimal progressive pressurization rate is between 1 and 20V/ms.
4. The method for testing insulation resistance of a multilayer chip ceramic capacitor according to claim 1, wherein the insulation threshold is calculated according to capacitance of the multilayer chip ceramic capacitor to be tested, and a calculation formula of the insulation threshold is:
Wherein γ represents an insulation threshold; c represents the capacitance of the multilayer chip ceramic capacitor to be measured; alpha represents a time constant set point.
5. The method for testing insulation resistance of a multilayer chip ceramic capacitor according to claim 4, wherein: the time constant set value is 500MΩ·μF.
6. The method for testing insulation resistance of a multilayer chip ceramic capacitor as defined in claim 1, wherein: the multilayer chip ceramic capacitor to be tested is a multilayer chip ceramic capacitor of type II ceramic, and the thickness range of a ceramic medium is 1-5 mu m;
the size of the multilayer chip ceramic capacitor to be tested is between British system 0603 and 1210.
7. The method for testing insulation resistance of a multilayer chip ceramic capacitor according to claim 1, wherein said determining of said optimal progressive pressurization rate comprises:
Pre-selecting a plurality of electroplated multilayer chip ceramic capacitors as nondestructive testing samples, and determining the testing voltage of the test;
Under different progressive pressurization rates, progressively applying the test voltage of the test to the nondestructive testing sample in a progressive pressurization mode and performing insulation test to obtain the tested nondestructive testing sample;
And carrying out nondestructive testing on each tested nondestructive testing sample by different nondestructive testing methods, and determining the optimal progressive pressurization rate of the tested nondestructive testing sample under the testing voltage of the current test.
8. The method for testing insulation resistance of a multilayer chip ceramic capacitor as defined in claim 7, wherein: the nondestructive testing method comprises a breakdown voltage testing method, an ultrasonic flaw detection method and an initial fault detection method.
9. The method for testing the insulation resistance of a multilayer chip ceramic capacitor according to claim 8, wherein said step of performing a nondestructive test on each of said tested nondestructive test samples by different nondestructive testing methods to determine an optimal progressive pressurization rate of said tested nondestructive test samples at the test voltage of the present test comprises:
When the breakdown voltage detection method is adopted, breakdown voltage tests are carried out on a first preset number of the tested nondestructive testing samples through a breakdown voltage tester, and the breakdown voltage bad proportion is determined;
When the ultrasonic flaw detection method is adopted, detecting a second preset number of nondestructive detection samples after the test by using an ultrasonic scanning microscope, and determining the poor proportion of ultrasonic flaw detection;
When the initial fault detection method is adopted, a third preset number of the tested nondestructive detection samples are placed in an oven with rated upper limit temperature, two ends of the tested nondestructive detection samples are connected with a direct current power supply and kept for a first preset connection time, an initial fault detection product is obtained, the initial fault detection product is placed in a constant-temperature constant-humidity box with the temperature of 85 ℃ and the humidity of 85%RH, the direct current power supply is connected with the second preset connection time, and the initial fault bad proportion is determined; the voltage value output by the direct current power supply is the rated voltage of a nondestructive testing sample;
and determining the optimal progressive pressurization rate of the tested nondestructive testing sample under the testing voltage of the current test according to the breakdown voltage bad proportion, the ultrasonic flaw detection bad proportion and the initial fault bad proportion.
10. A test apparatus for insulation resistance of a multilayer chip ceramic capacitor, the test apparatus comprising:
The progressive pressurizing module is used for taking the electroplated multilayer chip ceramic capacitor as a multilayer chip ceramic capacitor to be tested, and progressively applying test voltages to the multilayer chip ceramic capacitor to be tested in a progressive pressurizing mode according to the optimal progressive pressurizing rate of each test voltage;
the insulation test module is used for conducting insulation test on the multilayer chip ceramic capacitor to be tested under the test voltage to obtain an insulation resistance value;
and the good product detection module is used for comparing the insulation resistance value with a preset insulation threshold value and determining whether the multilayer chip ceramic capacitor to be detected is good or not.
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| CN202410012306.2A CN117907684A (en) | 2024-01-02 | 2024-01-02 | Method and device for testing insulation resistance of multilayer chip ceramic capacitor |
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| CN202410012306.2A CN117907684A (en) | 2024-01-02 | 2024-01-02 | Method and device for testing insulation resistance of multilayer chip ceramic capacitor |
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