CN117892673B - Timing sequence convergence structure and method based on register and digital-analog hybrid chip - Google Patents
Timing sequence convergence structure and method based on register and digital-analog hybrid chip Download PDFInfo
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Abstract
The invention discloses a timing sequence convergence structure and method based on a register and a digital-analog hybrid chip, comprising the following steps: the starting zone bit registers are connected in series between the analog side and the digital side, and are sequentially connected; at least one set of buffer registers connected in series between the analog side and the digital side; the multiplexers are in one-to-one correspondence with the cache register sets, are connected with the output ends of the cache register sets, and are sequentially connected; the enabling end of the first reading register is connected with the output end of a group of starting zone bit registers, and the output end of the first reading register is connected with one of the multiplexers. According to the scheme, the time sequence convergence power consumption is reduced, the back-end time sequence convergence time is shortened, the chip area is reduced, and the chip utilization rate is improved.
Description
Technical Field
The invention relates to the field of signals, in particular to a register-based timing sequence convergence structure, a timing sequence convergence verification method and a digital-analog hybrid chip.
Background
The existing timing sequence convergence method needs that the front end and the back end try the scheme together to reach the convergence condition: at the beginning of design, the cascade length of the clock tree and the register chain cannot be accurately estimated due to the influences of area, layout, noise and the like, and the cascade length can be determined only when the project is late. Modifying the time taken for code re-synthesis introduces a significant amount of iteration time.
When the register data size reaches a certain level, a large amount of power consumption and area waste are introduced: in existing digital-to-analog designs, the interface may be up to several kilobits wide, introducing multiple stages of timing convergence registers may introduce dynamic power consumption of up to several hundred milliwatts.
Disclosure of Invention
In order to solve the technical problems, the invention provides a timing sequence convergence structure, a timing sequence convergence method and a digital-analog hybrid chip based on a register, which reduces the timing sequence convergence power consumption and improves the chip utilization rate.
Specifically, the technical scheme of the invention is as follows:
a register-based timing closure structure, comprising:
The starting zone bit registers are connected in series between the analog side and the digital side, and are sequentially connected;
at least one set of buffer registers connected in series between the analog side and the digital side;
The multiplexers are in one-to-one correspondence with the cache register sets, are connected with the output ends of the cache register sets, and are sequentially connected;
The enabling end of the first reading register is connected with the output end of a group of starting zone bit registers, and the output end of the first reading register is connected with each multiplexer;
The input end of the second reading register is connected with the multiplexer, and the output end of the second reading register is connected with the analog side;
a write address register connected in series between the analog side and the digital side.
And setting a group of starting zone bit registers and a first reading register, wherein the input ends of the starting zone bit registers are connected with the digital side, and the output ends of the starting zone bit registers are connected with the enabling ends of the first reading register. When the data of the digital side enters the starting zone bit register, the address writing register starts to write the data of the digital side into the cache register; when the data of the digital side enters the first reading register through the start flag bit register, the second reading register reads the data cached by the corresponding cache register through the multiplexer. In this embodiment, only the first-stage buffer register and the second read register may introduce flip, so that power consumption of timing convergence is greatly reduced. Meanwhile, compared with the traditional scheme, the number of the used registers and the number of clock trees are greatly reduced, the utilization rate of the digital-analog hybrid chip is improved, and the resource waste is reduced.
In some embodiments, the clock tree length of each of the enable bit registers is stepped down.
In some embodiments, the write address register is configured to write the data sent by the digital side into one of the columns of cache registers in the cache register set.
In some embodiments, the second read register is configured to select, by using the multiplexer, data buffered in one of the corresponding buffer register sets to read.
In some embodiments, the clock tree length of the buffer register set is consistent with the clock domain of the digital side input data function, and the second read register clock tree length and the first read register clock tree length are consistent with the clock domain of the analog side input data function.
The invention also provides a timing sequence convergence verification method applied to the timing sequence convergence structure based on the register in the previous embodiment, which is characterized by comprising the following steps:
Transmitting first initial data to the starting zone bit register through the digital side, wherein the first initial data is a starting signal;
When the starting zone bit register receives the first initial data, controlling the write address register to write second initial data into the cache register group;
Controlling the start flag bit register to send the first initial data to a first reading register;
when the first reading register receives the first initial data, the second reading register is controlled to read the second initial data cached by the cache register set through a first preset time;
When a group of the starting zone bit registers and the first reading registers finish timing sequence convergence through a preset timing sequence convergence model, determining constraint of static timing sequence analysis according to a first timing sequence beat number in the timing sequence convergence process of the group of the starting zone bit registers and the first reading registers;
Judging whether the time sequence convergence structure based on the register is in violation or not according to the constraint of the static time sequence analysis, the second initial data cached by the cache register group and the second initial data read by the second reading register;
if no timing violation exists, judging that the timing convergence of the register-based timing convergence structure is successful.
And constructing a timing sequence convergence model through a calculation flow by using the start zone bit register and the first reading register, and automatically enabling the buffer register group to execute timing sequence convergence operation according to the timing sequence convergence model through a tool. The working pressure of a developer is greatly reduced, the utilization rate of a chip is improved, and the time sequence convergence power consumption is further reduced.
In some embodiments, after the controlling the second read register to read the second initial data buffered in the buffer register set for a first preset time, the method further includes the steps of:
Setting a timing sequence convergence window according to the column number of the cache register group;
Judging whether second initial data cached by the cache register group is consistent with second initial data read by the second reading register or not according to the timing sequence convergence window in a preset environment;
And if the timing sequence is consistent, judging that the timing sequence convergence based on the register is successful.
In some embodiments, the controlling the write address register to write the second initial data into the cache register set specifically includes the steps of:
and controlling the write address register to write partial data in the second initial data into one column of cache registers in the cache register group.
In some embodiments, the controlling the second read register to read the second initial data buffered in the buffer register set after a first preset time specifically includes the steps of:
and controlling the second reading register to select partial second initial data cached by one row of cache registers in the corresponding cache register group through the multiplexer for reading.
The invention also provides a digital-analog hybrid chip, which comprises the timing sequence convergence structure in the embodiment.
Compared with the prior art, the invention has at least one of the following beneficial effects:
1. And setting a group of starting zone bit registers and a first reading register, wherein the input ends of the starting zone bit registers are connected with the digital side, and the output ends of the starting zone bit registers are connected with the enabling ends of the first reading register. When the data of the digital side enters the starting zone bit register, the address writing register starts to write the data of the digital side into the cache register; when the data of the digital side enters the first reading register through the start flag bit register, the second reading register reads the data cached by the corresponding cache register through the multiplexer. In this embodiment, only the first-stage buffer register and the second read register may introduce flip, so that power consumption of timing convergence is greatly reduced. Meanwhile, compared with the traditional scheme, the number of the used registers and the number of clock trees are greatly reduced, the area of the digital-analog hybrid chip is reduced, the utilization rate of the digital-analog hybrid chip is improved, and the resource waste is reduced. Meanwhile, the manual design complexity of timing sequence convergence is greatly reduced, and the use power consumption of the chip is reduced.
2. And constructing a timing sequence convergence model through a calculation flow by using the start zone bit register and the first reading register, and determining a static timing sequence analysis constraint. And automatically judging whether the timing sequence convergence structure successfully completes the timing sequence convergence or not through a static timing sequence analysis tool. The working pressure of a developer is greatly reduced, the utilization rate of a chip is improved, and the time sequence convergence power consumption is further reduced.
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The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a block diagram of one embodiment of a register-based timing closure structure of the present invention;
FIG. 2 is a flow chart of one embodiment of a timing closure verification method of the present invention;
FIG. 3 is a flow chart of another embodiment of a timing closure verification method of the present invention;
FIG. 4 is a block diagram of a timing closure structure in the prior art;
FIG. 5 is a timing closure window diagram of the prior art;
FIG. 6 is a timing closure window diagram of the present invention;
FIG. 7 is a block diagram of another embodiment of a register-based timing closure structure of the present invention.
Description of the drawings: a start flag register 100; a cache register 200; a multiplexer 300; a first read register 400; a second read register 500; address register 600 is written.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
The functions of the digital-analog hybrid chip are continuously increased, a large number of digital and analog modules exist in the same chip, the placement position of digital analog is affected by function arrangement, the interference problem is solved, and the like, and the trend of increasing complexity is presented, so that the implementation requirements on the digital modules are continuously improved.
The increase in digital part area complicates the design of the clock tree, with the average length of the digital clock tree being proportional to the logic driven. The digital clock frequency becomes faster and faster as the process continues to advance, and the situation where the digital-to-analog interface clock frequency exceeds GHz (10 x 9 flip/s) is common.
Since digital circuit designs must ensure functional correctness at each clock cycle and must be applicable at different process corners, there must be a way to account for digital-to-analog clock delay differences. However, due to the improvement of the complexity of the chip functions, the length of the digital clock tree cannot be constrained, and the power consumption and the area consumption of the traditional solution become too high to affect the competitiveness of the chip.
As shown in fig. 4, the existing solution for timing convergence is to determine the data connection positions of the digital side and the analog side, then to complete the layout and PR (Place placement standard unit and Route winding) of the digital module, then to determine the length of the clock tree according to the result of the digital static timing analysis, and to adjust the number and positions of the interface registers. Typically, the analog clock delay is very small and all later adjustments are done on the digital side. However, the existing timing convergence solution has many problems, for example, at the beginning of design, due to the influences of area, layout, noise, etc., the cascade length of the clock tree and the register chain cannot be accurately estimated, and the clock tree and the register chain can be determined only when the project is late. Modifying the time spent for code re-synthesis introduces a significant amount of iteration time; when the data volume reaches a certain degree, a great amount of power consumption and area waste are introduced: in existing digital-to-analog designs, the interface may be up to several kilobits wide, introducing multiple stages of timing convergence registers may introduce dynamic power consumption of up to several hundred milliwatts.
Further, referring to fig. 5, in the prior art, since the timing convergence window is one clock period, as shown in the figure, the data arriving at the sampling register has relatively large uncertainty with respect to the clock of the sampling register under different process angles (the actual situation also needs to consider that the clock tree delay is more complex); the data 200_min_counter refers to the position where the data arrives at the fastest process corner, the data200_max_ coner refers to the position where the data arrives at the register at the slowest process corner, and in order to meet the requirement that the timing convergence window is in the PR stage (Place placement standard cells and Route windings), a great deal of time is consumed to manually intervene in the layout of the clock tree, the layout of the register chain, the optimization of the timing and other problems are caused due to the fact that the registers need to be rearranged.
In order to solve the above technical problems, the present invention provides a general and feasible register-based timing sequence convergence structure, and referring to fig. 6, the timing sequence convergence window is enlarged, and clock tree deviation is offset to make the timing sequence easier to meet the requirements. Referring to fig. 1, a group of data caches are arranged at the digital function side, the depth of the caches is larger than the maximum delay of a clock tree, and the depth of the caches is generally set to be 4, and the caches can be written and covered periodically; setting a primary read data register for the analog interface; arranging the length of the digital side clock tree to be consistent with the digital function, wherein the analog side clock tree is close to the analog side clock length; setting a flag bit to indicate that writing into a first-level buffer register is started, gradually transiting the flag bit register to a read clock domain, gradually changing the length of a clock tree to a read clock, and starting a read counting function when the length of the clock tree reaches the read clock domain; when the time sequence is converged, setting static time sequence analysis on the time sequence cached in the reading register, wherein the numerical value is the number of transition stages of the zone bit; the timing of the fully converged flag bit can synchronously reset the address counter on the read side.
The specific scheme is as follows:
In one embodiment, as shown in fig. 1, the present invention provides a register-based timing convergence structure, comprising: a set of enable flag registers 100, at least one set of cache registers 200, at least one multiplexer 300, a first read register 400, at least one second read register 500, and a write address register 600.
A set of start flag registers 100 are connected in series between the analog side and the digital side, and each start flag register 100 is connected in turn.
Specifically, a set of start flag registers 100 (a set of start flag registers is set according to actual conditions, for example, a set of 3 start flag registers are sequentially connected) are connected in series between the digital side and the analog side, where each start flag register is sequentially connected in a manner that an output end of a previous stage of start flag registers 100 is connected to an input end of a subsequent stage of start flag registers 100. Each start flag register 100 is provided with a clock tree, and the clock tree lengths of each start flag register are sequentially decremented (e.g., a set of start flag registers 100 with a first stage clock tree length set to 4, a second stage clock tree length set to 3, etc., thereby decrementing).
At least one group of cache registers is serially connected between the analog side and the digital side.
Specifically, at least one group of buffer register sets includes a plurality of buffer registers 200, and an input end of each buffer register 200 is connected to a digital side and is used for buffering data sent from the digital side. The data buffered by the buffer registers of each column in the buffer register sets are not the same (for example, each buffer register set has at least one column of buffer registers 200, if the data sent by the digital side is 0, 1,2, the data buffered by the first column of buffer registers 200 is 0, the data buffered by the second column of buffer registers 200 is 1, the data buffered by the third column of buffer registers 200 is 2), and the depth of the buffer register sets is greater than the maximum delay of the clock tree (generally set to 4).
Further, the clock tree length of the buffer register sets is consistent with the digital side function (for example, the clock tree length of the first column buffer register of each buffer register set is set to 4 in this embodiment), and each buffer register 200 may be periodically written to cover the data transferred on the digital side.
Further, when the start flag bit register 100 receives the data sent from the digital side, the buffer register set starts buffering the data sent from the digital side.
The multiplexers 300 are in one-to-one correspondence with the cache register sets, the multiplexers 300 are connected to the output ends of the cache register sets, and the multiplexers 300 are sequentially connected.
Specifically, at least one multiplexer 300, each multiplexer 300 corresponds to a cache register set one by one, and each multiplexer 300 is connected to the output end of the corresponding cache register set in a distributed manner. The output end of each column of the buffer registers 200 in the buffer register set is connected to a corresponding way of the multiplexer 300 (for example, the data on the digital side buffered by the first column of buffer registers 200 is 0, the data on the digital side buffered by the second column of buffer registers 200 is 1, and the data on the digital side buffered by the third column of buffer registers is 2. Correspondingly, the output end of the first column of buffer registers 200 is connected to a first way (the first way is 0 way) of the corresponding multiplexer 300, and the output end of the second column of buffer registers 200 is connected to a second way (the second way is 1 way) of the corresponding multiplexer 300, so that the description is omitted herein), and the function of the multiplexer 300 is to select the data buffered by any way of the buffer registers 200 connected.
The enable end of the first read register 400 is connected to the output end of the set of enable flag bit registers 100, and the output end of the first read register 400 is connected to one of the multiplexers 300.
Specifically, the enable end of the first read register 400 (for example, the first read register 400 is a read address register in this embodiment) is connected to the output end of the set of start flag bit registers 100, and the output end of the first read register 400 is connected to each of the multiplexers 300 (the output end of the first read register 400 is connected to the multiplexer 300 corresponding to the first set of buffer register sets in this embodiment).
The second read register 500 corresponds to the multiplexers 300 one by one, an input end of the second read register 500 is connected to the multiplexers 300, and an output end of the second read register 500 is connected to the analog side.
Specifically, at least one second read register 500, where the second read registers 500 are in one-to-one correspondence with the multiplexers 300, and the input ends of the second read registers 500 are connected to the multiplexers 300, and the output ends are connected to the analog side. Meanwhile, the clock tree lengths of the second read register 500 and the first read register 400 are close to the analog side clock length (i.e., the clock tree lengths of the second read register 500 and the first read register 400 in fig. 1 are made to coincide with the clock domain in which the analog side input data function is located).
Further, when the data transmitted from the digital side is sequentially transferred from the start flag bit register 100 to the first read register 400, the second read register 500 reads the data buffered in one of the buffer registers 200 through the corresponding multiplexer 300.
The write address register 600 is connected in series between the analog side and the digital side, and the write address register 600 is used only to control the digital side cache register 200.
Specifically, the address register 600 is serially connected between the digital side and the analog side, where the address register 600 functions to write the data sent from the digital side into one column of the buffer registers 200 (e.g., the data sent from the digital side is 0 and 1, in this embodiment, the address register 600 writes the data sent from the digital side into one column of the buffer registers 200, and in writing the digital 1 into another column of the buffer registers 200), and the clock tree length of the address register 600 is also set according to the actual situation (e.g., the clock tree lengths of the address register 600 and the buffer register 200 are made consistent with the clock domain where the data function is located on the digital side.
In this embodiment, a set of start flag bit register 100 and first read register 400 are set, wherein an input end of the start flag bit register 100 is connected to the digital side, and an output end of the start flag bit register 100 is connected to an enable end of the first read register 400. When the data of the digital side enters the start flag bit register 100, the write address register 600 starts writing the data of the digital side into the cache register 200; when the data on the digital side enters the first read register 400 through the start flag bit register 100, the second read register 500 reads the data buffered in the corresponding buffer register 200 through the multiplexer 300. Because only the first-stage buffer register 200 and the second read register 500 in this embodiment will introduce flip, the power consumption of timing closure is greatly reduced. Meanwhile, the number of registers and the number of clock trees used in the embodiment are greatly reduced compared with the traditional scheme, the utilization rate of the digital-analog hybrid chip is improved, and the resource waste is reduced.
In one embodiment, as shown in fig. 2, the present invention provides a timing closure verification method, which is applied to the register-based timing closure structure described in the foregoing embodiment, and includes the steps of:
Before timing closure verification is performed on the register-based timing closure structure, the process of timing closure performed on the register-based timing closure structure in the foregoing embodiment is described first:
first, a data chain is concatenated by a set of start flag bit registers and a first read register. The starting end of the data chain is connected with the digital side, and the tail end of the data chain is connected with the analog side.
Further, the clock delay difference that can be improved by each stage of register chain is calculated, and the length of the total register chain is calculated (the clock delay difference that can be improved by each start flag bit register and the first read register is calculated in this embodiment, so that the length of the total register chain is calculated; the length of the register chain is 4 in this embodiment); continuously adjusting the length of clock branches of each stage of register chain, and establishing a clock gradient from digital to analog (in the embodiment, the lengths of clock trees of each start bit register and each first read register are set, and the lengths of the clock trees of each start bit register and each first read register are sequentially decreased); the delay difference of the clock tree is large under different process angles, the delay difference of the clock tree is 1 unit under a fast process angle, 3 units under a slow process angle, and the middle process angle is any numerical value distributed in different 1-3 units. Therefore, a preset timing convergence model is built through the steps, and the timing convergence process is completed through the steps by a group of data chains cascaded by the start zone bit register and the first reading register.
Further, the control register sets complete the timing convergence operation according to the preset timing convergence model (in the same embodiment, each register set and the corresponding second read register are cascaded into a data chain, according to the step of the timing convergence model, clock delay differences which can be improved by each row of register and the corresponding second read register in the register set are automatically calculated, so as to calculate the length of a total register chain, the clock tree length of each row of register and the second read register is automatically set, the driving load capacity of each register and each second read register in the data chain and the corresponding clock tree, and the driving load capacity of the buffer BUFF are automatically set, so that the cascaded data chain of each register set and the corresponding second read register completes the timing convergence operation through the steps.
S100, sending first initial data to a start flag bit register through a digital side, wherein the first initial data is a start signal.
S110, when the start flag bit register receives the first initial data, the write address register is controlled to write the second initial data into the cache register set.
Specifically, the first initial data (the first initial data in this embodiment is a start signal) is sent to the start flag bit register through the digital side, when the start flag bit register receives the first initial data, the write address register is controlled to write the first initial data into the buffer register set (for example, when the start flag bit register receives the first initial data, the start flag bit register is used for buffering the second initial data in the buffer register set).
S120, the start flag bit register is controlled to send the first initial data to the first reading register.
Specifically, the first initial data is controlled to sequentially pass through each start flag bit register, and the first initial data is sent from the output end of the start flag bit register of the last stage to the enabling end of the first reading register.
And S130, when the first reading register receives the first initial data, controlling the second reading register to read the second initial data cached by the cache register set through the first preset time.
Specifically, when the first read register receives the first initial data (in this embodiment, when the first initial data is sent to the first read register, the first read register is used to start the second read register to read the second initial data), the second read register is controlled to select a part of the second initial data buffered by one of the buffer registers in the buffer register set to read after a first preset time (for example, the first initial data is 0 and 1, the buffer register set is first-column buffer data 0 and the second-column buffer data 1. The output end of the first-column buffer register is connected to a first way (i.e. 0 way) of the multiplexer, and the output end of the second-column buffer register is connected to a second way (i.e. 1 way) of the multiplexer; of course, the second read register may be controlled to select all the second initial data in all the buffer register sets for reading through the multiplexer.
S140, when the set of start bit registers and the first reading register complete timing sequence convergence through a preset timing sequence convergence model, determining the constraint of static timing sequence analysis according to the first timing sequence beat number in the timing sequence convergence process completed by the set of start bit registers and the first reading register.
Specifically, after the set of the start flag bit register and the first read register complete the timing convergence (i.e., the set of the start flag bit register and the first read register succeed in timing convergence through the preset timing convergence model) by the preset timing convergence model (in this embodiment, the first timing beat is determined according to the number of the start flag bit registers between the first start flag bit register and the first read register near the digital side, and the number of the start flag bit registers is 2 according to the clock delay difference of the start flag bit registers and the first read register, the data between the start flag bit registers and the first read register, and the driving load of the clock), the first timing beat is specifically set according to the actual situation (i.e., the number of the start flag bit registers between the first start flag bit register and the first read register near the digital side is 3 according to the number of the start flag bit registers near the digital side, and the first timing beat is 3 according to the number of the start flag bit registers near the digital side).
Further, after the first time sequence beat number is obtained, determining a constraint of static time sequence analysis according to the first time sequence beat number. ( In this embodiment, the constraint of the static timing analysis includes a first multicycle constraint and a second multicycle constraint. If the first timing beat number is 2, the first multicycle constraint is set_ multicycle _path-setup-end 2; the second multicycle constraint is set_ multicycle _path-hold-end 1, and similarly, the first time sequence beat number is different, and the first multicycle constraint and the second multicycle constraint are modified correspondingly. )
S150, judging whether the timing sequence convergence structure based on the register is in a timing sequence violation or not according to the constraint of the static timing sequence analysis, the second initial data cached by the cache register group and the second initial data read by the second read register.
S160, if no timing violation exists, the timing convergence of the judged register-based timing convergence structure is successful.
Specifically, after the static timing analysis constraint is determined, whether the timing convergence structure based on the register is in a timing violation is judged by the static timing analysis constraint, the second initial data cached by the cache register group and the second initial data cached by the second cache register (in this embodiment, the timing violation includes a setup time violation and a hold time violation, wherein the setup time violation is a setup violation, the hold time violation is a hold violation), when the static timing analysis result shows that the timing violation does not occur, it is indicated that the timing convergence structure based on the register has succeeded in timing convergence, and the second initial data cached by the second cache register and the second initial data cached by the cache register group are consistent (in this embodiment, if the second cache register is controlled to read all the second initial data, all the second initial data read by the second cache register is consistent with all the second initial data cached by the cache register group, and if the second cache register is controlled to read part of the second initial data is controlled to read, part of the second initial data read by the second cache is consistent with the second initial data cached by the corresponding part of the second cache register group).
The timing sequence of a single register is matched with the timing sequence constraint in static timing sequence analysis, so that a large number of register timing sequence problems are solved, the power consumption is reduced, and the economic benefit is improved.
In one embodiment, as shown in fig. 3, the present invention provides a timing convergence verification method, based on the above embodiment, the step of controlling the second read register to read the second initial data buffered in the buffer register set after a first preset time further includes:
s200, setting a timing sequence convergence window according to the number of columns of the buffer register group.
Specifically, the timing convergence window is substantially clock period (in this embodiment, referring to fig. 6, if the number of columns of the buffer register set is 3, the timing convergence window is set to 3 beats or 3 clock periods, specifically may be set according to practical situations), and compared with the timing convergence window in this embodiment, the timing convergence window in the prior art is shorter (for example, referring to fig. 5, the timing convergence window is 1 beat or 1 clock period), so that problems such as incomplete reading, and errors in reading data may occur in the data read in the prior art.
S210, judging whether the second initial data cached by the cache register set is consistent with the second initial data read by the second reading register according to the timing sequence convergence window in a preset environment.
S220, if the timing convergence structures are consistent, judging that the timing convergence based on the register is successful.
Specifically, in this embodiment, the preset environment includes a temperature, a voltage, different process angles, and the like where the timing convergence structure of the register is located, and in the preset environment, after a first preset time (in this embodiment, the first preset time is 3 clock cycles different from the second initial data written into the buffer register and the second initial data read out by the last second read register, that is, the first preset time is related to the number of stages of the start flag bit register, and in fig. 1, the number of stages of the start flag bit register is 3, then the first preset time is 3 clock cycles), whether the second initial data buffered in the buffer register set is consistent with the second initial data read by the second read register is judged in the clock cycle set by the timing convergence window. The timing sequence convergence window is not the same as the first preset time, but the larger the timing sequence convergence window is, the better the stability of the data read by the second reading register is when the second reading register reads the data after the first preset time. (in this embodiment, if the second read register is controlled to read all the second initial data, it is determined whether all the second initial data read by the second read register is consistent with all the second initial data cached by the cache register set, and if the second read register is controlled to read part of the second initial data, it is determined whether part of the second initial data read by the second read register is consistent with part of the second initial data cached by the corresponding cache register set (for example, if the second read register is controlled to read part of the second initial data cached by the first row cache register, it is determined whether part of the second initial data read by the second read register is consistent with part of the second initial data cached by the first row cache register)).
If the timing sequence convergence structures are consistent, judging that the timing sequence convergence structure based on the register is successful in timing sequence convergence.
In one embodiment, the present invention provides a timing convergence verification method, based on the above embodiment, the controlling the write address register to write the second initial data into the cache register set specifically includes the steps of:
And controlling the write address register to write partial data in the second initial data into one column of cache registers in the cache register group.
In one embodiment, the present invention provides a timing convergence verification method, based on the above embodiment, the controlling the second read register to read the second initial data buffered in the buffer register set specifically includes the steps of:
and controlling the second reading register to select part of the second initial data cached by one row of cache registers in the corresponding cache register group through the multiplexer for reading.
In the embodiment, the start flag bit register and the first reading register construct a timing sequence convergence model through a calculation flow, and the tool automatically enables the buffer register group to execute timing sequence convergence operation according to the timing sequence convergence model. The working pressure of a developer is greatly reduced, the utilization rate of a chip is improved, and the time sequence convergence power consumption is further reduced.
In one embodiment, as shown in fig. 7, the present invention provides another form of register-based timing closure structure, where the functions, numbers and connections of the registers in fig. 7 are substantially the same as those in fig. 1, with only partial differences, and the differences between fig. 1 and fig. 7 are described below:
The same set of start flag registers 100 in fig. 7 are connected in series between the analog and digital sides, with each start flag register 100 connected in turn. The first stage of the set of start bit registers 100 shown in fig. 7 is connected to the analog side, while the first stage of the set of start bit registers 100 in fig. 1 is connected to the digital side. In fig. 7, each start flag register is sequentially connected in such a manner that the output end of the start flag register 100 of the previous stage is connected to the input end of the start flag register 100 of the next stage. Each start flag register 100 is provided with a clock tree, and the clock tree lengths of each start flag register are sequentially incremented (e.g., a set of start flag registers 100 has a first stage clock tree length set to 1, a second stage clock tree length set to 2, etc., thereby incrementing).
In fig. 7, compared with fig. 1, at least one group of buffer register sets is also provided, wherein one group of buffer register sets includes a plurality of buffer registers 200, and input ends of the buffer registers 200 are all connected to the analog side.
Further, the clock tree length of the buffer register sets in fig. 7 is consistent with the analog side function (for example, the clock tree length of the first column buffer register of each buffer register set is set to 1 in this embodiment).
Further, the output terminal of the second read register 500 in fig. 7 is connected to the digital side, and at the same time, the clock tree lengths of the second read register 500 and the first read register 400 in fig. 7 are close to the clock length of the digital side (i.e. the clock tree lengths of the second read register 500 and the first read register 400 in fig. 7 are made to coincide with the clock domain where the digital side input data function is located).
Further, the length of the clock tree of the write address register 600 in fig. 7 is made to coincide with the clock domain in which the analog side input data function is located. The length of the clock tree of the write address register 600 of this embodiment is 1.
In this embodiment, only the structure of fig. 7 is partially different from that of fig. 1, and the rest is the same. Meanwhile, the timing convergence verification method for fig. 7 is the same as the steps in the foregoing embodiment, and will not be described again.
In one embodiment, the invention provides a digital-analog hybrid chip, which comprises the register-based timing convergence structure described in the previous embodiment.
In one embodiment, the present invention provides a computer medium having a computer program stored thereon, where the computer program, when executed by a processor, implements the timing closure verification method as described in the previous embodiment. That is, when some or all of the foregoing technical solutions that contribute to the prior art according to the embodiments of the present invention are embodied by means of a computer software product, the foregoing computer software product is stored in a computer-readable storage medium. The computer readable storage medium can be any means or device that can carry computer program code entities such as a U disk, removable magnetic disk, optical disk, computer memory, read only memory, random access memory, and the like.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (8)
1. A timing closure verification method, applied to a register-based timing closure structure, the structure comprising: the starting zone bit registers are connected in series between the analog side and the digital side, and are sequentially connected;
at least one set of buffer registers connected in series between the analog side and the digital side;
The multiplexers are in one-to-one correspondence with the cache register sets, are connected with the output ends of the cache register sets, and are sequentially connected;
The enabling end of the first reading register is connected with the output end of a group of starting zone bit registers, and the output end of the first reading register is connected with each multiplexer;
The input end of the second reading register is connected with the multiplexer, and the output end of the second reading register is connected with the analog side;
a write address register connected in series between the analog side and the digital side;
The timing sequence convergence verification method comprises the following steps:
Transmitting first initial data to the starting zone bit register through the digital side, wherein the first initial data is a starting signal;
When the starting zone bit register receives the first initial data, controlling the write address register to write second initial data into the cache register group;
Controlling the start flag bit register to send the first initial data to a first reading register;
when the first reading register receives the first initial data, the second reading register is controlled to read the second initial data cached by the cache register set through a first preset time;
When a group of the starting zone bit registers and the first reading registers finish timing sequence convergence through a preset timing sequence convergence model, determining constraint of static timing sequence analysis according to a first timing sequence beat number in the timing sequence convergence process of the group of the starting zone bit registers and the first reading registers;
Judging whether the time sequence convergence structure based on the register is in violation or not according to the constraint of the static time sequence analysis, the second initial data cached by the cache register group and the second initial data read by the second reading register;
if no timing violation exists, judging that the timing convergence of the register-based timing convergence structure is successful.
2. The timing closure verification method of claim 1, wherein the clock tree length of each of said start bit registers is stepped down.
3. The timing closure verification method of claim 1, wherein the write address register is configured to write data sent from the digital side into one of the columns of the cache registers in the set of cache registers.
4. A timing closure verification method according to claim 3, wherein said second read register is configured to select, via said multiplexer, data buffered in one of said corresponding buffer register sets for reading.
5. The timing closure verification method of claim 1 wherein the clock tree length of the buffer register set is consistent with the clock domain of the digital side input data function, and the second read register clock tree length and the first read register clock tree length are consistent with the clock domain of the analog side input data function.
6. The timing closure verification method according to any one of claims 1 to 5, wherein after the second read register is controlled to read the second initial data buffered in the buffer register set for a first preset time, the method further comprises the steps of:
Setting a timing sequence convergence window according to the column number of the cache register group;
Judging whether second initial data cached by the cache register group is consistent with second initial data read by the second reading register or not according to the timing sequence convergence window in a preset environment;
And if the timing sequence is consistent, judging that the timing sequence convergence based on the register is successful.
7. The timing closure verification method according to any one of claims 1 to 5, wherein said controlling said write address register to write second initial data into said set of cache registers comprises the steps of:
and controlling the write address register to write partial data in the second initial data into one column of cache registers in the cache register group.
8. The timing closure verification method according to any one of claims 1 to 5, wherein the controlling the second read register to read the second initial data buffered in the buffer register set for a first preset time specifically includes the steps of:
and controlling the second reading register to select partial second initial data cached by one row of cache registers in the corresponding cache register group through the multiplexer for reading.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7928770B1 (en) * | 2006-11-06 | 2011-04-19 | Altera Corporation | I/O block for high performance memory interfaces |
| CN103957139A (en) * | 2014-05-09 | 2014-07-30 | 天津市德力电子仪器有限公司 | Ten-Gigabit Ethernet frame analyzing method based on FPGA |
| CN104850829A (en) * | 2015-05-05 | 2015-08-19 | 中国人民解放军国防科学技术大学 | Coarse-grain parallel-based fingerprint matching unit |
| CN108027807A (en) * | 2015-09-19 | 2018-05-11 | 微软技术许可有限责任公司 | Block-based processor core topology register |
| CN108140232A (en) * | 2015-06-10 | 2018-06-08 | 无比视视觉技术有限公司 | For handling the image processor of image and method |
| CN108874702A (en) * | 2018-06-15 | 2018-11-23 | 中国电子科技集团公司第五十二研究所 | The symmetrical encryption and decryption IP kernel parallel processing apparatus of multichannel and method based on AXI bus |
| CN111324493A (en) * | 2018-12-13 | 2020-06-23 | 展讯通信（上海）有限公司 | Development system and method for processor board level debugging |
| CN112486453A (en) * | 2020-12-10 | 2021-03-12 | 上海金卓科技有限公司 | Asynchronous first-in first-out register and chip |
| CN114785354A (en) * | 2022-04-13 | 2022-07-22 | 浙江大学 | Low-complexity multi-system LDPC check node updating method of FIFO architecture |
| CN116595938A (en) * | 2023-07-14 | 2023-08-15 | 上海韬润半导体有限公司 | Layout method, system and integrated circuit of pipeline register |
| CN117332374A (en) * | 2023-11-04 | 2024-01-02 | 恒烁半导体(合肥)股份有限公司 | AI chip calculation and communication fusion method and device and AI chip |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8887018B2 (en) * | 2010-06-11 | 2014-11-11 | Texas Instruments Incorporated | Masking circuit removing unknown bit from cell in scan chain |
| US9910454B2 (en) * | 2012-06-07 | 2018-03-06 | Sonics, Inc. | Synchronizer with a timing closure enhancement |
| US11449397B2 (en) * | 2019-09-11 | 2022-09-20 | International Business Machines Corporation | Cache array macro micro-masking |
-
2024
- 2024-03-18 CN CN202410302913.2A patent/CN117892673B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7928770B1 (en) * | 2006-11-06 | 2011-04-19 | Altera Corporation | I/O block for high performance memory interfaces |
| CN103957139A (en) * | 2014-05-09 | 2014-07-30 | 天津市德力电子仪器有限公司 | Ten-Gigabit Ethernet frame analyzing method based on FPGA |
| CN104850829A (en) * | 2015-05-05 | 2015-08-19 | 中国人民解放军国防科学技术大学 | Coarse-grain parallel-based fingerprint matching unit |
| CN108140232A (en) * | 2015-06-10 | 2018-06-08 | 无比视视觉技术有限公司 | For handling the image processor of image and method |
| CN108027807A (en) * | 2015-09-19 | 2018-05-11 | 微软技术许可有限责任公司 | Block-based processor core topology register |
| CN108874702A (en) * | 2018-06-15 | 2018-11-23 | 中国电子科技集团公司第五十二研究所 | The symmetrical encryption and decryption IP kernel parallel processing apparatus of multichannel and method based on AXI bus |
| CN111324493A (en) * | 2018-12-13 | 2020-06-23 | 展讯通信（上海）有限公司 | Development system and method for processor board level debugging |
| CN112486453A (en) * | 2020-12-10 | 2021-03-12 | 上海金卓科技有限公司 | Asynchronous first-in first-out register and chip |
| CN114785354A (en) * | 2022-04-13 | 2022-07-22 | 浙江大学 | Low-complexity multi-system LDPC check node updating method of FIFO architecture |
| CN116595938A (en) * | 2023-07-14 | 2023-08-15 | 上海韬润半导体有限公司 | Layout method, system and integrated circuit of pipeline register |
| CN117332374A (en) * | 2023-11-04 | 2024-01-02 | 恒烁半导体(合肥)股份有限公司 | AI chip calculation and communication fusion method and device and AI chip |
Non-Patent Citations (2)
| Title |
|---|
| 一种改进的快速IMP伪码捕获方法;史治平;晏辉;唐发建;龚万春;;信号处理;20110525(第05期);第703-708页 * |
| 改进的基于属性不变量生成和数学归纳法的时序逻辑优化算法;郝亚男;杨海钢;路宝珠;崔秀海;张茉莉;;计算机辅助设计与图形学学报;20120915(第09期);第1232-1240页 * |
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