CN112612608A - Memory training method and system - Google Patents
Memory training method and system Download PDFInfo
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- CN112612608A CN112612608A CN202011490385.6A CN202011490385A CN112612608A CN 112612608 A CN112612608 A CN 112612608A CN 202011490385 A CN202011490385 A CN 202011490385A CN 112612608 A CN112612608 A CN 112612608A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5083—Techniques for rebalancing the load in a distributed system
Abstract
The invention provides a memory training method and a memory training system. The method comprises the steps that a central controller, at least two storage controllers which are connected in parallel and connected with the central controller, and at least one micro-processing unit arranged in the storage controllers are arranged; the central controller starts the memory training of the time sequence parameters; executing at least one memory training subtask in a storage controller by a micro-processing unit to obtain a first subtask result and sending the first subtask result to a central controller; and after receiving the first subtask result, the central controller executes at least one memory training subtask according to the first subtask result, and determines the configuration value of the time sequence parameter. The invention can give full play to the advantages of the central processing unit and the micro-processing unit to complete the memory training, thereby greatly improving the memory training efficiency of the multi-storage controller system; the memory training speed of the multi-memory controller system is greatly improved, and the development of artificial intelligence and high-performance calculation is promoted.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a memory training method and system.
Background
With the development of artificial intelligence and high-performance computing, computing units such as processors and display cards put higher requirements on the capacity and bandwidth of a memory. Due to the high operating frequency (GHz level) of the memory itself, the parallel synchronous bus (parallel data line, command address line, synchronous with clock and sampling signal), the packaging process difference or PCB wiring difference, and the influence of external application environment such as temperature and voltage variation, the memory signal is very easy to be interfered to cause data receiving and transmitting error.
Memory training is to adjust a memory controller (MC for short) by a cyclic attempt, where the memory controller may perform necessary control on access to a memory according to a certain timing rule, and the memory controller includes control of address signals, data signals, and various command signals, so that a master device can use storage resources on the memory according to its own requirements, and related timing parameter values, such as delay parameters of ADDR/CMD signals to CLK and DQ signals to DQs, are tested to obtain a delay parameter that can ensure that each signal has sufficient setup time before signal sampling and sufficient hold time after sampling, so that the signal can be correctly sampled. And selecting an optimal value from the delay parameters which can work, and configuring the optimal value into the storage controller to ensure that the storage equipment works in the most stable state. Therefore, the processor or the display card can optionally perform memory training on the memory in the starting process, find the optimal parameters and configure the optimal parameters into the memory controller, so as to ensure the stable operation of the memory.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
in the prior art, memory training is mainly performed for one memory controller; as the computing units have higher requirements on the capacity and bandwidth of the storage units, a plurality of storage controllers are integrated in a general system so as to manage more storage units, and the storage controllers can run concurrently to improve the storage bandwidth. The prior art also does not provide a solution for how memory training should be performed for multiple storage controllers.
In the simplest mode, the prior art is simply expanded for a system integrating a plurality of storage controllers, and the plurality of storage controllers are sequentially and serially subjected to memory training. Meanwhile, the scheme can not play the parallelism of each storage controller, the efficiency is very low, and the memory training speed is seriously influenced.
If the CPU initiates multiple threads and controls the storage controllers to perform memory training in a parallel manner, frequent small data transmission between the CPU and the multiple storage controllers is required (the memory training process is a small data transceiving process of multiple loop iteration), and indirect mode communication is used (data interaction is generally required to be performed between the CPU and the storage controllers across multiple buses and modules), so that the memory training efficiency of the scheme is relatively low.
Disclosure of Invention
The memory training method and the memory training system can fully exert the respective advantages of the central processing unit and the micro-processing unit to complete memory training, and greatly improve the memory training efficiency of a multi-storage controller system; the memory training speed of the multi-memory controller system is greatly improved, and the development of artificial intelligence and high-performance calculation is promoted.
In a first aspect, the present invention provides a memory training method, including a central controller, at least two parallel-connected memory controllers connected to the central controller, and at least one micro-processing unit disposed in the memory controllers;
the central controller starts the memory training of the time sequence parameters;
executing at least one memory training subtask in a storage controller by a micro-processing unit to obtain a first subtask result and sending the first subtask result to a central controller;
and after receiving the first subtask result, the central controller executes at least one memory training subtask according to the first subtask result, and determines the configuration value of the time sequence parameter.
Optionally, the memory training of the timing parameter may be preset to at least two subtasks, and executed by a designated central controller or a micro-processing unit;
or the memory training of the time sequence parameters is dynamically divided into at least two subtasks by the central controller according to preset conditions, and the corresponding central controller or the micro-processing unit is appointed to execute.
Optionally, the subtask of the memory training includes at least one of: the method comprises a loop iteration calculation subtask, an optimal configuration value calculation subtask of a time sequence parameter, a memory training result analysis subtask, a memory training result recording subtask and a training interval calculation subtask optimized by memory training.
Optionally, before the central controller starts memory training of timing parameters, the method further includes:
the central controller is communicated and interacted with the micro-processing unit through the communication unit;
preferably, the communication unit is one of: the system comprises a communication register arranged in a storage controller, a storage unit connected with the storage controller and a central controller and a preset communication mechanism.
Optionally, after the central controller initiates memory training of timing parameters, the method includes:
the method comprises the steps that a micro-processing unit obtains a current state value stored in a communication unit, when the current state value is a first preset value, the micro-processing unit executes at least one memory training subtask with preset time sequence parameters in a storage controller to obtain a first subtask result, and the first subtask result is sent to a central controller;
or, the central processing unit obtains a current state value stored in the communication unit, and when the current state value is a second preset value, the central processing unit receives a first subtask result, then executes at least one memory training subtask with a preset time sequence parameter according to the first subtask result, and determines a configuration value of the preset time sequence parameter.
Optionally, the acquiring, by the microprocessor unit, a current state value stored in the communication unit, and when the current state value is a first preset value, the executing, by the microprocessor unit, at least one memory training subtask with a preset timing parameter in the storage controller to obtain a first subtask result, and sending the first subtask result to the central controller includes:
the micro-processing unit acquires a current state value stored in the communication unit and judges whether the current state value is a first preset value or not;
when the current state value is a first preset value, determining a preset parameter to be subjected to memory training according to the first preset value;
according to the preset parameters, configuring a parameter interval to be trained in a microprocessing unit;
the micro-processing unit traverses each parameter value in the parameter interval to be trained to carry out memory training;
and determining a result bitmap which meets the memory training requirement of the preset parameters, and writing the result bitmap serving as a first subtask result into a preset register of a storage controller.
Optionally, the obtaining, by the central processing unit, a current state value stored in the communication unit, and when the current state value is a second preset value, after receiving a first subtask result, the central processing unit executes at least one memory training subtask of a preset timing parameter according to the first subtask result, and determining the configuration value of the preset timing parameter includes:
the central processing unit acquires a current state value stored in the communication unit and judges whether the current state value is a second preset value or not;
when the current state value is a second preset value, judging whether a time sequence parameter corresponding result bitmap which finishes memory training needs to be read from a preset register of a storage controller or not according to the second preset value;
the central controller records the first subtask result;
the central controller executes at least one memory training subtask with preset time sequence parameters according to the result bitmap corresponding to the time sequence parameters of which the memory training is finished and the first subtask result;
and determining the configuration value of the preset time sequence parameter.
In a second aspect, the present invention provides a system for memory training, including: the system comprises a central controller, at least two storage controllers connected in parallel and connected with the central controller, and at least one micro-processing unit arranged in the storage controllers; wherein:
the micro-processing unit is used for executing at least one memory training subtask in the storage controller after the central controller starts memory training of the time sequence parameters to obtain a first subtask result and sending the first subtask result to the central controller;
the central controller: the memory training device is used for starting memory training of a time sequence parameter, receiving a first subtask result, executing at least one memory training subtask according to the first subtask result, and determining a configuration value of the time sequence parameter.
Optionally, the system further comprises:
the communication unit is used for carrying out communication interaction between the central controller and the micro-processing unit;
preferably, the communication unit is a communication register disposed in the storage controller, or a storage unit connected to the storage controller or the central controller, or a preset communication mechanism.
Optionally, the micro-processing unit comprises:
the acquisition module is used for acquiring the current state value stored in the communication unit;
the judging module is used for judging whether the current state value is a first preset value or not;
the determining module is used for determining a preset parameter to be subjected to memory training and a parameter interval to be trained according to the first preset value;
the configuration module is used for configuring a parameter interval to be trained;
and the first memory training module is used for traversing each parameter value in the parameter interval to be trained to perform memory training.
Optionally, the central controller comprises:
the acquisition module is used for acquiring the current state value stored in the communication unit;
the judging module is used for judging whether the current state value is a second preset value or not;
the reading module is used for judging whether a time sequence parameter corresponding result bitmap which finishes the memory training needs to be read from a preset register of the storage controller or not according to a second preset value when the current state value is the second preset value;
the recording module is used for recording the first subtask result;
the second memory training module is used for executing at least one memory training subtask with preset time sequence parameters according to the result bitmap corresponding to the time sequence parameters of which the memory training is finished and the first subtask result; and determining the configuration value of the preset time sequence parameter.
The memory training method and system provided by the embodiment of the invention not only can solve the problem that the prior art can not solve the memory training of a plurality of memory controller systems, but also can solve the problem that the memory training efficiency is not high only by simply expanding the prior art to adapt to a plurality of memory controller systems, the embodiment of the invention utilizes at least two micro-processing units (namely micro-processors, abbreviated as MP) in the system, the micro-processing units can execute integrated circuits of control and arithmetic logic operation, can finish the functions of instruction fetching, instruction execution and memory component access) and a central processing unit (CPU for short) to form a set of distributed system, the calculation difficulty in the memory training is small, but the memory training subtask with large calculation amount is handed to a micro-processing unit which can quickly access the register of the storage controller for carrying out, such as a loop iteration operation subtask in the memory training; and the memory training subtask with high computational difficulty is handed to a central controller which can execute a high-level language and realize complex logic, such as the memory training result analysis and recording subtask.
Therefore, the method and the system of the embodiment of the invention can fully exert the respective advantages of the central processing unit and the micro-processing unit to be matched with each other to finish the memory training, thereby greatly improving the memory training efficiency of the multi-memory controller system; the memory training speed of the multi-memory controller system is greatly improved, and the development of artificial intelligence and high-performance calculation is promoted.
Drawings
FIG. 1 is a flow chart of a method for memory training according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of memory training according to another embodiment of the present invention;
FIG. 3 is a flowchart of a method for memory training according to another embodiment of the present invention;
FIG. 4 is a block diagram illustrating a system for memory training according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a memory training system according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a memory training method, as shown in fig. 1, including a central controller, at least two storage controllers connected in parallel to the central controller, and at least one microprocessor unit disposed in the storage controllers; the method comprises the following steps:
s11, starting memory training of the time sequence parameters by the central controller;
s12, the micro-processing unit executes at least one memory training subtask in the storage controller to obtain a first subtask result and sends the first subtask result to the central controller;
and S13, after receiving the first subtask result, the central controller executes at least one memory training subtask according to the first subtask result, and determines the configuration value of the time sequence parameter.
The memory training method provided by the embodiment of the invention not only solves the problem that the prior art can not solve the memory training of a plurality of memory controller systems, but also can solve the problem that the memory training efficiency is not high only by simply expanding the prior art to adapt to a plurality of memory controller systems, the embodiment of the invention utilizes at least two micro-processing units (namely, micro-processors, abbreviated as MP) in the system, wherein the micro-processing units are integrated circuits capable of executing control and arithmetic logic operation and can complete the functions of fetching instructions, executing instructions and accessing memory components, and a central processing unit (CPU for short) to form a set of distributed system, so that the calculation difficulty in the memory training is small, but the memory training subtask with large calculation amount is handed to a micro-processing unit which can quickly access the register of the storage controller for carrying out, such as a loop iteration operation subtask in the memory training; and the memory training subtask with high computational difficulty is handed to a central controller which can execute a high-level language and realize complex logic, such as the memory training result analysis and recording subtask.
Therefore, the method of the embodiment of the invention can fully exert the respective advantages of the central processing unit and the micro-processing unit to cooperate with each other to complete the memory training, thereby greatly improving the memory training efficiency of the multi-memory controller system; the memory training speed of the multi-memory controller system is greatly improved, and the development of artificial intelligence and high-performance calculation is promoted.
Optionally, the memory training of the timing parameter may be preset to at least two subtasks, and executed by a designated central controller or a micro-processing unit;
or the memory training of the time sequence parameters is dynamically divided into at least two subtasks by the central controller according to preset conditions, and the corresponding central controller or the micro-processing unit is appointed to execute.
Optionally, the subtask of the memory training includes at least one of: the method comprises a loop iteration calculation subtask, an optimal configuration value calculation subtask of a time sequence parameter, a memory training result analysis subtask, a memory training result recording subtask and a training interval calculation subtask optimized by memory training.
The method of the embodiment of the invention can simply preset the memory training as a plurality of subtasks and appoint the optimal one to execute according to the running characteristics, the capability and the like of the microprocessing unit and the central controller; for example, a round-robin iterative computation subtask is assigned, or an optimal configuration value of a time sequence parameter is assigned to the microprocessing unit to be executed, and a memory training result analysis subtask, a memory training result recording subtask, or a training interval calculation subtask optimized for memory training is assigned to the central controller to be executed.
For another example, according to the principle that a test passing parameter window of memory training on the same device is close to a test passing parameter window of history training, the information of the test passing parameter window of history training is delivered to the central controller to be calculated to obtain a training interval which is preferable for memory training, then the central controller sends the training interval which is preferable for memory training to the micro-processing unit, and the micro-processing unit refers to the interval to perform memory training, so that the number of times of parameter testing of memory training is greatly reduced, and the memory training speed is greatly improved.
Further, the central controller may dynamically divide and allocate the memory training of the timing parameter according to the specific requirements of the memory training and the calculation rates of the central controller and the micro-processing unit, and may also designate a corresponding central controller or micro-processing unit to execute according to the specific requirements or conditions. For example, when there are two storage controllers, the first storage controller only needs to perform memory training on one timing parameter and only finds the middle value of the parameter interval; the second storage controller needs to perform memory training on the N time sequence parameters and also needs to calculate configuration values of the parameters according to a specific algorithm; the micro-processing unit in the first storage controller can complete the memory training with complete time sequence parameters; and the central controller divides the memory training of the N time sequence parameters, and completes the memory training of the N time sequence parameters step by step with the microprocessing unit in the second storage controller. The method can adjust the memory training subtask division method in real time according to the actual situation, and further improves the memory training efficiency of the multi-storage controller system.
Optionally, before the central controller starts memory training of timing parameters, the method further includes:
the central controller is communicated and interacted with the micro-processing unit through the communication unit;
preferably, the communication unit is one of: the system comprises a communication register arranged in a storage controller, a storage unit connected with the storage controller and a central controller and a preset communication mechanism.
Specifically, the method according to the embodiment of the present invention can coordinate the whole memory training process between the central controller and the micro-processing unit through the communication of the general purpose register in the storage controller. The parallelism of the multiple micro-processing units and the high efficiency of the micro-processing units for locally accessing the register of the storage controller are mainly utilized, a set of high-efficiency memory training scheme aiming at the multi-storage controller system is provided, and the memory efficiency of the multi-storage controller system can be greatly improved.
Alternatively, the communication unit may be configured as other preset mechanisms that enable communication between the storage controller and the central controller.
Optionally, after the central controller initiates memory training of timing parameters, the method includes:
the method comprises the steps that a micro-processing unit obtains a current state value stored in a communication unit, when the current state value is a first preset value, the micro-processing unit executes at least one memory training subtask with preset time sequence parameters in a storage controller to obtain a first subtask result, and the first subtask result is sent to a central controller;
or, the central processing unit obtains a current state value stored in the communication unit, and when the current state value is a second preset value, the central processing unit receives a first subtask result, then executes at least one memory training subtask with a preset time sequence parameter according to the first subtask result, and determines a configuration value of the preset time sequence parameter.
Optionally, the acquiring, by the microprocessor unit, a current state value stored in the communication unit, and when the current state value is a first preset value, the executing, by the microprocessor unit, at least one memory training subtask with a preset timing parameter in the storage controller to obtain a first subtask result, and sending the first subtask result to the central controller includes:
the micro-processing unit acquires a current state value stored in the communication unit and judges whether the current state value is a first preset value or not;
when the current state value is a first preset value, determining a preset parameter to be subjected to memory training according to the first preset value;
according to the preset parameters, configuring a parameter interval to be trained in a microprocessing unit;
the micro-processing unit traverses each parameter value in the parameter interval to be trained to carry out memory training;
and determining a result bitmap which meets the memory training requirement of the preset parameters, and writing the result bitmap serving as a first subtask result into a preset register of a storage controller.
Optionally, the obtaining, by the central processing unit, a current state value stored in the communication unit, and when the current state value is a second preset value, after receiving a first subtask result, the central processing unit executes at least one memory training subtask of a preset timing parameter according to the first subtask result, and determining the configuration value of the preset timing parameter includes:
the central processing unit acquires a current state value stored in the communication unit and judges whether the current state value is a second preset value or not;
when the current state value is a second preset value, judging whether a time sequence parameter corresponding result bitmap which finishes memory training needs to be read from a preset register of a storage controller or not according to the second preset value;
the central controller records the first subtask result;
the central controller executes at least one memory training subtask with preset time sequence parameters according to the result bitmap corresponding to the time sequence parameters of which the memory training is finished and the first subtask result;
and determining the configuration value of the preset time sequence parameter.
For example, the current state value may be set to S, and the central controller or the micro processing unit may be controlled to perform the next step by determining the parity of S.
For another example, the current state value may be set to MN, and it is determined whether M is a first preset value, or it is determined whether N is a second preset value.
Specifically, as shown in fig. 2, the method in this embodiment may implement efficient memory training of multiple storage controllers by using the following steps:
specifically, the memory training generally needs to train multiple parameters, and it is assumed that P parameters need to be trained. After the training of the 1 st parameter is completed, the optimal configuration value of the parameter is obtained through analysis, the optimal configuration value is configured into a current micro-processing unit (MP for short), the training of the 2 nd parameter is carried out on the basis, so that the accuracy of the training of the 2 nd parameter is improved, and the follow-up parameters are analogized in turn. 2P states are defined in the state register, so that the CPU and the MP can be conveniently coordinated and matched to complete the memory training process, and the states are defined as follows:
0- -written by the CPU, indicates that training of parameter 0 is to begin. After MP detects, begin to train parameter 0;
1- -written by MP, signifying the end of parameter 0 training, and writing the result bitmap into the data register. After the CPU detects the bitmap, reading the result bitmap;
and 2, writing by the CPU, namely analyzing the read parameter 0 training result bitmap, finding the optimal configuration value of the parameter 0, and writing the optimal configuration value into a data register. After MP detects, using the optimal configuration value of parameter 0 to update the parameter table, and starting to train parameter 1;
……
and 2P-2, written by the CPU, which indicates that the read result bitmap of the parameter P-2 is analyzed, the optimal configuration value of the parameter is found, and the optimal configuration value is written into the data register. After MP detects, using the optimal configuration value of the parameter to update the parameter table, and starting to train the parameter P-1;
2P-1- -written by MP, indicating that the training of parameter P-1 is finished, and writing the result bitmap into the data register. And after the CPU detects the parameter P-1, reading the result bitmap, analyzing and finding out the optimal configuration value of the parameter P-1.
Specifically, M MCs operate in parallel, and for the CPU, M threads are run to process interaction with M MPs, respectively, where a flow chart of 1 CPU thread is shown in fig. 2:
s301: write state 0 to the state register and initiate training of parameter 0 to MP.
S302: and reading the state register to obtain the state S.
S303: and judging whether the number S is an odd number, if so, indicating that the MP finishes the training of the parameter (S-1)/2, jumping to the step S304, otherwise, jumping to the step S302, and continuously reading the state of the state machine.
S304: the training result bitmap for parameter (S-1)/2 of MP writes is read from the data register.
S305: and recording a result bitmap of the type parameters of the current MC so as to perform secondary analysis.
S306: and judging whether the parameter is the last parameter, if so, ending the process, otherwise, jumping to the step S307.
S307: analyzing the optimal configuration value of the parameters according to the result bitmap, writing the optimal configuration value back to the data register, and writing the state S +1 into the state register to inform the MP of: the CPU end has completed the analysis and record of the current parameter and sends the optimal configuration value of the parameter, and the MP can train the next parameter on the basis of the times.
In addition, as shown in fig. 3, the flow of the thread on the side of the microprocessing unit (i.e., the MP end) in the method of the present embodiment may specifically adopt the following steps to implement the flash memory training; for example, the operation flow for the MP end may be as shown in fig. 3:
s401: and configuring the current MC by using the timing parameters in the default parameter table, wherein the default parameter table stores ideal configuration values of all the timing parameters.
S402: and reading the state register to obtain the state S.
S403: and judging whether the number S is an even number, if so, indicating that the CPU finishes reading and analyzing the result bitmap of the parameter S/2, writing the analyzed optimal parameter value into a data register, jumping to the step S404, otherwise, jumping to the step S402, and continuously reading the state of the state machine.
S404: setting the serial number of the current parameter type as S/2, and configuring the current parameter as the minimum legal value A of the type parameter in the current MC.
S405: and sending the data in a plurality of formats to the memory.
S406: and reading data from the memory.
S407: and judging whether the sent and received data are consistent. If the two are consistent, the step S408 is jumped to, otherwise, the step S409 is jumped to.
S408: each parameter has a result bitmap, and the length of the bitmap is equal to the length of the legal configuration value range of the parameter. The result of the parameter configuration value A is written into the bitmap bit0, the result of the configuration value A +1 is written into the bitmap bit1, and so on. This step indicates that the data transfer was successful, so a 1 is written to the bitmap corresponding bit.
S409: indicating that the data transfer failed, a 0 is written to the corresponding bit of the bitmap.
S410: and judging whether the current configuration value is the maximum legal value B. If not, go to step S411, otherwise go to step S412.
S411: the parameter configuration value is incremented for the next attempt at the parameter value.
S412: writing the result bitmap of the current parameters to the data register, writing state S +1 to the state register to inform the CPU: the MP end has finished training the parameter S/2 and writes the result bitmap into the data register, and the CPU end can read the result bitmap of the parameter on the basis.
S413: and judging whether the current parameter type is the last parameter type. If not, jumping to step S402, continuing the training of the next parameter type, otherwise ending the process.
Through the above structure and flow analysis of the multi-MC system efficient memory training, it can be known that the memory training of M MCs is performed in parallel. In the memory training process, although the CPU also needs to indirectly access the general register in the MC, only a small amount of state and result data transmission is carried out, and in the memory training process, a large amount of access to the MC control register is carried out through local direct access of the MP, so that the efficiency is greatly improved.
An embodiment of the present invention further provides a system for memory training, as shown in fig. 4, the system includes: the system comprises a central controller, at least two storage controllers connected in parallel and connected with the central controller, and at least one micro-processing unit arranged in the storage controllers; wherein:
the micro-processing unit is used for executing at least one memory training subtask in the storage controller after the central controller starts memory training of the time sequence parameters to obtain a first subtask result and sending the first subtask result to the central controller;
the central controller: the memory training device is used for starting memory training of a time sequence parameter, receiving a first subtask result, executing at least one memory training subtask according to the first subtask result, and determining a configuration value of the time sequence parameter.
The memory training system provided by the embodiment of the invention not only solves the problem that the prior art can not solve the memory training of a plurality of memory controller systems, but also can solve the problem that the memory training efficiency is not high only by simply expanding the prior art to adapt to a plurality of memory controller systems, the embodiment of the invention utilizes at least two micro-processing units and a central controller in the system to form a set of distributed system, and the memory training subtask with small calculation difficulty and large calculation amount in the memory training is delivered to the micro-processing unit which can quickly access the register of the memory controller, for example, the circular iterative operation subtask in the memory training; and the memory training subtask with high computational difficulty is handed to a central controller which can execute a high-level language and realize complex logic, such as the memory training result analysis and recording subtask.
Therefore, the system provided by the embodiment of the invention can fully exert the respective advantages of the central processing unit and the micro-processing unit to cooperate with each other to complete memory training, and the memory training efficiency of the multi-memory controller system is greatly improved; the memory training speed of the multi-memory controller system is greatly improved, and the development of artificial intelligence and high-performance calculation is promoted.
Optionally, the system further comprises:
the communication unit is used for carrying out communication interaction between the central controller and the micro-processing unit;
preferably, the communication unit is a communication register disposed in the storage controller, or a storage unit connected to the storage controller or the central controller, or a preset communication mechanism.
Optionally, the micro-processing unit comprises:
the acquisition module is used for acquiring the current state value stored in the communication unit;
the judging module is used for judging whether the current state value is a first preset value or not;
the determining module is used for determining a preset parameter to be subjected to memory training and a parameter interval to be trained according to the first preset value;
the configuration module is used for configuring a parameter interval to be trained;
and the first memory training module is used for traversing each parameter value in the parameter interval to be trained to perform memory training.
Optionally, the central controller comprises:
the acquisition module is used for acquiring the current state value stored in the communication unit;
the judging module is used for judging whether the current state value is a second preset value or not;
the reading module is used for judging whether a time sequence parameter corresponding result bitmap which finishes the memory training needs to be read from a preset register of the storage controller or not according to a second preset value when the current state value is the second preset value;
the recording module is used for recording the first subtask result;
the second memory training module is used for executing at least one memory training subtask with preset time sequence parameters according to the result bitmap corresponding to the time sequence parameters of which the memory training is finished and the first subtask result; and determining the configuration value of the preset time sequence parameter.
Specifically, as shown in fig. 5, the system according to this embodiment may implement efficient memory training of multiple storage controllers by using the following system structure:
the memory training scheme of the multi-memory controller system adopts a distributed mode and consists of 1 CPU and M MPs, wherein the MP is a microprocessing unit in the MC and can execute microcode, directly carry out configuration and reading operation on an MC register and carry out simple logic operation. As shown in fig. 5:
wherein the dashed double-headed arrows indicate the access of the CPU/MP to the custom status register and data register, and the solid double-headed arrows indicate the access of the MP to the MC control register and the data transmission loop.
After the memory training function is realized by using microcode, the memory training function is compiled together with the initialization microcode and operated in the MP. When the CPU needs to initiate the memory training, the CPU informs the MP to call the corresponding function, and the memory training is started.
The CPU and the MP are synchronized through the general registers in the MC, one general register is defined as a status register, and a plurality of general registers are defined as data registers. The CPU and the MP can only perform the write operation of the status register and the data register by one party at the same time according to the current status in the status register, so the problem of write competition can not occur, and no special mechanism is used for protection.
The CPU is responsible for initiating memory training, analyzing the memory training result bitmap and distributing the optimal parameter configuration value. M MPs access the MC register locally to perform memory training, transmit a memory training result bitmap to the CPU to obtain an optimal parameter value issued by the CPU, update a parameter table and prepare for training the next parameter. The reason why the analysis processing of the bitmap data of the memory training result is processed by the CPU side, rather than by the MP itself, is that the MP side runs assembly microcode, which makes it difficult to implement a complex data processing function and cannot implement a data storage and recording function.
The system of this embodiment may be configured to implement the technical solutions of the method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. The memory training method is characterized by comprising a central controller, at least two storage controllers which are connected with the central controller in parallel and at least one microprocessing unit arranged in the storage controllers;
the central controller starts the memory training of the time sequence parameters;
executing at least one memory training subtask in a storage controller by a micro-processing unit to obtain a first subtask result and sending the first subtask result to a central controller;
and after receiving the first subtask result, the central controller executes at least one memory training subtask according to the first subtask result, and determines the configuration value of the time sequence parameter.
2. The method of claim 1, wherein the memory training of the timing parameters is predesigned as at least two subtasks and is performed by a designated central controller or a micro-processing unit;
or the memory training of the time sequence parameters is dynamically divided into at least two subtasks by the central controller according to preset conditions, and the corresponding central controller or the micro-processing unit is appointed to execute.
3. The method of claim 1 or 2, wherein the memory-trained subtasks include at least one of: the method comprises a loop iteration calculation subtask, an optimal configuration value calculation subtask of a time sequence parameter, a memory training result analysis subtask, a memory training result recording subtask and a training interval calculation subtask optimized by memory training.
4. The method of any of claims 1-3, wherein prior to the central controller initiating memory training of timing parameters, the method further comprises:
the central controller is communicated and interacted with the micro-processing unit through the communication unit;
preferably, the communication unit is one of: the system comprises a communication register arranged in a storage controller, a storage unit connected with the storage controller and a central controller and a preset communication mechanism.
5. The method of claim 4, wherein after the central controller initiates memory training of timing parameters, the method comprises:
the method comprises the steps that a micro-processing unit obtains a current state value stored in a communication unit, when the current state value is a first preset value, the micro-processing unit executes at least one memory training subtask with preset time sequence parameters in a storage controller to obtain a first subtask result, and the first subtask result is sent to a central controller;
or, the central processing unit obtains a current state value stored in the communication unit, and when the current state value is a second preset value, the central processing unit receives a first subtask result, then executes at least one memory training subtask with a preset time sequence parameter according to the first subtask result, and determines a configuration value of the preset time sequence parameter.
6. The method of claim 5, wherein the obtaining, by the MPU, a current state value stored in the communication unit, and when the current state value is a first preset value, the executing, by the MPU, at least one memory training subtask with a preset timing parameter in the storage controller to obtain a first subtask result and sending the first subtask result to the central controller comprises:
the micro-processing unit acquires a current state value stored in the communication unit and judges whether the current state value is a first preset value or not;
when the current state value is a first preset value, determining a preset parameter to be subjected to memory training according to the first preset value;
according to the preset parameters, configuring a parameter interval to be trained in a microprocessing unit;
the micro-processing unit traverses each parameter value in the parameter interval to be trained to carry out memory training;
and determining a result bitmap which meets the memory training requirement of the preset parameters, and writing the result bitmap serving as a first subtask result into a preset register of a storage controller.
7. The method according to claim 5 or 6, wherein the central processing unit obtains a current state value stored in the communication unit, and when the current state value is a second preset value, after the central processing unit receives a first subtask result, the central processing unit executes at least one memory training subtask of a preset timing parameter according to the first subtask result, and determining the configuration value of the preset timing parameter includes:
the central processing unit acquires a current state value stored in the communication unit and judges whether the current state value is a second preset value or not;
when the current state value is a second preset value, judging whether a time sequence parameter corresponding result bitmap which finishes memory training needs to be read from a preset register of a storage controller or not according to the second preset value;
the central controller records the first subtask result;
the central controller executes at least one memory training subtask with preset time sequence parameters according to the result bitmap corresponding to the time sequence parameters of which the memory training is finished and the first subtask result;
and determining the configuration value of the preset time sequence parameter.
8. A system for memory training, comprising: the system comprises a central controller, at least two storage controllers connected in parallel and connected with the central controller, and at least one micro-processing unit arranged in the storage controllers; wherein:
the micro-processing unit is used for executing at least one memory training subtask in the storage controller after the central controller starts memory training of the time sequence parameters to obtain a first subtask result and sending the first subtask result to the central controller;
the central controller: the memory training device is used for starting memory training of a time sequence parameter, receiving a first subtask result, executing at least one memory training subtask according to the first subtask result, and determining a configuration value of the time sequence parameter.
9. The system according to claim 8, further comprising:
the communication unit is used for carrying out communication interaction between the central controller and the micro-processing unit;
preferably, the communication unit is a communication register disposed in the storage controller, or a storage unit connected to the storage controller or the central controller, or a preset communication mechanism.
10. The system of claim 8 or 9, wherein the micro-processing unit comprises:
the acquisition module is used for acquiring the current state value stored in the communication unit;
the judging module is used for judging whether the current state value is a first preset value or not;
the determining module is used for determining a preset parameter to be subjected to memory training and a parameter interval to be trained according to the first preset value;
the configuration module is used for configuring a parameter interval to be trained;
and the first memory training module is used for traversing each parameter value in the parameter interval to be trained to perform memory training.
11. The system according to claim 8 or 9, wherein the central controller comprises:
the acquisition module is used for acquiring the current state value stored in the communication unit;
the judging module is used for judging whether the current state value is a second preset value or not;
the reading module is used for judging whether a time sequence parameter corresponding result bitmap which finishes the memory training needs to be read from a preset register of the storage controller or not according to a second preset value when the current state value is the second preset value;
the recording module is used for recording the first subtask result;
the second memory training module is used for executing at least one memory training subtask with preset time sequence parameters according to the result bitmap corresponding to the time sequence parameters of which the memory training is finished and the first subtask result; and determining the configuration value of the preset time sequence parameter.
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