CN111966410A

CN111966410A - Startup processing method and device, electronic equipment and storage medium

Info

Publication number: CN111966410A
Application number: CN202010763585.8A
Authority: CN
Inventors: 张宝祺; 董骥; 王焕东; 吴胜
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2020-11-20
Anticipated expiration: 2040-07-31
Also published as: CN111966410B

Abstract

The embodiment of the invention provides a starting processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method is applied to an electronic device comprising at least two processing units, wherein each processing unit comprises at least two processing cores and comprises the following steps: receiving a starting instruction aiming at the electronic equipment; responding to the starting instruction, respectively performing memory training on the at least two processing units through at least two processing cores included by a target processing unit to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit which stores a program required by the memory training; and controlling the electronic equipment to start through the memory control parameters respectively corresponding to the at least two processing units. The invention can shorten the time length of memory training and improve the efficiency of memory training.

Description

Startup processing method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a boot processing method and apparatus, an electronic device, and a storage medium.

Background

In the field of computer technology, a computer may be any device that provides a service to a user, and a memory of the device needs to be controlled according to a memory control parameter, where the memory control parameter may include, but is not limited to: the method comprises the steps of charging time and reading delay time, wherein the memory cannot be read and accessed in the charging time, and if data are not read in the reading delay time, reading abnormity is judged.

In the prior art, the memory control parameter may be obtained by the device through memory training, and during the memory training process, the memory control parameter is continuously adjusted to obtain a better memory control parameter. Specifically, if the device has multiple CPUs (Central Processing units), the multiple CPUs may be sorted according to a certain rule, and then memory training is performed on the multiple CPUs one by one according to the order, so as to obtain the memory control parameter corresponding to each CPU.

The inventor finds that the memory training process of the scheme is long in time and low in efficiency in the research process of the scheme.

Disclosure of Invention

In view of the above, embodiments of the present invention are proposed in order to provide a start-up processing method that overcomes or at least partially solves the above mentioned problems.

Correspondingly, the embodiment of the invention also provides a starting processing device, electronic equipment and a storage medium, which are used for ensuring the realization and application of the method.

In order to solve the above problem, an embodiment of the present invention discloses a start processing method, which is applied to an electronic device including at least two processing units, where the processing unit includes at least two processing cores, and includes:

receiving a starting instruction aiming at the electronic equipment;

responding to the starting instruction, respectively performing memory training on the at least two processing units through at least two processing cores included by a target processing unit to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit which stores a program required by the memory training;

and controlling the electronic equipment to start through the memory control parameters respectively corresponding to the at least two processing units.

Optionally, the method further comprises:

performing at least one of the following processes by the target processing core: initializing the sub-devices of the electronic device, constructing a loading environment of a kernel program, and loading the kernel program, wherein the target processing core is a processing core for performing memory training on the target processing unit.

Optionally, the method further comprises:

storing the memory control parameters respectively corresponding to the at least two processing units into the storage areas corresponding to the target processing unit;

the controlling the electronic device to start through the memory control parameters respectively corresponding to the at least two processing units includes:

acquiring memory control parameters respectively corresponding to the at least two processing units from a storage area corresponding to the target processing unit;

and starting the file system of the electronic equipment through the loaded kernel program, and controlling the processing units to use the memory through the memory control parameters respectively corresponding to the at least two processing units in the starting process.

Optionally, the method further comprises:

after memory training of the processing unit is finished, writing an end mark in a target storage position corresponding to the processing unit, wherein the target storage position is located in a storage area of the target processing unit;

the starting of the file system of the electronic device by the loaded kernel program comprises:

and starting a file system of the electronic equipment through the loaded kernel program under the condition that the end mark is written in the target storage position.

Optionally, before the memory training is performed on the at least two processing units by the at least two processing cores included in the target processing unit, the method further includes:

acquiring an initialization program from a storage area corresponding to a target processing unit;

and respectively initializing at least two processing cores of the processing unit by the initialization program.

The embodiment of the present invention further discloses a start processing apparatus, which is applied to an electronic device including at least two processing units, where the processing unit includes at least two processing cores, and includes:

the starting instruction receiving module is used for receiving a starting instruction aiming at the electronic equipment;

the memory training module is used for responding to the starting instruction, respectively performing memory training on the at least two processing units through at least two processing cores included by a target processing unit so as to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit which stores a program required by the memory training;

and the starting control module is used for controlling the electronic equipment to start through the memory control parameters respectively corresponding to the at least two processing units.

Optionally, the apparatus further comprises:

a preparation processing module for performing at least one of the following processes by the target processing core: initializing the sub-devices of the electronic device, constructing a loading environment of a kernel program, and loading the kernel program, wherein the target processing core is a processing core for performing memory training on the target processing unit.

Optionally, the apparatus further comprises:

the memory control parameter storage module is used for storing the memory control parameters respectively corresponding to the at least two processing units into the storage areas corresponding to the target processing unit;

the start control module includes:

the memory control parameter acquisition submodule is used for acquiring memory control parameters respectively corresponding to the at least two processing units from the storage areas corresponding to the target processing unit;

and the starting control submodule is used for starting the file system of the electronic equipment through the loaded kernel program and controlling the processing units to use the memory through the memory control parameters respectively corresponding to the at least two processing units in the starting process.

Optionally, the apparatus further comprises:

an end mark writing module, configured to write an end mark in a target storage location corresponding to the processing unit after memory training on the processing unit is completed, where the target storage location is located in a storage area of the target processing unit;

the start control sub-module includes:

and the file system loading unit is used for starting the file system of the electronic equipment through the loaded kernel program under the condition that the end mark is written in the target storage position.

Optionally, the apparatus further comprises:

the initialization program acquisition module is used for acquiring an initialization program from a storage area corresponding to the target processing unit;

and the initialization module is used for respectively initializing at least two processing cores of the processing unit through the initialization program.

An embodiment of the present invention also discloses an electronic device, including a memory, and one or more programs, where the one or more programs are stored in the memory, and configured to be executed by one or more processors, and the one or more programs include instructions for:

receiving a starting instruction aiming at an electronic device, wherein the electronic device comprises at least two processing units, and the processing units comprise at least two processing cores;

The embodiment of the invention also discloses a readable storage medium, and when instructions in the storage medium are executed by a processor of the electronic equipment, the electronic equipment can execute one or more starting processing methods in the embodiment of the invention.

The embodiment of the invention has the following advantages:

in the embodiment of the invention, the memory training can be respectively carried out on the at least two processing units through the at least two processing cores of the processing unit which stores the program required by the memory training, before the memory training process, each processing core can acquire the program required by the memory training from the processing unit where the processing core is located, the memory training is carried out on the at least two processing units in a parallel mode, and the memory training is simultaneously carried out on the at least two processing cores.

Drawings

FIG. 1 is a flow chart of the steps of one embodiment of a boot process method of the present invention;

FIG. 2 is a block diagram of an embodiment of a boot processing apparatus according to the present invention;

FIG. 3 is a block diagram illustrating an electronic device for boot-up processing according to an example embodiment.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

One of the core concepts of the embodiments of the present invention is that, for an electronic device having a plurality of processing units, a plurality of processing cores included in the processing unit are used to perform memory training on the plurality of processing units, and compared with performing memory training on the plurality of processing units in sequence, performing memory training on the plurality of processing units by using the plurality of processing cores, thereby implementing parallelization of memory training in time. For example, for an electronic device having 4 processing units, if memory training is performed on the 4 processing units sequentially, and the duration required by the memory training of each processing unit is T, the total duration of the memory training performed on the 4 processing units is 4 × T; in the present invention, if one of the processing units is 4 cores, and the processing unit includes 4 processing cores, the 4 processing cores may be respectively adopted to respectively perform memory training on the 4 processing units, so that the total duration of the memory training performed on the 4 processing units is T. Therefore, the memory training method and the memory training device shorten the memory training time and improve the memory training efficiency.

In addition, the selected processing core may be a processing core of a processing unit in which a program required by memory training is stored, so that the processing core can directly acquire the program required by memory training from the processing unit in which the processing core is located before training, thereby simplifying the process of acquiring the program required by memory training, shortening the time for acquiring the program required by memory training, further shortening the time for memory training, and improving the efficiency for memory training.

Referring to fig. 1, a flowchart illustrating steps of an embodiment of a method for starting processing according to the present invention is shown, and is applied to an electronic device including at least two processing units, where the processing units include at least two processing cores, and the method specifically includes the following steps:

step 101, receiving a starting instruction for the electronic device.

The start instruction is an operation instruction of a user to a designated button of the electronic device, for example, a pressing operation to a power key. After the electronic device receives the starting instruction, each processing unit of the electronic device is powered on, so that the processing unit starts the electronic device.

The electronic device of the invention may be any device having a processing unit, wherein the processing unit may be a unit with data processing capabilities, typically a CPU. The processing unit may be multi-core, and in the embodiment of the present invention, the multi-core included in the processing unit is referred to as a plurality of processing cores.

Step 102, in response to the start instruction, performing memory training on the at least two processing units through at least two processing cores included in a target processing unit, so as to adjust memory control parameters corresponding to the at least two processing units, respectively, where the target processing unit is a processing unit storing a program required by the memory training.

The program required by the memory training is called a memory training program, and the memory training program is used for expressing the implementation logic of the memory training. The memory training is used for continuously adjusting the memory control parameters of the processing unit and stopping the memory training after the preset conditions are reached, and the obtained memory control parameters are the better memory control parameters obtained by the memory training. The preset condition is that the establishment time of a signal is greater than or equal to a first preset time length, the retention time of the signal is greater than or equal to the preset time length, the reference voltage of a configuration data line of the electronic device reaches a preset target voltage, the signal is a representation mode of data, the establishment time of the signal is a time interval that data has arrived and is stable and continuous before a rising edge of a clock signal arrives, the retention time of the signal is a time that the data is stable and unchanged after the rising edge of the clock signal of a trigger arrives, and the data is kept unchanged in the retention time so that the data is stably read.

The memory control parameters in the above process include but are not limited to: charging time, reading delay time and writing delay time, wherein data cannot be read or written in the charging time; the read delay time is used for controlling the maximum delay time of writing, and after a read request is sent, if data is not read within the read delay time, the read failure is represented; after sending the write request, if no data is written in the write delay time, the write failure is represented.

Embodiments of the present invention may allocate at least two processing cores of a target processing unit to each processing unit, i.e. establish a correspondence between a processing core and a processing unit.

In a first example, the number of processing cores of the target processing unit is greater than or equal to the number of processing units, such that each processing unit may be assigned a corresponding processing core, resulting in a one-to-one correspondence between processing cores and processing units. For example, for 3 processing units CPU1, CPU2, and CPU3, where the target processing unit CPU1 has 3 processing COREs CORE1, CORE2, and CORE3, CORE1 may be allocated to CPU1, CORE2 may be allocated to CPU2, and CORE3 may be allocated to CPU3, so that CORE1 memory-trains CPU1, CORE2 memory-trains CPU2, and CORE3 memory-trains CPU 3.

In a second example, the number of processing cores of the target processing unit is smaller than the number of processing units, so that each processing unit cannot be allocated with a corresponding processing core, and at this time, the same processing core may be allocated to a plurality of processing units, one processing core corresponding to one or more processing units. In order to shorten the memory training time as much as possible, the processing cores may be uniformly distributed with the processing units, so that the number of the processing units corresponding to one processing core is close to that of the processing units corresponding to one processing core. For example, for 5 processing units, namely, CPU1, CPU2, CPU3, CPU4 and CPU5, the target processing unit, namely, CPU1, has 3 processing COREs, namely, CORE1, CORE2, CORE3 and CORE4, CORE1 is allocated to CPU1 and CPU2, CORE2 is allocated to CPU3 and CPU4, and CORE3 is allocated to CPU5, so that CORE1 performs memory training on CPU1 and CPU2, CORE2 performs memory training on CPU3 and CPU4, and CORE3 performs memory training on CPU 5.

It should be noted that, when a processing CORE performs memory training on at least two processing units, it needs to perform memory training sequentially, for example, for CORE1 described above, it may perform memory training on CPU1 first, and then perform memory training on CPU 2.

It can be seen that the duration of the memory training of the first example can be shortened to the greatest extent, the degree of shortening can be represented by a shortening degree parameter, and the shortening degree parameter has a positive relationship with the number of processing units: the more the number of the processing units is, the larger the shortening degree parameter is, and the larger the shortening degree is; the smaller the number of processing units, the smaller the shortening degree parameter and the smaller the shortening degree; the memory is shortened to a lesser extent in the second example than in the first example, and the shortening parameter has a reverse relationship with the number of processing units and a forward relationship with the number of processing cores of the target processing unit: if the smaller the number of the processing units is, the larger the number of the processing cores of the target processing unit is, the larger the shortening degree parameter is; the shortening degree parameter is smaller if the larger the number of processing units, the larger the number of processing cores of the target processing unit.

Thus, in the first example, the number of processing units may be used as the shortening degree parameter, or a linear/nonlinear transformation of the shortening degree parameter may be used as the shortening degree parameter, but a positive relationship between the shortening degree parameter and the number of processing units in the first example is to be ensured; in the second example, the ratio between the number of processing cores of the target processing unit and the number of processing units, or the linear/nonlinear transformation of the ratio may be used as the shortening degree parameter, but the forward relationship between the shortening degree parameter and the number of processing cores, and the reverse relationship between the number of processing units in the second example are ensured.

In addition, since the efficiency of the memory training can be regarded as having an inverse relationship with the duration, the improvement degree parameter of the efficiency of the memory training can be determined according to the above relationship, and specifically, the reciprocal of the shortening degree parameter or the linear/nonlinear conversion thereof can be used as the improvement degree parameter.

Step 103, controlling the electronic device to start through the memory control parameters respectively corresponding to the at least two processing units.

It can be understood that, during the process of starting up the electronic device, the program and data required for starting up need to be loaded into the memory of the processing unit, so that the use of the memory of the processing unit during the starting up process needs to be controlled by the memory control parameter. For example, if there are 3 processing units, CPU1, CPU2, and CPU3, the memory usage of CPU1 may be controlled by the memory control parameters of CPU1, the memory usage of CPU2 may be controlled by the memory control parameters of CPU2, and the memory usage of CPU3 may be controlled by the memory control parameters of CPU 3.

In practical applications, the memory controller may be called to control the memory.

It should be noted that, the memory training is performed in the starting process, so that the starting time of the electronic device can be shortened by shortening the time of the memory training, and the starting efficiency is further improved.

Optionally, after step 102 and before step 103, the method further comprises step 104:

step 104, performing at least one of the following processes by the target processing core: initializing the sub-devices of the electronic device, constructing a loading environment of a kernel program, and loading the kernel program, wherein the target processing core is a processing core for performing memory training on the target processing unit.

Wherein, the sub-devices of the electronic device include but are not limited to: the initialization of the sub-device may be performed by setting each parameter of the sub-device to a default value, for example, setting the frequency of the microphone to a default frequency, setting the transmission rate of the USB interface to a default transmission rate, setting the IP (internet protocol) address and the port of the network card to a default address and a default port, respectively, and setting the sampling frequency of the sound card to a default frequency.

The loading environment of the kernel program is constructed to prepare for loading the kernel program, and the loading environment may include a hardware environment and a software environment required for loading the kernel program.

After the loading environment is prepared, a kernel program may be loaded into a storage area of the target processing unit from a disk of the electronic device, where the kernel program is a program for starting a file system, a system of the electronic device generally includes a kernel system and a file system, the kernel system is composed of a plurality of kernel programs, and the starting electronic device is the kernel system of the starting electronic device, so as to start the file system through the kernel system. The kernel System is usually a BIOS (Basic Input Output System), the kernel System is configured when the electronic device leaves a factory, and the file System may also be referred to as an Operating System (OS), and may be configured when the electronic device leaves the factory or may be installed by a user after the user purchases the electronic device.

In the invention, the target processing core is the processing core for performing the memory training on the target processing unit, and the target processing core is the processing core of the target processing unit, so that the problem of performing the memory training across nodes does not exist, and the target processing core completes the memory training firstly on the premise of full memory. Based on this, when the target processing core completes the memory training, but the other processing cores do not complete the memory training, the target processing core completes the initialization of the child device, the construction of the loading environment, the loading of the kernel program and other processing processes, so that the memory training time can be further shortened, and the memory training efficiency can be improved. For example, for 3 processing units, namely, the CPU1, the CPU2 and the CPU3, among them, the target processing unit, namely, the CPU1 has 3 processing COREs, namely, CORE1, CORE2 and CORE3, the CORE1 performs memory training on the CPU1, the CORE2 performs memory training on the CPU2, and the CORE3 performs memory training on the CPU3, and since the CORE1 is a processing CORE performing memory training on the target processing unit, namely, the CPU1, the CORE1 performs the rest of the processing procedures as the target processing CORE.

It can be understood that the invention adopts the target processing core which completes the memory training first to perform the rest of the processing procedures after the memory training, and if the processing core which does not complete the memory training first is adopted to perform the rest of the processing procedures, the memory training of the processing core needs to be completed, so that the waiting time is increased, and the memory training time is longer.

Optionally, after step 102, the method further comprises step 105:

and 105, storing the memory control parameters respectively corresponding to the at least two processing units into the storage areas corresponding to the target processing unit.

In practical applications, the memory control parameter is an important parameter of the training result parameter, but there are some other training result parameters, including but not limited to: the memory training time of each processing core, the mark of success or failure of training and the failure reason. Based on this, the training result parameter can be stored in a storage area of the target processing unit, wherein the storage area can be a storage space designated in a flash (flash memory), so that the training result parameter is not easy to lose, and the flash can be in communication connection with the target processing unit through an SPI (Serial Peripheral Interface).

Of course, the storage area may also select other storage devices, which is not limited by the present invention.

Based on step 105, said step 103 comprises sub-steps 1031 to 1032:

and a substep 1031, obtaining the memory control parameters respectively corresponding to the at least two processing units from the storage areas corresponding to the target processing unit.

Specifically, a storage area may be allocated to each processing unit to store the memory control parameter of the processing unit, so as to obtain the memory control parameter from the corresponding storage area according to the processing unit. It can be understood that, for each processing unit, a plurality of memory control parameters may be stored in a key-value pair manner, with the identifier of the memory control parameter as a key and the value of the memory control parameter as a value.

In sub-step 1032, the file system of the electronic device is started through the loaded kernel program, and in the starting process, the use of the memory by the processing units is controlled through the memory control parameters respectively corresponding to the at least two processing units.

As described in the foregoing description of the kernel program in step 104, step 104 completes the loading of the kernel program through the target processing core, so that the kernel program, and thus the file system, can be started, during the process of starting the file system.

Optionally, after step 102, the method further comprises step 106:

and 106, after finishing memory training on the processing unit, writing an end mark in a target storage position corresponding to the processing unit, where the target storage position is located in a storage area of the target processing unit.

In the present invention, a storage area may be provided for each processing unit in the storage area of the target processing unit to store the end flag of the processing unit. To reduce the waste of the memory area, the end flag may be set to 1 bit, and the end flags of the plurality of processing units may be concatenated into one byte, for example, the end flag is represented by a value "1"; in addition, a default value can be written into the target storage position in the initial state, which represents that the operation is not finished. For example, if there are processing units CPU1, CPU2, and CPU3, the concatenated bytes may be: 00000000, after the CPU1 finishes the memory training, the concatenated bytes may be: 10000000, after the CPU2 finishes the memory training, the concatenated bytes may be: 11000000, after the CPU3 finishes the memory training, the concatenated bytes may be: 11100000.

based on the step 106, the sub-step 1032 of starting the file system of the electronic device by the loaded kernel program includes the sub-step 10321 of:

sub-step 10321 of starting a file system of the electronic device by the loaded kernel program in case the end flag is written in the target storage location.

Specifically, under the condition that the target storage positions of the processing units are all end marks, starting a file system of the electronic equipment through a loaded kernel program; in the case where the end flag is not written in the target storage location of at least one of the processing units, the file system of the electronic device is not started by the loaded kernel program.

In the invention, when the ending mark of the processing unit is spliced into a byte, whether the target storage positions of the processing units are all ending marks can be determined through the value of the byte; for example, if the byte is 11100000 ═ 224, it is determined that all of the target storage locations of the processing units are end flags.

The invention can accurately represent whether the memory training is finished or not through the end mark, in addition, the end mark is stored in the storage area corresponding to the target processing unit, the cross-node acquisition of the end mark is avoided, the speed of writing the end mark and reading the end mark is improved, the memory training time length is further shortened, and the memory training efficiency is improved.

Optionally, before the step 102, a step 107 is further included:

step 107, the initialization program is acquired from the storage area corresponding to the target processing unit.

The initialization program is a program in the BIOS, and is used for initializing the processing unit, and for different processing units, the initialization program can be different and can be applied to different processing units to perform different processing tasks; the initialization program may also be the same for different processing units, and may be applied to a scenario where different processing units adopt the same processing task, and the processing logic of different processing units is the same.

Step 108, initializing at least two processing cores of the processing unit by the initialization program respectively.

The initializing the processing core for allocating the resource of the processing unit to the processing core may include, but is not limited to: allocating the memory of the processing unit to the processing core, closing the interrupt, configuring the exception vector, initializing the cache, initializing the TLB (translation lookaside buffer, which may be referred to as a fast table for short), and clearing the mailbox.

After the initialization of the processing cores, the processing cores of the processors other than the target processor enter an idle mode so as not to perform any operation, and the processing cores of the target processor do not enter the idle mode, and step 102 is performed for memory training.

In summary, in the embodiment of the present invention, memory training may be performed on at least two processing units respectively through at least two processing cores of a processing unit in which a program required for memory training is stored, before a memory training process, each processing core may obtain the program required for memory training from the processing unit in which the processing core is located, and perform memory training on at least two processing units in a parallel manner, where the at least two processing cores perform memory training on at least two processing units simultaneously, and compared with performing memory training on multiple processing units sequentially, the memory training time is shortened and the memory training efficiency is improved.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

Referring to fig. 2, a block diagram of an embodiment of a boot processing apparatus according to the present invention is shown, and is applied to an electronic device including at least two processing units, where the processing units include at least two processing cores, and the apparatus 200 may specifically include the following modules:

a starting instruction receiving module 201, configured to receive a starting instruction for the electronic device.

A memory training module 202, configured to perform memory training on the at least two processing units through at least two processing cores included in a target processing unit in response to the start instruction, so as to adjust memory control parameters respectively corresponding to the at least two processing units, where the target processing unit is a processing unit storing a program required by the memory training.

The starting control module 203 is configured to control the electronic device to start through the memory control parameters respectively corresponding to the at least two processing units.

Optionally, the apparatus further comprises a preparation processing module:

Optionally, the apparatus further includes a memory control parameter storage module:

and the memory control parameter storage module is used for storing the memory control parameters respectively corresponding to the at least two processing units into the storage areas corresponding to the target processing unit.

Based on the memory control parameter storage module, the start control module comprises a memory control parameter acquisition submodule and a start control submodule:

and the memory control parameter acquisition submodule is used for acquiring memory control parameters respectively corresponding to the at least two processing units from the storage areas corresponding to the target processing unit.

Optionally, the apparatus further comprises an end flag writing module:

based on the end mark writing module, the start control submodule includes a file system loading unit:

Optionally, the apparatus further includes an initialization program obtaining module and an initialization module:

and the initialization program acquisition module is used for acquiring the initialization program from the storage area corresponding to the target processing unit.

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

FIG. 3 is a block diagram illustrating a configuration of an electronic device 300 for boot processing according to an example embodiment. For example, the electronic device 300 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.

Referring to fig. 3, electronic device 300 may include one or more of the following components: processing component 302, memory 304, power component 306, multimedia component 308, audio component 310, input/output (I/O) interface 312, sensor component 314, and communication component 316.

The processing component 302 generally controls overall operation of the electronic device 300, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing elements 302 may include one or more processors 320 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 302 can include one or more modules that facilitate interaction between the processing component 302 and other components. For example, the processing component 302 can include a multimedia module to facilitate interaction between the multimedia component 308 and the processing component 302.

The memory 304 is configured to store various types of data to support operations at the device 300. Examples of such data include instructions for any application or method operating on the electronic device 300, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 304 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

The power supply component 306 provides power to the various components of the electronic device 300. The power components 306 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 300.

The multimedia component 308 comprises a screen providing an output interface between the electronic device 300 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 308 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 300 is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The audio component 310 is configured to output and/or input audio signals. For example, the audio component 310 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 300 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 304 or transmitted via the communication component 316. In some embodiments, audio component 310 also includes a speaker for outputting audio signals.

The I/O interface 312 provides an interface between the processing component 302 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

Sensor assembly 314 includes one or more sensors for providing various aspects of status assessment for electronic device 300. For example, sensor assembly 314 may detect an open/closed state of device 300, the relative positioning of components, such as a display and keypad of electronic device 300, sensor assembly 314 may also detect a change in the position of electronic device 300 or a component of electronic device 300, the presence or absence of user contact with electronic device 300, the orientation or acceleration/deceleration of electronic device 300, and a change in the temperature of electronic device 300. Sensor assembly 314 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 314 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 314 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 316 is configured to facilitate wired or wireless communication between the electronic device 300 and other devices. The electronic device 300 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 316 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 316 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 300 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.

In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as the memory 304, that are executable by the processor 320 of the electronic device 300 to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

A non-transitory computer readable storage medium in which instructions, when executed by a processor of an electronic device, enable the electronic device to perform a boot processing method, the method comprising:

Optionally, the method further comprises:

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a predictive manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The foregoing describes in detail a method, an apparatus, an electronic device, and a storage medium for start-up processing provided by the present invention, and a specific example is applied in the description to explain the principle and the implementation of the present invention, and the description of the foregoing embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A boot processing method applied to an electronic device including at least two processing units, each of the processing units including at least two processing cores, the method comprising:

receiving a starting instruction aiming at the electronic equipment;

2. The method of claim 1, further comprising:

3. The method of claim 2, further comprising:

4. The method of claim 3, further comprising:

5. The method according to any one of claims 1 to 4, further comprising, before the memory training of the at least two processing units by the at least two processing cores included in the target processing unit, respectively:

6. A boot processing apparatus applied to an electronic device including at least two processing units, the processing units including at least two processing cores, comprising:

7. The apparatus of claim 6, further comprising:

8. The apparatus of claim 7, further comprising:

the start control module includes:

9. The apparatus of claim 8, further comprising:

the start control sub-module includes:

10. The apparatus of any one of claims 6 to 9, further comprising:

11. An electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors the one or more programs including instructions for:

12. A readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the boot processing method of any of method claims 1 to 5.