CN111966410B

CN111966410B - Start-up processing method and device, electronic equipment and storage medium

Info

Publication number: CN111966410B
Application number: CN202010763585.8A
Authority: CN
Inventors: 张宝祺; 董骥; 王焕东; 吴胜
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2023-11-14
Anticipated expiration: 2040-07-31
Also published as: CN111966410A

Abstract

The embodiment of the invention provides a starting processing method, a starting processing device, electronic equipment and a storage medium, and relates to the technical field of computers. Wherein the method is applied to an electronic device comprising at least two processing units, the processing units comprising at least two processing cores, comprising: receiving a starting instruction aiming at the electronic equipment; responding to the starting instruction, respectively performing memory training on the at least two processing units through at least two processing cores included in a target processing unit to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit storing a program required by the memory training; and controlling the electronic equipment to be started through the memory control parameters respectively corresponding to the at least two processing units. The invention can shorten the time length of memory training and improve the efficiency of memory training.

Description

Start-up processing method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a startup processing method, a startup processing device, an electronic device, and a storage medium.

Background

In the field of computer technology, a computer may be any device that provides services to a user, where the memory of the device needs to be controlled according to memory control parameters, where the memory control parameters may include, but are not limited to: charging time and reading delay time, wherein the memory cannot be read and accessed in the charging time, and if the data is not read in the reading delay time, the abnormal reading is judged.

In the prior art, the memory control parameter may be obtained by the device through memory training, and in the process of memory training, the memory control parameter is continuously adjusted to obtain a better memory control parameter. Specifically, if there are multiple CPUs (Central Processing Unit, central processing units) in the device, the multiple CPUs may be ordered according to a certain rule, and then memory training may be performed on the multiple CPUs one by one according to the order, so as to obtain the memory control parameters corresponding to each CPU.

The inventor finds that the memory training process of the scheme needs longer time and has lower efficiency in the research process of the scheme.

Disclosure of Invention

In view of the foregoing, embodiments of the present invention have been developed to provide a startup processing method that overcomes, or at least partially solves, the foregoing problems.

Correspondingly, the embodiment of the invention also provides a starting processing device, electronic equipment and a storage medium, which are used for ensuring the realization and the application of the method.

In order to solve the above-mentioned problems, an embodiment of the present invention discloses a startup processing method applied to an electronic device including at least two processing units, where the processing units include at least two processing cores, including:

receiving a starting instruction aiming at the electronic equipment;

responding to the starting instruction, respectively performing memory training on the at least two processing units through at least two processing cores included in a target processing unit to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit storing a program required by the memory training;

and controlling the electronic equipment to be started through the memory control parameters respectively corresponding to the at least two processing units.

Optionally, the method further comprises:

performing at least one of the following processing by the target processing core: initializing sub-equipment of the electronic equipment, constructing a loading environment of a kernel program, and loading the kernel program, wherein the target processing core is a processing core for performing memory training on the target processing unit.

Optionally, the method further comprises:

storing the memory control parameters corresponding to the at least two processing units respectively into the storage areas corresponding to the target processing units;

the controlling the electronic device to be started through the memory control parameters respectively corresponding to the at least two processing units includes:

acquiring memory control parameters corresponding to the at least two processing units respectively from a storage area corresponding to the target processing unit;

and starting a file system of the electronic equipment through the loaded kernel program, and controlling the use of the memory by the processing units through the memory control parameters respectively corresponding to the at least two processing units in the starting process.

Optionally, the method further comprises:

after the memory training of the processing unit is finished, writing an ending mark in a target storage position corresponding to the processing unit, wherein the target storage position is positioned in a storage area of the target processing unit;

the starting the file system of the electronic device through the loaded kernel program comprises the following steps:

and starting a file system of the electronic device through the loaded kernel program under the condition that the ending mark is written in the target storage position.

Optionally, before the at least two processing cores included in the target processing unit respectively perform memory training on the at least two processing units, the method further includes:

acquiring an initialization program from a storage area corresponding to a target processing unit;

and initializing at least two processing cores of the processing unit respectively through the initializing program.

The embodiment of the invention also discloses a starting processing device which is applied to the electronic equipment comprising at least two processing units, wherein the processing units comprise at least two processing cores and comprise:

the starting instruction receiving module is used for receiving a starting instruction aiming at the electronic equipment;

the memory training module is used for responding to the starting instruction, respectively performing memory training on the at least two processing units through at least two processing cores included in a target processing unit so as to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit storing a program required by the memory training;

and the starting control module is used for controlling the starting of the electronic equipment through the memory control parameters respectively corresponding to the at least two processing units.

Optionally, the apparatus further comprises:

a preparation processing module, configured to perform at least one of the following processing by the target processing core: initializing sub-equipment of the electronic equipment, constructing a loading environment of a kernel program, and loading the kernel program, wherein the target processing core is a processing core for performing memory training on the target processing unit.

Optionally, the apparatus further comprises:

the memory control parameter storage module is used for storing the memory control parameters corresponding to the at least two processing units respectively into the storage areas corresponding to the target processing units;

the start control module includes:

the memory control parameter acquisition sub-module is used for acquiring memory control parameters corresponding to the at least two processing units respectively from the storage areas corresponding to the target processing units;

and the starting control sub-module is used for starting the file system of the electronic equipment through the loaded kernel program and controlling the use of the memory by the processing units through the memory control parameters respectively corresponding to the at least two processing units in the starting process.

Optionally, the apparatus further comprises:

the end mark writing module is used for writing an end mark in a target storage position corresponding to the processing unit after the memory training of the processing unit is ended, wherein the target storage position is positioned in a storage area of the target processing unit;

The start control submodule includes:

and the file system loading unit is used for starting the file system of the electronic device through the loaded kernel program under the condition that the ending mark is written in the target storage position.

Optionally, the apparatus further comprises:

an initialization program acquisition module for acquiring an initialization program from a storage area corresponding to the target processing unit;

and the initialization module is used for initializing at least two processing cores of the processing unit respectively through the initialization program.

The embodiment of the invention also discloses an electronic device, which comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs comprise instructions for:

receiving a start instruction for an electronic device, wherein the electronic device comprises at least two processing units, and the processing units comprise at least two processing cores;

The embodiment of the application also discloses a readable storage medium, which enables the electronic equipment to execute one or more of the starting processing methods in the embodiment of the application when the instructions in the storage medium are executed by the processor of the electronic equipment.

The embodiment of the application has the following advantages:

in the embodiment of the application, the memory training can be respectively carried out on at least two processing units through at least two processing cores of the processing unit storing the program required by the memory training, and before the memory training process, each processing core can acquire the program required by the memory training from the processing unit where the processing core is positioned, and carry out the memory training on at least two processing units in a parallel mode, and at least two processing cores carry out the memory training on at least two processing units at the same time.

Drawings

FIG. 1 is a flow chart of steps of an embodiment of a boot processing method of the present application;

FIG. 2 is a block diagram of an embodiment of a boot processing apparatus of the present application;

Fig. 3 is a block diagram of an electronic device for initiating a process, according to an example embodiment.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

One of the core concepts of the embodiments of the present invention is that, for an electronic device having a plurality of processing units, memory training is performed on the plurality of processing units by using a plurality of processing cores included in the processing unit, and compared with memory training is performed on the plurality of processing units sequentially, memory training is performed on the plurality of processing units by using the plurality of processing cores, so that parallelization of memory training in time can be achieved. For example, for an electronic device having 4 processing units, if the 4 processing units are sequentially subjected to memory training, and the duration required for the memory training of each processing unit is T, the total duration of the memory training of the 4 processing units is 4*T; in the present invention, if one of the processing units is 4 cores, the processing unit includes 4 processing cores, the 4 processing cores may be used to perform memory training on the 4 processing units respectively, so that the total duration of performing memory training on the 4 processing units is T. It can be seen that the method shortens the memory training time and improves the memory training efficiency.

In addition, the selected processing core can be a processing core of a processing unit storing a program required by memory training, so that the processing core can directly acquire the program required by the memory training from the processing unit where the processing core is located before training, thereby simplifying the process of acquiring the program required by the memory training, shortening the time for acquiring the program required by the memory training, further shortening the time for the memory training and improving the efficiency of the memory training.

Referring to fig. 1, a flowchart illustrating steps of an embodiment of a startup processing method of the present invention is applied to an electronic device including at least two processing units, where the processing units include at least two processing cores, and may specifically include the following steps:

step 101, receiving a start instruction for the electronic device.

The start instruction is an operation instruction of a user to a specified button of the electronic device, for example, a pressing operation of a power key. After the electronic equipment receives the starting instruction, each processing unit of the electronic equipment is powered on, so that the processing unit starts the electronic equipment.

The electronic device of the invention may be any device having a processing unit, wherein the processing unit may be a unit having data processing capabilities, typically a CPU. The processing unit may be multi-core, and in embodiments of the present invention, the multi-core included in the processing unit is referred to as a plurality of processing cores.

Step 102, in response to the start instruction, performing memory training on the at least two processing units through at least two processing cores included in a target processing unit, so as to adjust memory control parameters corresponding to the at least two processing units, where the target processing unit is a processing unit storing a program required by the memory training.

The program required by the memory training is called a memory training program, and the memory training program is used for expressing the implementation logic of the memory training. The memory training is used for continuously adjusting the memory control parameters of the processing unit, and stopping the memory training after the preset condition is reached, wherein the obtained memory control parameters are better memory control parameters obtained by the memory training. The preset condition is that the signal establishment time is greater than or equal to a first preset time length, the signal holding time is greater than or equal to a preset time length, the reference voltage of a configuration data line of the electronic device reaches a preset target voltage, the signal is a representation mode of data, the signal establishment time is a time interval when the data arrives and is stable and continuous before the rising edge of a clock signal arrives, the signal holding time is a time when the data is stable and unchanged after the rising edge of the clock signal of a trigger arrives, and the data is kept unchanged in the holding time so that the data is stably read.

The memory control parameters in the above process include, but are not limited to: charging time, reading delay time and writing delay time, wherein data cannot be read or written in the charging time; the read delay time is used for controlling the maximum delay time of writing, and after the read request is sent, if the data is not read in the read delay time, the read failure is represented; after sending the write request, if the data is not written within the write delay time, the write failure is represented.

The embodiment of the invention can allocate at least two processing cores of the target processing unit to each processing unit, namely, the corresponding relation between the processing cores and the processing units is established.

In a first example, the number of processing cores of the target processing unit is greater than or equal to the number of processing units, so that each processing unit may be assigned a corresponding processing core such that there is a one-to-one correspondence between processing cores and processing units. For example, for 3 processing units CPU1, CPU2 and CPU3, where the target processing unit CPU1 has 3 processing COREs CORE1, CORE2, CORE3, CORE1 may be assigned to CPU1, CORE2 may be assigned to CPU2, and CORE3 may be assigned to CPU3, such that CORE1 memory trains CPU1, CORE2 memory trains CPU2, and CORE3 memory trains CPU 3.

In a second example, the number of processing cores of the target processing unit is smaller than the number of processing units, such that each processing unit cannot be allocated a corresponding processing core, where the same processing core may be allocated to multiple processing units, one processing core corresponding to one or more processing units. In order to shorten the duration of memory training as much as possible, the processing cores may be uniformly allocated to the processing units, so that the number of processing units corresponding to one processing core is close to that of the processing units corresponding to one processing core. For example, for 5 processing units CPU1, CPU2, CPU3, CPU4 and CPU5, where the target processing unit CPU1 has 3 processing COREs CORE1, CORE2, CORE3 and CORE4, CORE1 is assigned to CPU1 and CPU2, CORE2 is assigned to CPU3 and CPU4, and CORE3 is assigned to CPU5, so that CORE1 performs memory training on CPU1, CPU2, CORE2 performs memory training on CPU3 and CPU4, and CORE3 performs memory training on CPU 5.

It should be noted that when one processing CORE performs memory training on at least two processing units, the processing CORE1 needs to perform memory training successively, for example, for the CORE1, the memory training may be performed on the CPU1 first, and then the memory training may be performed on the CPU 2.

It can be seen that the duration of the memory training in the first example can be shortened to the greatest extent, and the shortening degree can be represented by a shortening degree parameter, where the shortening degree parameter has a positive relationship with the number of processing units: the greater the number of processing units, the greater the shortening degree parameter, the greater the degree of shortening; the smaller the number of processing units, the smaller the shortening degree parameter, and the smaller the degree of shortening; the second example has a smaller memory reduction than the first example, and the reduction parameter has a reverse relationship with the number of processing units and a forward relationship with the number of processing cores of the target processing unit: if the number of the processing units is smaller, the number of the processing cores of the target processing unit is larger, and the shortening degree parameter is larger; if the number of processing units is larger, the number of processing cores of the target processing unit is larger, and the shortening degree parameter is smaller.

Thus, in the first example, the number of processing units may be taken as the shortening degree parameter, or a linear/nonlinear transformation of the shortening degree parameter may be taken as the shortening degree parameter, but the forward relation between the shortening degree parameter and the number of processing units in the first example is ensured; in the second example, a ratio between the number of processing cores of the target processing unit and the number of processing units, or a linear/nonlinear transformation of the ratio may be used as the shortening degree parameter, but a forward relationship between the shortening degree parameter and the number of processing cores and a reverse relationship between the numbers of processing units in the second example are ensured.

In addition, since the efficiency of the memory training may be considered as being inversely related to the time length, the improvement degree parameter of the efficiency of the memory training may be determined according to the above relationship, and specifically, the inverse of the shortening degree parameter, or the linear/nonlinear transformation thereof may be used as the improvement degree parameter.

And step 103, controlling the electronic equipment to be started through the memory control parameters respectively corresponding to the at least two processing units.

It will be appreciated that in the process of starting the electronic device, the programs and data required for starting need to be loaded into the memory of the processing unit, so that the use of the memory of the processing unit in the starting process needs to be controlled by the memory control parameters. For example, if there are 3 processing units CPU1, CPU2 and CPU3, the use of the memory by CPU1 may be controlled by the memory control parameter of CPU1, the use of the memory by CPU2 may be controlled by the memory control parameter of CPU2, and the use of the memory by CPU3 may be controlled by the memory control parameter of CPU 3.

In practical applications, the memory controller may be invoked to control the memory.

It should be noted that, the memory training is performed during the starting process, so that the duration of the memory training is shortened, the starting duration of the electronic device can be shortened, and the starting efficiency is further improved.

Optionally, after step 102, before step 103, the method further comprises step 104:

step 104, performing at least one of the following processing by the target processing core: initializing sub-equipment of the electronic equipment, constructing a loading environment of a kernel program, and loading the kernel program, wherein the target processing core is a processing core for performing memory training on the target processing unit.

Among other things, the sub-devices of the electronic device include, but are not limited to: the device comprises a microphone, a USB (Universal Serial Bus) interface, a network card and a sound card, so that the device can be initialized to default values for parameters of the device, for example, the frequency of the microphone is set to default frequency, the transmission rate of the USB interface is set to default transmission rate, the IP (internet protocol) address and port of the network card are set to default address and default port respectively, and the sampling frequency of the sound card is set to default frequency.

The loading environment in which the kernel program is built is used to prepare for loading the kernel program, and the loading environment may include a hardware environment and a software environment required for loading the kernel program.

After the loading environment is ready, a kernel program can be loaded into a storage area of the target processing unit from a disk of the electronic device, wherein the kernel program is a program for starting a file system, the system of the electronic device generally comprises a kernel system and the file system, the kernel system is formed by a plurality of kernel programs, and the starting electronic device is the kernel system for starting the electronic device so as to start the file system through the kernel system. The kernel System is usually a BIOS (Basic Input Output System, basic input/output System), where the kernel System is configured when an electronic device is shipped, and the file System may also be called an Operating System (OS), and may be configured when the electronic device is shipped, or may be installed by a user after the user purchases the electronic device.

In the invention, the target processing core is a processing core for performing memory training on the target processing unit, and the target processing core is a processing core of the target processing unit, so that the problem of performing memory training across nodes is solved, and the target processing core completes memory training on the premise of full memory. Based on the method, when the target processing core completes the memory training, but the other processing cores do not complete the memory training, the target processing core completes the other processing processes such as initializing the sub-equipment, constructing the loading environment, loading the kernel program and the like, so that the duration of the memory training can be further shortened, and the efficiency of the memory training can be improved. For example, for 3 processing units CPU1, CPU2 and CPU3, where the target processing unit CPU1 has 3 processing COREs CORE1, CORE2, CORE3, CORE1 memory trains CPU1, CORE2 memory trains CPU2, CORE3 memory trains CPU3, and CORE1 is the processing CORE memory trains target processing unit CPU1, so CORE1 is the target processing CORE to perform the rest of the above processing procedures.

It can be understood that the invention adopts the target processing core which finishes the memory training first to carry out the rest processing processes after the memory training, and if the processing core which does not finish the memory training first is adopted to carry out the rest processing processes, the memory training of the processing core needs to be waited, thereby increasing the waiting time and leading the memory training time to be longer.

Optionally, after step 102, the method further comprises step 105:

and 105, storing the memory control parameters corresponding to the at least two processing units into the storage areas corresponding to the target processing units.

In practical applications, the memory control parameters are important parameters of the training result parameters, but there are some other training result parameters, including but not limited to: the duration required for the memory training of each processing core, the sign of the success or failure of the training, and the reason for the failure. Based on the above, the training result parameters may be stored in a storage area of the target processing unit, where the storage area may be a storage space specified in a flash (flash memory), so that the training result parameters are not easy to be lost, and the flash may be communicatively connected to the target processing unit through an SPI (Serial Peripheral Interface ).

Of course, the storage area may also select the rest of the storage devices, which is not limited by the present invention.

Based on step 105, said step 103 comprises substeps 1031 to 1032:

sub-step 1031, obtaining memory control parameters corresponding to the at least two processing units respectively from the storage areas corresponding to the target processing units.

Specifically, a storage area may be allocated for each processing unit to store the memory control parameters of the processing unit, so as to obtain the memory control parameters from the corresponding storage area according to the processing unit. It will be appreciated that for each processing unit, a plurality of memory control parameters may be stored in key-value pairs, with the identification of the memory control parameters as keys and the value of the memory control parameters as values.

Sub-step 1032, starting the file system of the electronic device through the loaded kernel program, and controlling the use of the memory by the processing units through the memory control parameters respectively corresponding to the at least two processing units in the starting process.

As described in the foregoing description of the kernel program in step 104, the loading of the kernel program is completed in step 104 through the target processing core, so that the kernel program can be started, and then the file system is started, and the file system is started.

Optionally, after step 102, the method further comprises step 106:

and step 106, after the memory training of the processing unit is finished, writing an ending mark in a target storage position corresponding to the processing unit, wherein the target storage position is positioned in a storage area of the target processing unit.

In the present invention, a storage area may be set for each processing unit in the storage area of the target processing unit to store the end flag of the processing unit. To reduce the waste of memory area, the end flag may be set to 1 bit, and the end flags of the plurality of processing units may be concatenated into one byte, for example, the end flag may be represented by a value of "1"; in addition, a default value may be written to the target storage location in the initial state, representing not ending. For example, if there are processing units CPU1, CPU2, CPU3, then in the initial state, the concatenated bytes may be: 00000000, after the CPU1 finishes the memory training, the concatenated bytes may be: 10000000, after the CPU2 finishes the memory training, the concatenated bytes may be: 11000000, after the CPU3 finishes the memory training, the concatenated bytes may be: 11100000.

Based on the step 106, the starting of the file system of the electronic device by the loaded kernel program in the sub-step 1032 includes the sub-step 10321:

sub-step 10321, in the case where the end flag is written in the target storage location, starts a file system of the electronic device by the loaded kernel program.

Specifically, under the condition that the target storage positions of the processing units are all end marks, starting a file system of the electronic equipment through a loaded kernel program; in the case where the end flag is not written in the target storage location of at least one of the processing units, the file system of the electronic device is not started by the loaded kernel program.

In the invention, when the ending mark of the processing unit is spliced into one byte, whether all the target storage positions of the processing units are ending marks can be determined through the value of the byte; for example, if the byte is 11100000=224, it is determined that the target storage location of each processing unit is an end flag.

According to the invention, whether the memory training is finished or not can be accurately represented by the ending mark, in addition, the ending mark is stored in the storage area corresponding to the target processing unit, so that the cross-node acquisition of the ending mark is avoided, the speed of writing in the ending mark and reading the ending mark is improved, the duration of the memory training is further shortened, and the efficiency of the memory training is improved.

Optionally, before the step 102, step 107 is further included:

step 107, acquiring an initialization program from a storage area corresponding to the target processing unit.

The initialization program is a program in the BIOS, and is used for initializing the processing unit, and can be different for different processing units and applied to scenes of different processing tasks of different processing units; the initialization program can be the same for different processing units, and can be applied to a scene that different processing units adopt the same processing tasks, and the processing logic of different processing units is the same.

Step 108, initializing at least two processing cores of the processing unit respectively through the initializing program.

Wherein initializing the processing cores for allocating resources of the processing unit to the processing cores may include, but is not limited to: allocating memory of the processing unit to the processing core, closing interrupts, configuring exception vectors, initializing caches, initializing TLBs (translation lookaside buffer, address translation lookaside buffers, which may be referred to simply as a fast table), cleaning mailboxes.

After initializing the processing cores, the processing cores of the processor other than the target processor enter an idle mode so as not to perform any operation, while the processing cores of the target processor do not enter the idle mode, and step 102 is entered for memory training.

In summary, in the embodiment of the present application, the memory training may be performed on at least two processing units through at least two processing cores of the processing unit storing the program required for the memory training, before the memory training process, each processing core may acquire the program required for the memory training from the processing unit where the processing core is located, perform the memory training on at least two processing units in a parallel manner, and at least two processing cores perform the memory training on at least two processing units simultaneously.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the application.

Referring to fig. 2, which shows a block diagram of an embodiment of a start-up processing apparatus of the present invention, applied to an electronic device comprising at least two processing units, said processing units comprising at least two processing cores, the apparatus 200 may specifically comprise the following modules:

a start instruction receiving module 201, configured to receive a start instruction for the electronic device.

The memory training module 202 is configured to perform memory training on the at least two processing units through at least two processing cores included in a target processing unit in response to the start instruction, so as to adjust memory control parameters corresponding to the at least two processing units, where the target processing unit is a processing unit storing a program required for the memory training.

And the starting control module 203 is configured to control the electronic device to start through the memory control parameters respectively corresponding to the at least two processing units.

Optionally, the apparatus further comprises a preparation processing module:

Optionally, the apparatus further includes a memory control parameter storage module:

and the memory control parameter storage module is used for storing the memory control parameters corresponding to the at least two processing units respectively into the storage areas corresponding to the target processing units.

Based on the memory control parameter storage module, the starting control module comprises a memory control parameter acquisition sub-module and a starting control sub-module:

and the memory control parameter acquisition sub-module is used for acquiring the memory control parameters respectively corresponding to the at least two processing units from the storage areas corresponding to the target processing units.

Optionally, the apparatus further comprises an end flag writing module:

Based on the end mark writing module, the start control sub-module comprises a file system loading unit:

Optionally, the apparatus further includes an initialization program acquisition module and an initialization module:

and the initialization program acquisition module is used for acquiring the initialization program from the storage area corresponding to the target processing unit.

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.

Fig. 3 is a block diagram of an electronic device 300 for enabling a process according to an exemplary embodiment. For example, electronic device 300 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to fig. 3, an electronic device 300 may include one or more of the following components: a processing component 302, a memory 304, a power supply component 306, a multimedia component 308, an audio component 310, an input/output (I/O) interface 312, a sensor component 314, and a communication component 316.

The processing component 302 generally controls overall operation of the electronic device 300, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing element 302 may include one or more processors 320 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 302 can include one or more modules that facilitate interactions between the processing component 302 and other components. For example, the processing component 302 may include a multimedia module to facilitate interaction between the multimedia component 308 and the processing component 302.

Memory 304 is configured to store various types of data to support operations at device 300. Examples of such data include instructions for any application or method operating on the electronic device 300, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 304 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 306 provides power to the various components of the electronic device 300. The power supply components 306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 300.

The multimedia component 308 includes a screen between the electronic device 300 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 308 includes a front-facing camera and/or a rear-facing camera. When the electronic device 300 is in an operational mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 310 is configured to output and/or input audio signals. For example, the audio component 310 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 300 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 304 or transmitted via the communication component 316. In some embodiments, audio component 310 further comprises a speaker for outputting audio signals.

The I/O interface 312 provides an interface between the processing component 302 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 314 includes one or more sensors for providing status assessment of various aspects of the electronic device 300. For example, the sensor assembly 314 may detect an on/off state of the device 300, a relative positioning of components, such as a display and keypad of the electronic device 300, a change in position of the electronic device 300 or a component of the electronic device 300, the presence or absence of a user's contact with the electronic device 300, an orientation or acceleration/deceleration of the electronic device 300, and a change in temperature of the electronic device 300. The sensor assembly 314 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 314 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 314 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 316 is configured to facilitate communication between the electronic device 300 and other devices, either wired or wireless. The electronic device 300 may access a wireless network based on a communication standard, such as WiFi,2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 316 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 316 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 300 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 304, including instructions executable by processor 320 of electronic device 300 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

A non-transitory computer readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform a boot processing method, the method comprising:

Optionally, the method further comprises:

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The above details of a start-up processing method, apparatus, electronic device and storage medium provided by the present invention, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. A method of enabling processing for a processor of an electronic device comprising at least two processing units, said processing units comprising at least two processing cores, comprising:

the processor receives a start instruction for the electronic device;

the processor responds to the starting instruction, and respectively performs memory training on the at least two processing units through at least two processing cores included in a target processing unit so as to adjust memory control parameters respectively corresponding to the at least two processing units, wherein the target processing unit is a processing unit storing a program required by the memory training; the at least two processing units include a target processing unit;

the processor controls the electronic equipment to start through the memory control parameters respectively corresponding to the at least two processing units;

when the number of the processing cores of the target processing unit is smaller than that of the processing units, the same processing core is distributed to a plurality of processing units, and one processing core corresponds to one or more processing units; and uniformly distributing the processing cores to the processing units, so that the number of the processing units corresponding to one processing core is close.

2. The method according to claim 1, wherein the method further comprises:

3. The method according to claim 2, wherein the method further comprises:

4. A method according to claim 3, characterized in that the method further comprises:

5. The method of any one of claims 1 to 4, further comprising, prior to the memory training of the at least two processing units by the at least two processing cores included in the target processing unit, respectively:

6. A boot processing apparatus for use in a processor of an electronic device comprising at least two processing units, the processing units comprising at least two processing cores, comprising:

the processor starting instruction receiving module is used for receiving a starting instruction aiming at the electronic equipment;

The processor memory training module is configured to perform memory training on at least two processing units through at least two processing cores included in a target processing unit in response to the start instruction, so as to adjust memory control parameters corresponding to the at least two processing units, where the target processing unit is a processing unit storing a program required by the memory training; the at least two processing units include a target processing unit;

the processor starting control module is used for controlling the starting of the electronic equipment through the memory control parameters respectively corresponding to the at least two processing units;

7. The apparatus of claim 6, wherein the apparatus further comprises:

8. The apparatus of claim 7, wherein the apparatus further comprises:

the start control module includes:

9. The apparatus of claim 8, wherein the apparatus further comprises:

the start control submodule includes:

10. The apparatus according to any one of claims 6 to 9, further comprising:

11. An electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, the one or more programs comprising instructions for:

12. A readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the boot processing method according to any one of the method claims 1 to 5.