CN117891236A - Test system - Google Patents
Test system Download PDFInfo
- Publication number
- CN117891236A CN117891236A CN202410081374.4A CN202410081374A CN117891236A CN 117891236 A CN117891236 A CN 117891236A CN 202410081374 A CN202410081374 A CN 202410081374A CN 117891236 A CN117891236 A CN 117891236A
- Authority
- CN
- China
- Prior art keywords
- data
- target
- unit
- target data
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 171
- 230000015654 memory Effects 0.000 claims abstract description 291
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000012545 processing Methods 0.000 claims description 149
- 238000012546 transfer Methods 0.000 claims description 58
- 230000005540 biological transmission Effects 0.000 description 53
- 238000010586 diagram Methods 0.000 description 16
- 239000011159 matrix material Substances 0.000 description 10
- 230000006870 function Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 5
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 3
- 238000013507 mapping Methods 0.000 description 3
- LMDZBCPBFSXMTL-UHFFFAOYSA-N 1-ethyl-3-(3-dimethylaminopropyl)carbodiimide Chemical compound CCN=C=NCCCN(C)C LMDZBCPBFSXMTL-UHFFFAOYSA-N 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Abstract
The embodiment of the invention provides a test system, and relates to the technical field of testing. The test system comprises at least one I/O unit, a plurality of devices and a shared operation unit; the method comprises the steps that a first device obtains an operation instruction for performing target operation on a shared memory; the target operation is used for writing target data into the shared memory; the target data is data which needs to be transmitted between a first device and at least one second device in a plurality of devices in the process of testing the tested piece, and the second device is configured with a target memory; the sharing operation unit sends the operation instruction or the target data corresponding to the operation instruction to at least one designated device configured with a target memory; the at least one specifying means includes a second means; the second device reads at least part of the target data required for the test from the target memory. In the invention, the device provided with the target memory in the test system can directly read at least part of data required by the test from the local memory, thereby effectively improving the data reading efficiency.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a testing system.
Background
In vehicles such as automobiles and new energy vehicles, the electronic and electric architecture of the whole vehicle is more and more complex, and the number, the data bandwidth and the processing capacities of a CPU and a GPU of the electronic control unit (Electronic Control Unit, ECU) are changed by an order of magnitude compared with the prior art.
Hardware-in-the-Loop (HIL) testing can verify the functions of various controllers such as a domain control, an ECU, a CPU and the like in a vehicle in advance so as to shorten the development period of the controllers.
In the existing HIL test system, the device (such as a Real-time machine or an industrial personal computer (RTPC)) with data storage and processing capacity in the HIL test system and an I/O card are used for executing test tasks to complete the test of the tested piece; in general, in the HIL system, no matter what devices are integrated, data sharing is usually required between the devices, in the prior art, data sharing is usually realized between the I/O card and the RTPC through ethernet, which is inefficient and affects test efficiency.
Disclosure of Invention
The invention aims to provide a test system, wherein a device provided with a target memory in the test system can directly read at least part of data required by the test from a local memory, so that the data reading efficiency is effectively improved; in particular, for data that needs to be repeatedly read by multiple devices (which may include a real-time computing device and/or an I/O processing device), the multiple devices can directly read the data from the local memory, without reading the data from the shared memory through the shared operation unit, so that the processing burden of the shared operation unit is effectively reduced, and the processing efficiency of the shared operation unit is improved.
To achieve the above object, the present invention provides a test system comprising: at least one I/O unit, a plurality of devices and a shared operating unit; the plurality of devices comprise at least one real-time computing device and at least one I/O processing device, wherein the I/O processing device is connected to at least one I/O unit, and the I/O unit is directly or indirectly connected to a tested piece; a first device of the plurality of devices is used for acquiring an operation instruction for performing target operation on a shared memory and sending the operation instruction to the shared operation unit; the target operation is used for writing target data into the shared memory; the target data is data which needs to be transferred between the first device and a second device in the plurality of devices in the process of testing the tested piece, and a target memory is configured in the second device; the sharing operation unit is configured to cause the target data to be stored in a target memory of at least one designated device among the plurality of devices, the at least one designated device including the second device; the second device is used for reading at least part of the target data required for testing from a target memory of the second device.
In one embodiment, the second apparatus comprises: designating a module and a target memory;
The designating module is used for receiving the operation instruction or the target data from the sharing operation unit, sending the target data to a target memory of the second device, and reading at least part of the target data required by the test from the target memory.
In one embodiment, the specifying module includes: a data transfer unit and a processing unit;
The data transfer unit is used for receiving the operation instruction or the target data from the sharing operation unit and sending the target data to a target memory of the second device;
The processing unit is used for reading at least part of the target data required for testing from a target memory of the second device.
In one embodiment, the specifying device is configured to prohibit a write operation to a target memory of the specifying device, or: is configured to prohibit execution of a write operation to a target address space of a target memory of the specified device, the target address space including a storage address for storing the target data.
In one embodiment, the at least one specifying means further comprises the first means;
The first device is further configured to: the target data is read from a target memory of the first device.
In one embodiment, the sharing operation unit is specifically configured to, when the target data is stored in a target memory of at least one designated device of the plurality of devices: the target data is written into the target memory of the specified device.
In one embodiment, the sharing operation unit is configured to cause, when target data corresponding to the operation instruction meets a preset condition, the target data to be stored in a target memory of at least one designated device among the plurality of devices.
In one embodiment, the preset conditions include any one or any combination of the following:
the target data is derived from a first designated device of the at least one real-time computing device or a first designated port of the real-time computing device;
the target data is to be sent to a second designated device of the at least one real-time computing device or a second designated port of the real-time computing device;
The target data is data that needs to be transferred between the real-time computing devices;
the target data is derived from a first designated I/O unit of the at least one I/O unit or a third designated port of the I/O unit;
The target data is required to be sent to a second designated I/O unit of the at least one I/O unit or a fourth designated port of the I/O unit;
the target data is for being written to a specified address;
the target data are data containing preset identifiers;
the target data are located in a first preset data list;
the target data are located outside a second preset data list;
The acquisition frequency of the target data is smaller than a preset frequency threshold;
The target data is to be transmitted to a plurality of second devices.
In an embodiment, the shared operating unit is further configured to:
And refusing to transmit the target data or the operation instruction to a preset port so that the target data cannot be written into a target memory of a preset device in the plurality of devices through the preset port.
In one embodiment, the test system includes N devices, N being greater than 1;
the plurality of devices are ones of the N devices for performing a current test task.
In one embodiment, the at least one specifying means satisfies at least one of:
the at least one designated device is all of the plurality of devices;
the at least one designated device is the real-time computing device;
The first device is the real-time computing device, the at least one designated device includes all I/O processing devices of the plurality of devices;
the first device is the I/O processing device, the at least one designated device includes all real-time computing devices of the plurality of devices;
The at least one designated device includes the device of the plurality of devices corresponding to the target data.
In one embodiment, the second means is for:
determining whether to read the specified data from a target memory of the second device when the specified data required for the test needs to be read;
if yes, reading the specified data from the target memory;
if not, the specified data is read from the shared memory through the shared operation unit.
In one embodiment, the second means is for:
Determining to read the specified data from a target memory of the second device when the specified data is within a preset data range; and/or the number of the groups of groups,
When the current time is within the specified time range of the specified data, it is determined to read the specified data from the target memory of the second device.
In one embodiment, the second means is for:
If the specified data is the target data, it is determined to read the specified data from a target memory of the second device.
In one embodiment, the shared operation unit is configured to execute the operation instruction and write the target data into the shared memory;
At least one third device of the plurality of devices is configured to: at least part of the target data required for the test is read from the shared memory by the shared operation unit.
In one embodiment, the test system is a HIL system.
Drawings
FIG. 1 is a schematic diagram of a test system in a first embodiment according to the invention;
FIG. 2 is a schematic diagram of a test system in accordance with a first embodiment of the present invention, wherein a plurality of devices 2 includes at least one real-time computing device 21 and at least one I/O processing device 22;
FIG. 3 is a schematic diagram of a process of sharing target data W among a plurality of devices in a test system according to a first embodiment of the present invention;
FIG. 4 is a schematic view of a second apparatus according to a second embodiment of the present invention;
Fig. 5 is a schematic diagram of the second apparatus in fig. 4, wherein the processing module 211 includes: a data transfer unit 2111 and a processing unit 2112;
FIG. 6 is a schematic diagram of a real-time computing device 21 sharing target data X to an I/O processing device 22 in a test system according to a second embodiment of the invention;
FIG. 7 is a schematic diagram of the I/O processing device 22 in the test system sharing target data Y to the real-time computing device 21 according to the second embodiment of the present invention;
FIG. 8 is a schematic diagram of a first real-time computing device sharing target data Z to a second real-time computing device in a test system according to a second embodiment of the present invention;
FIG. 9 is a schematic diagram showing the I/O processing device 22 without the target memory configured in the test system sharing the target data K to the real-time computing device 21 according to the second embodiment of the present invention;
Fig. 10 is a schematic diagram of a real-time computing device 21 in a test system according to a second embodiment of the present invention sharing target data A1 to an I/O processing device 22 through a sharing operation unit, wherein the I/O processing device 22 includes: a data transfer unit and a processing unit;
fig. 11 is a schematic diagram of an I/O processing device 22 sharing target data A2 to a real-time computing device 21 through a sharing operation unit in a test system according to a second embodiment of the present invention, wherein the I/O processing device 22 includes: a data transfer unit and a processing unit;
FIG. 12 is a schematic diagram of a real-time computing device 21 sharing data to an I/O processing device 22 through a shared operating unit in a test system according to a second embodiment of the invention, wherein the I/O processing device 22 includes FPGA circuitry;
FIG. 13 is a schematic diagram of an I/O processing device 22 sharing data to a real-time computing device 21 through a shared operating unit in a test system according to a second embodiment of the present invention, wherein the I/O processing device 22 includes FPGA circuitry;
FIG. 14 is a schematic diagram of a third real-time computing device sharing data to a fourth real-time computing device through a sharing operation unit in a test system according to a second embodiment of the present invention;
FIG. 15 is a schematic diagram of a test system in accordance with an embodiment of the present invention as an HIL system;
FIG. 16 is a schematic diagram of a HIL system with a plurality of control modules, each control module being connected to a corresponding I/O unit in a cascade manner, according to an embodiment of the present invention;
FIG. 17 is a schematic diagram of a HIL system with multiple control modules, each of which is directly connected to a corresponding I/O unit, according to an embodiment of the present invention.
Detailed Description
The following detailed description of various embodiments of the present invention will be provided in connection with the accompanying drawings to provide a clearer understanding of the objects, features and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the invention, but rather are merely illustrative of the true spirit of the invention.
In the following description, for the purposes of explanation of various disclosed embodiments, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. One skilled in the relevant art will recognize, however, that an embodiment may be practiced without one or more of the specific details. In other instances, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.
Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and variations such as "comprises" and "comprising" will be understood to be open-ended, meaning of inclusion, i.e. to be interpreted to mean "including, but not limited to.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or/and" unless the context clearly dictates otherwise.
In the following description, for the purposes of clarity of presentation of the structure and manner of operation of the present invention, the description will be made with the aid of directional terms, but such terms as "forward," "rearward," "left," "right," "outward," "inner," "outward," "inward," "upper," "lower," etc. are to be construed as convenience, and are not to be limiting.
In an existing test system, all devices are connected to a shared memory unit in a star-shaped manner, data to be shared are synchronized to the shared memory of the shared memory unit, each device can read required target data from the shared memory, and data sharing is realized through read-write operation of the shared memory. However, each device needs to read data from the shared memory when reading the data, and the data reading efficiency is low; in addition, for the same data which needs to be repeatedly read by different devices, the process of reading for multiple times can increase the burden of the shared memory unit, affect the efficiency of the shared memory unit, and also affect the overall test efficiency.
An embodiment of the present invention relates to a test system, please refer to fig. 1 and 2, comprising: sharing an operation unit 1, a plurality of devices 2, and at least one I/O unit 3; each device 2 is directly or indirectly connected to the shared operating unit 1, and in fig. 1, each device 2 is directly connected to the shared operating unit 1 as an example. Further, the test system further comprises: the shared memory 4, the shared operating unit 1 is connected to the shared memory 4, and the shared memory 4 may be a single DDR memory or a memory pool including a plurality of DDR memories, part or all of the DDR memories may be disposed in one cabinet, or the DDR memories may be distributed across different cabinets, for example.
The plurality of devices 2 includes at least one real-time computing device 21 and at least one I/O processing device 22 (the plurality of real-time computing devices 21 and the plurality of I/O processing devices 22 are shown in FIG. 2 by way of example only); the I/O processing device 22 is connected to at least one I/O unit 3, the I/O unit 3 being connected directly or indirectly to a test piece (the test piece is not shown in the figure). One I/O processing device 22 may exchange data with one or more I/O units 3, for example, each I/O unit 3 is connected to a different terminal of the I/O processing device 22, and for example, each I/O unit 3 is cascade-connected to the I/O processing device 22 (in this embodiment and the following embodiments, each I/O unit 3 is cascade-connected, for example), and communicates through EtherCAT ethernet or the like. Regardless of the connection, interaction between the I/O processing device 22 and the I/O unit 3 may ultimately be accomplished, either directly between the I/O processing device 22 and the I/O unit 3 or through other circuitry. The I/O unit 3 is used for connecting the tested pieces, and the whole test system can be connected with one or a plurality of tested pieces at the same time.
The device 2 in the test system may be a circuit, a circuit board including the circuit, or a configuration including the circuit board and a housing (or a rack) for loading the circuit board.
A first device of the plurality of devices 2 is configured to acquire an operation instruction for performing a target operation on the shared memory 4, and send the operation instruction to the shared operation unit 1; the target operation is for writing target data to the shared memory 4; the target data is that a target memory is configured in the second device in the process of testing the tested piece.
The first device is any one device 2 of the plurality of devices 2, which may be a real-time computing device 21 or an I/O processing device 22; when the first device needs to transfer target data to the second device, an operation instruction for writing the target data into the shared memory 4 is generated, and the operation instruction is sent to the shared operation unit 1, wherein the target data is the data which needs to be transferred between the first device and at least one second device in the plurality of devices 2 in the test process.
The second device may also be the real-time computing device 21 or the I/O processing device 22, and the number of the second devices may be one or more, and if the number of the second devices is plural, the real-time computing device 21 and/or the I/O processing device 22 may be included therein; that is, the target data may be data that needs to be transferred between the plurality of real-time computing devices 21, or data that is transferred between the real-time computing devices 21 and the I/O processing devices 22, or data that is transferred between the plurality of I/O processing devices 22.
The shared operating unit 1, upon receiving the operation instruction, causes the target data to be stored in the target memory of at least one designated device among the plurality of devices, the at least one designated device including the second device. Specifically, the shared operating unit 1 sends the operation instruction or the target data corresponding to the operation instruction to at least one specifying device, where the specifying device includes the second device, and the specifying devices are each configured with a target memory. That is, the shared operating unit 1 may send some operation instructions or target data corresponding to the operation instructions to the designated device, where the designated device includes the second device that needs to receive the target data.
That is, the shared operating unit 1 may write the target data directly into the target memory of each of the specifying devices, or may transfer the operation instruction to each of the specifying devices, and the operation instruction is executed by each of the specifying devices to store the target data into the configured target memory. The second device to receive the target data is included in the designated device, and the target data is stored in the target memory of the second device. In the testing process, if part or all of the target data is needed, the second device can directly read at least part of the needed target data from the target memory of the second device. For example, the second device may read all data required for the test from the local target memory, but not limited thereto, and may read part of the data required for the test from the local target memory, and the other part of the data required for the test is read from the shared memory 4 through the shared operating unit 1.
In addition, the shared operating unit 1 also receives an execution operation instruction to write the target data into the shared memory 4; that is, the target data required for the test is also stored in the shared memory 4.
Thereby, at least one third device of the plurality of devices 2 is arranged to: at least part of the target data required for the test is read from the shared memory 4 by the shared operating unit 1. The third device is any one device 2 among the plurality of devices 2, and may be the device 1 provided with the target memory, or may be the device 1 not provided with the target memory, and may read from the shared memory 4 through the shared operation unit 1 when the target data needs to be read during the test.
In the present embodiment, the target memory may be configured in some or all of the devices 2 included in the test system; for example, some fixed data needs to be read frequently by some devices, a target memory may be configured in the some devices, and these fixed data are stored in the target memories of the devices respectively. The target memory may be understood as a local memory of the device, and the local memory may be a memory provided in the device or a memory externally connected to the device, so long as writing and reading of data are realized locally, the local memory may be understood as a local memory. In the above process, the target memory is required to be included in the specifying device that receives the target data, so as to store the target data in the target memory of the specifying device.
The sharing operation unit 1 is configured to cause target data corresponding to an operation instruction to be stored in a target memory of at least one designated device among the plurality of devices 1 when the target data satisfies a preset condition. That is, in the test process, whether the shared operating unit 1 transmits the received operation instruction (or the target data corresponding to the operation instruction) to the specification device or not depends on whether the target data corresponding to the operation instruction satisfies a preset condition defining whether the target data needs to be transmitted to the specification device or not.
In one example, when the first device obtains the target data to be shared to the second device, it may first determine whether the target data meets a preset condition, and send the indication information indicating whether the target data meets the preset condition to the sharing operation unit 1 together with an operation instruction for writing the target data into the shared memory, where the sharing operation unit 1 may determine whether the target data meets the preset condition based on the indication information, and determine that the target data needs to be sent to the specified device when receiving the first indication information indicating that the target data meets the preset condition; and when receiving the indication information indicating that the target data does not meet the preset condition, determining that the target data does not need to be sent to the designated device.
In another example, the sharing operation unit 1 autonomously determines whether the target data satisfies a preset condition when receiving the operation instruction, and determines that the target data needs to be transmitted to the specifying device when determining that the target data satisfies the preset condition; when the target data is judged not to meet the preset condition, the target data is determined not to be required to be sent to the appointed device. For example, when each operation instruction is received, the shared operation unit 1 first determines that the operation instruction is a write operation instruction, and if so, determines whether the operation instruction satisfies a preset condition.
In the two modes, the preset condition comprises any one or any combination of the following:
The target data is derived from a first designated device of the at least one real-time computing device or a first designated port of the real-time computing device; for example, after acquiring the target data, the real-time computing device judges whether the target data is the first designated device or not, if yes, the target data is determined to meet the preset condition; if not, determining that the target data does not meet the preset condition. Or after receiving the operation instruction, the sharing operation unit 1 judges whether the port in the operation instruction sent by the real-time computing device is a first designated port, if so, the target data is determined to meet the preset condition; if not, determining that the target data does not meet the preset condition.
The target data is required to be sent to a second designated device of the at least one real-time computing device or a second designated port of the real-time computing device; whether the object to be shared of the target data is a second designated device or a second designated port of the real-time computing device or not, if yes, determining that the target data meets a preset condition; if not, determining that the target data does not meet the preset condition.
The target data is data which needs to be transferred between the real-time computing devices; namely, the sharing operation unit 1 receives an operation instruction for writing target data into the shared memory from one real-time computing device, and the shared object of the target data corresponding to the operation instruction is another real-time computing device, and determines that the target data meets a preset condition; if not, determining that the target data does not meet the preset condition.
The target data is derived from a first designated I/O unit of the at least one I/O unit or a third designated port of the I/O unit; that is, the target data is sent out by the first appointed I/O unit or the third appointed port of any I/O unit, and the target data is determined to meet the preset condition; if not, determining that the target data does not meet the preset condition.
The target data is required to be sent to a second designated I/O unit or a fourth designated port of the I/O unit in the at least one I/O unit; whether the object to be shared of the target data is a second designated I/O unit or a fourth designated port of any I/O unit or not, if yes, determining that the target data meets a preset condition; if not, determining that the target data does not meet the preset condition.
The target data is for being written to a specified address; for example, the first device may determine whether the target address is a specified address if the target address is the pointed target address included in the operation instruction for writing the target data into the shared memory, and if yes, determine that the target data meets the preset condition; if not, determining that the target data does not meet the preset condition.
For example, a storage address for target data to be written to the shared memory is divided into any one of a plurality of address segments to specify the address segment. Specifically, the storage address in the shared memory is divided into a plurality of storage address segments, each storage address segment is configured with a corresponding attribute for defining whether the data pointing to the storage address segment can be stored to the target memory of the specified device; the designated address field is the target memory to which the data pointing to the designated address field can be stored; for example, the target address of the pointed shared memory, which is included in the operation instruction for writing the target data into the shared memory and generated by the first device, may be determined whether the target address is located in any designated address segment, and if yes, it is determined that the target data meets the preset condition; if not, determining that the target data does not meet the preset condition.
Further, the storage address in the shared memory may be divided into a plurality of storage address segments corresponding to all devices in the test system one by one, and a binding relationship between the storage address segments is established, so that a function of performing local storage of target data to one or more devices in a targeted manner may be realized through configuration of the storage address segments, for example, an attribute of the storage address segment C bound to the I/O processing device C is configured to be that data pointing to the storage address segment C may be stored in a target memory of the I/O processing device C, so that after an operation instruction that needs to write target data into the shared memory is sent to the shared operation unit by a certain real-time computing device, the shared operation unit determines that the target address is located in the storage address segment C, and sends the operation instruction or the target data in the operation instruction to the I/O processing device C for local storage (i.e. to the target memory in the I/O processing device C).
The target data are data containing preset identifiers; the preset identifier is used for representing information such as the type, the purpose, the format, the source, the destination and the like of the data, namely when the representation of the target data is the preset identifier, the target data is determined to meet the preset condition; otherwise, determining that the target data does not meet the preset condition.
The target data are located in a first preset data list; a first preset data list is preset in the device or the sharing operation unit, and the target data in the first preset data list meets preset conditions similar to the data white list; and the target data outside the first preset data list does not meet the preset condition.
The target data are located outside a second preset data list; a second preset data list is preset in the device or the sharing operation unit, and the target data of the second preset data list does not meet preset conditions similar to the data blacklist; and the target data outside the second preset data list meets the preset condition.
The acquisition frequency of the target data is smaller than a preset frequency threshold; and determining that the target data with the acquired frequency smaller than the preset frequency threshold value meets the preset condition, and determining that the target data with the acquired frequency reaching the preset frequency threshold value does not meet the preset condition. The acquisition frequency may refer to the frequency of generating the target data by the real-time computing device, or the frequency of receiving the target data by the shared operation unit, or the frequency of reporting the data by the I/O unit acquired by the I/O processing device; however, the present invention is not limited thereto, and it is also possible to determine that all of the target data having the acquisition frequency greater than the set threshold value do not satisfy the preset condition, and to determine that all of the target data having the acquisition frequency less than the set threshold value satisfy the preset condition.
For example, in the testing process, the real-time computing device a needs to periodically share the target data with the tested object connected to the I/O processing device B through the I/O unit, for example, after the real-time computing device a emulates the vehicle speed data of the vehicle speed sensor, the real-time computing device a needs to periodically send the vehicle speed data to the tested object (e.g. ECU), and if the generating frequency of the vehicle speed data is high (i.e. the sending period is short), the following situations are likely to occur: after the operation command R p( n (or the vehicle speed data p (n)) generated by the real-time computing device a and used for writing the vehicle speed data p (n) into the shared memory is sent to the I/O processing device B by the shared operation unit 1 and is written into the local target memory by the I/O processing device B, the real-time computing device a generates new vehicle speed data p (n+1) again, and sends the operation command R p(n+1) for writing the vehicle speed data p (n+1) into the shared memory to the shared operation unit 1 and writes the shared memory, the shared operation unit 1 sends the operation command R p(n+1) (or the vehicle speed data p (n+1)) to the I/O processing device B again and is written into the local target memory by the I/O processing device B, during which, if the I/O processing device B needs to share the vehicle speed data to the ECU to be tested, if the I/O processing device B reads the shared vehicle speed data p (n+1) from the shared memory, the vehicle speed data p (n) is read from the shared memory, and the ECU can send the vehicle speed data p (n) to the ECU) which can not be tested, and the vehicle speed data p (n+1) can not be accurately sent to the ECU (n+ecu) can not be tested, and the vehicle speed data can not be accurately sent to the ECU (n+1) can be tested). Therefore, the preset condition can be configured to be that the acquisition frequency of the target data is smaller than the preset frequency threshold, so that the I/O processing device B only reads the data with the frequency lower than the preset frequency threshold from the local memory, and the possibility of the occurrence of the situation can be avoided or reduced. For similar reasons, the device under test may also need to periodically report data to a simulation model running in the real-time computing device via the I/O unit, and also may use a limited acquisition frequency to determine whether certain target data is read locally.
When the target data is required to be sent to a plurality of second devices, namely the shared objects of the target data are a plurality of, determining that the target data meet the preset condition; otherwise, determining that the target data does not meet the preset condition.
For example, during testing, especially in the context of joint testing of multiple real-time computing devices, the following may occur: the data provided by one real-time computing device may be shared to both the other real-time computing device and to the portion of the I/O unit to which the I/O processing device is connected; the data of one I/O unit is required to be shared to a plurality of different real-time computing devices; the data given by one real-time computing device may be respectively given to other real-time computing devices, even to the I/O processing device, for example, one real-time computing device needs to synchronize clocks to the other real-time computing device and the I/O processing device, and further needs to send corresponding time service information to the real-time computing device and the I/O processing device; in the above case, one target data is to be shared to a plurality of other devices, that is, a write-once multi-port read target data may occur, so that the preset condition may be configured that the target data needs to be sent to a plurality of second devices, and at this time, the shared operation unit may send an operation instruction (or the target data corresponding to the operation instruction) to at least the plurality of second devices, where the plurality of second devices may read the target data from the local memory, so as to avoid the process that the plurality of second devices read the target data from the shared memory many times, and further avoid the problems such as reduced efficiency and increased burden of the shared operation unit caused by the foregoing.
It should be noted that the above-mentioned various preset conditions may be used in combination with each other without collision.
In one embodiment, the shared operating unit 1 is further configured to: the method comprises the steps of refusing to transmit target data or operation instructions to a preset port, so that the target data cannot be written into a target memory of a preset device in a plurality of devices through the preset port. The preset port is a port of the shared operation unit 1 connected to a preset device, the preset device is a device configured with a target memory, and the device can be a real-time computing device or an I/O processing device, when the shared operation unit 1 receives an operation instruction, if it is determined that the operation instruction or a target corresponding to the operation instruction needs to be sent to the preset device through the preset port, the sending is refused, and at this time, the target data is not stored in the target memory of the preset device.
The test system includes N devices (N is greater than 1), and the plurality of devices 1 are devices that are divided among the N devices to perform the current test task, and may be all or part of the N devices. Furthermore, the test system may also execute multiple current test tasks in parallel, and thus, for different current test tasks, the multiple divided devices 1 may be different, or may be coincident, or even identical, which is related to the computing resources provided by the devices and the needs of the users.
When determining that the target data needs to be sent to the designated device, the sharing operation unit 1 also needs to determine the designated device receiving the operation instruction or the target data corresponding to the operation instruction; that is, it is determined to which designated devices the operation instruction or the target data corresponding to the operation instruction needs to be broadcast to perform local storage, where the designated devices are devices configured with the target memory, and include the second device to which the target data needs to be transferred.
In one example, the sharing operation unit 1 is configured to determine at least one specified device from among a plurality of devices and transmit target data to the specified devices when it is determined that the target data needs to be transmitted to the specified devices.
In another example, after the first device acquires the operation instruction, at least one designated device is determined from the plurality of devices, and the second instruction information characterizing the at least one designated device determined by the first device is transmitted to the shared operating unit 1, that is, the object to which the target data is received is designated in the second instruction information, the shared operating unit 1 may acquire the designated device to which the target data needs to be transmitted from the second instruction information, and transmit the target data to the designated devices.
In the above two ways, the first device or the shared operating unit 1 determines at least one designated device from the plurality of devices in any of the following ways:
At least one designated device is all devices in a plurality of devices, and all devices for executing the current test task are taken as designated devices; specifically, at least some of the N devices in the test system are divided to perform the current test task, and the part of the devices performing the current test task is designated as a designated device (which also includes the first device that issues the operation instruction).
At least one of the designated devices is a real-time computing device; that is, all of the real-time computing devices in the plurality of devices performing the current test task are designated devices.
The first device is a real-time computing device and the at least one designated device includes all of the I/O processing devices of the plurality of devices. That is, among the plurality of devices performing the current test task, the target data originating from the real-time computing device is stored into the target memory of the I/O processing device.
The first device is an I/O processing device and the at least one designated device includes all real-time computing devices of the plurality of devices. That is, among the plurality of devices performing the current test task, the target data originating from the I/O processing device is stored into the target memory of the real-time computing device.
The at least one designated device includes a device corresponding to the target data among the plurality of devices, that is, only the second device that needs to use the target data is used as the designated device.
The above-described modes of selecting the designating means may be used in combination with each other without collision. In addition, the above-mentioned test system is exemplified by executing a current test task, and if the current test task is completed and the next test task is started to be executed, the selection of the device executing the test task from the N devices and/or the designated device in the device executing the test task may be changed. If the test system executes a plurality of test tasks simultaneously, the designated device of the devices executing each test task may be selected in the above manner.
When receiving the operation instruction or the target data corresponding to the operation instruction sent by the shared operation unit 1, each of the designating devices may directly store the target data in the local target memory, or may determine whether the target data is required data, and only store the required target data locally.
In one example, the designation device is configured to prohibit a write operation to a target memory of the designation device, or: configured to prohibit execution of a write operation to a target address space of a target memory of a specified device, the target address space including a storage address for storing target data. That is, in the specification device, the target memory may be used for storing target data, or the target address space may be divided into the target memory and dedicated for storing target data, but only the shared memory is supported to write data into the target memory of the specification device or the target address space of the target memory, and the specification device also prohibits writing operation into the target memory or the target address space of the target memory, thereby ensuring data consistency in the target memory of each specification device.
Further, the at least one specifying means further comprises a first means; the first device is also for: target data is read from a target memory of the first device. That is, if the first device is configured with the target memory, it needs to read the target data required by the target test during the test, and also needs to read from the local target memory.
For the second device, it will store the target data in the local target memory; if all the data required by the second device are stored in the local target memory, the second device can store the target data from the local target memory when the second device needs to read the target data; if the data required by the second device is only partially stored in the local target memory, the second device firstly determines whether to read the specified data from the target memory of the second device when the specified data required by the test is required to be read, and if the specified data is determined to be read from the target memory of the second device, the specified data is read from the target memory; if it is determined that the specified data is not to be read from the target memory of the second device, the specified data is read from the shared memory by the shared operation unit.
The second device determines whether the specified data is read from the local target memory or the shared memory as follows:
When the specified data is within the preset data range, determining to read the specified data from the target memory of the second device, namely, presetting data which can be read from the local memory in each device in advance, and then determining where to read the data required for testing according to the preset data, for example, setting according to the data type, wherein one or more types of data are configured to be read from the local target memory, and other types of specified data are configured to be read from the shared memory through the shared operation unit 1; in this case, the preset conditions of the target data are also used together, for example, the data of the types need to be configured to be sent to the designated device, or the types of the target data are not limited.
When the specified data is the target data stored in the target memory, determining to read the specified data from the target memory of the second device, namely, each device records the data stored in the local target memory, determining that the data are read from the local, firstly judging whether the specified data are the data stored in the local when the specified data need to be read, and if so, reading the specified data from the local target memory; if not, the specified data is read from the shared memory.
For example, when receiving an operation instruction sent by the shared memory unit 1, the second device obtains a storage address pointed by the operation instruction, where the storage address is generally an address indicating a shared memory pointed by the operation instruction, so that the second device records storage addresses of all operation instructions sent by the shared memory unit 1, for example, a storage address list may be formed, where the storage addresses include address1_1, address1_2, …, and address1_m, and after obtaining an operation instruction R e for reading the specified data e, the second device determines whether the storage address pointed by the operation instruction R e is already recorded in the storage address list, and if so, reads the specified data e from the local target memory; if not, the specified data e is read from the shared memory.
When the current time is within the specified time range of the specified data, it is determined to read the specified data from the target memory of the second device. That is, after the specified data is stored in the local target memory by the second device, a valid specified time range is configured for the specified data, for example, within 30 seconds after the specified data is stored in the local target memory, if the specified data needs to be read by the second device within the 30 seconds, the specified data can be read from the local memory; if it exceeds 30 seconds, the second device needs to read the specified data into the shared memory. In addition, after the specified data exceeds the corresponding specified time range, the specified data may be deleted; also, different specified data may be configured with different specified time ranges, which may be set based on the acquisition frequency of the specified data, the time interval for acquiring the specified data of the frequency characterization, and the specified time range may be configured to be less than or equal to the time interval.
For example, when receiving the operation instruction sent by the shared memory unit 1, the second device obtains the storage address pointed by the operation instruction, where the storage address is generally an address of the shared memory pointed by the operation instruction, so that it records the storage addresses of all the operation instructions sent by the shared memory unit 1, for example, a storage address list may be formed, where the storage address list includes address1_1, address1_2, …, and address1_m, where the duration of each address is 20 seconds, and if the duration exceeds 20 seconds, the address is deleted from the storage address list; after obtaining an operation instruction R f for reading the specified data f, the second device judges whether a storage address pointed by the operation instruction R f is recorded in a storage address list, if so, the specified data f is read from a local target memory; if not, the specified data f is read from the shared memory.
By way of example, it may also be configured as follows: for each device in the test system, when the specified data required by the test needs to be read, if the target memory is configured in the device and the target data is written in the target memory, the specified data is read from the target memory; if the target memory is not configured in the device or target data is not written in the target memory configured in the device, the specified data is read from the shared memory by the shared operation unit. That is, each device in the test system, if it stores the target data locally, reads only the specified data required for the test locally; if the target data is not stored locally, the designated data is read from the shared memory through the shared operation unit.
The following describes sharing of the target data W by the I/O processing device M with reference to the flowchart of fig. 3 and the above-described procedure, specifically as follows:
The I/O processing apparatus M acquires target data W generated by the test piece acquired by the specified I/O unit (or target data W generated by the specified I/O unit), generates an operation instruction R W (the operation instruction R W points to the storage address_w) for writing the target data W into the shared memory and sends to the shared operation unit, and the shared operation unit executes the operation instruction R W to write the target data W into the storage address_w of the shared memory; then, determining that the operation instruction R W is a write operation instruction, and determining whether the target data W satisfies a preset condition, taking the case that the target data W satisfies the preset condition as an example, that is, the target data W needs to be sent to the designating device, determining that the designating device receiving the target data W is the real-time computing device S1, sending the operation instruction R W or the target data W to the real-time computing device S1, and writing the target data W into the local target memory by the real-time computing device S1; when the real-time computing device S1 needs to read the target data W, it generates an operation instruction R dw1 for reading the target data W, first determines whether the target data W can be read from the local target memory, and when it is determined that the target data can be read from the local target memory, it executes the operation instruction R dw1 to read the target data W from the local target memory.
When the other real-time computing device S2 needs to read the target data W, an operation instruction R dw2 for reading the target data W is generated, whether the target data W can be read from the local target memory is first determined, it is determined that the target data cannot be read from the local target memory, the operation instruction R dw2 is sent to the sharing operation unit, and the sharing operation unit reads the target data W from the sharing memory and sends the target data W to the real-time computing device S2.
In the testing process, the device provided with the target memory in the testing system can directly read at least part of data required by the test from the local memory, so that the data reading efficiency is effectively improved; in particular, for data that needs to be repeatedly read by multiple devices (which may include a real-time computing device and/or an I/O processing device), the multiple devices can directly read the data from the local memory, without reading the data from the shared memory through the shared operation unit, so that the processing burden of the shared operation unit is effectively reduced, and the processing efficiency of the shared operation unit is improved.
A second embodiment of the present invention relates to a test system, and in contrast to the first embodiment, the present embodiment provides various implementation manners for implementing local data reading by a device configured with a target memory in the test system.
Referring to fig. 4, the second device configured with the target memory includes: a designation module 211 and a target memory 212 communicatively connected to each other; the designating module 201 is configured to receive an operation instruction or target data from the shared operating unit 1, send the target data to the target memory of the second device for storage, and read at least part of the target data required for the test from the target memory 212.
In some examples, the assignment module 211 may be an FPGA circuit or an ASIC circuit, i.e., the storage and reading of the target data into the target memory 212 is implemented by an FPGA, ASIC.
In another example, referring to fig. 5, the designating module 211 includes: a data transfer unit 2111 and a processing unit 2112, the data transfer unit 2111 being communicatively connected to the processing unit 2112 and the target memory 212, respectively; the processing unit 2112 may be a CPU processor.
The data transfer unit 2111 is configured to receive an operation instruction or target data from the sharing operation unit 1, and send the target data to a target memory of the second device for storage.
The processing unit 21 is arranged to read at least part of the target data required for the test from the target memory of the second device.
Referring to fig. 6, taking the first device as the real-time computing device 21 and the second device as the I/O processing device 22 as an example, the real-time computing device 21 includes a data transmission unit, a processing unit and a target memory, and a designated module of the I/O processing device 22 is an FPGA circuit, and the FPGA circuit is connected to one or more I/O units 3.
If there is at least one designated I/O unit in the I/O units connected to the I/O processing device 22 in the real-time computing device 21 that needs to share the target data X, an operation instruction R X for writing the target data X into the shared memory 4 is generated first, and the operation instruction R X is sent to the shared operation unit 1 through the data transfer unit, after receiving the operation instruction R X, the shared operation unit 1 obtains the designated device that needs to receive the operation instruction R X, where the designated device at least includes the I/O processing device 22, for example, the shared operation unit 1 in fig. 4 can send the operation instruction R X (or the target data X) to both the real-time computing device 21 (data transfer unit) and the I/O processing device 22 (FPGA circuit), and the data transfer unit in the real-time computing device 21 can directly store the target data X to the connected target memory, and the FPGA circuit in the connected target memory also stores the target data X; when the target data X, which may be data required for specifying an I/O unit or a test piece to which the I/O unit is connected, is required to be used, the subsequent I/O processing device 22 reads the target data X from the local target memory and transmits the target data X to the specified I/O unit.
Referring to fig. 7, taking the first device as the I/O processing device 22 and the second device as the real-time computing device 21 as an example, the real-time computing device 21 includes a data transmission unit, a processing unit and a target memory, and the I/O processing device 22 includes: the data transfer unit is connected to one or more I/O units 3 with a processing unit and a target memory.
The designated I/O unit of the I/O units 3 to which the processing units of the I/O processing device 22 are connected needs to share the target data Y, which may be data generated by the designated I/O unit or data generated by the test piece to which the designated I/O unit is connected, to the real-time computing device 21; the processing unit of the I/O processing device 22 obtains the target data Y from the designated I/O unit, generates an operation instruction R Y for writing the target data Y into the shared memory 4, and sends the operation instruction R Y to the shared operation unit 1 through the data transfer unit, the shared operation unit 1 obtains the designated device that needs to receive the operation instruction R Y after receiving the operation instruction R X, where the designated device at least includes a real-time computing device 21, for example, the shared operation unit 1 in fig. 5 may send the operation instruction R Y (or the target data Y) to the real-time computing device 21 (the data transfer unit) and the I/O processing device 22 (the data transfer unit), the data transfer unit in the real-time computing device 21 may directly store the target data Y to the target memory to which it is connected, and the data transfer unit of the I/O processing device 22 may directly store the target data Y to the target memory to which it is connected; when the target data Y needs to be used, the processing unit of the subsequent real-time computing device 21 reads the target data Y from the local target memory.
Referring to fig. 8, taking a first device as a real-time computing device, a second device as a real-time computing device, and a second real-time computing device as an example, where the first real-time computing device includes a data transmission unit, a processing unit, and a target memory, the second real-time computing device includes: the data transmission unit, the processing unit and the target memory.
The first real-time computing device needs to share the target data Z to the second real-time computing device, the processing unit of the first real-time computing device generates an operation instruction R Z for writing the target data Z into the shared memory 4, and sends the operation instruction R Z to the shared operating unit 1 through the data transfer unit, after receiving the operation instruction R Z, the shared operating unit 1 obtains a designated device that needs to receive the operation instruction R Z, where the designated device at least includes the second real-time computing device, for example, the shared operating unit 1 in fig. 5 can send the operation instruction R Z (or the target data Z) to the first real-time computing device (data transfer unit) and the second real-time computing device (data transfer unit) at the same time, and the data transfer unit in the first real-time computing device can directly store the target data Z to the target memory to which the data transfer unit is connected, and the data transfer unit in the second real-time computing device can directly store the target data Z to the target memory to which the data transfer unit is connected; the processing unit of the second subsequent real-time computing device reads the target data Z from the local target memory when the target data Z needs to be used.
It should be noted that, in fig. 8, the first device and the second device are both real-time computing devices, so that data sharing between the real-time computing devices is realized, and exemplary, the first device and the second device may also be both I/O processing devices, so that data sharing between I/O units may be realized, where the data transmission unit and the processing unit may be combined to implement the function of a specified module, or may also be implemented by an FPGA circuit or an ASCI circuit, and the specific data sharing process is similar and is not repeated herein.
It should be noted that, in the drawings of the present embodiment and the following embodiments, only the first device and the second device, which need to transmit the target data, and the number of devices in the test system are given as examples, but not limited thereto. In the drawing, a line one indicates a path of writing data, a line two indicates a path of transmitting an operation instruction or target data corresponding to the operation instruction to the specification device by the shared operation unit, and a line three indicates a path of reading data.
It can be seen that the data transfer unit is, for example, an IO hub; the data transmission unit can be used for carrying out transmission of operation instructions (mainly transmitting the operation instructions to the shared operation unit) and transmission of data read by the shared operation unit (mainly transmitting the read data to a corresponding device), and can also arbitrate the accessed operation instructions and the transmission sequence of the output operation instructions on the basis of the transmission of the data, and store the data in a local target memory connected with the data transmission unit.
In some embodiments, referring to fig. 9, the I/O processing device 22 as the first device is not configured with a target memory, wherein the designated module is an FPGA circuit, the processing unit is connected to one or more I/O units 3, and the real-time computing device 21 includes a data transfer unit, a processing unit and the target memory; the I/O processing device 22 may also store the target data K in a similar manner to the target memory in the real-time computing device 21, as follows:
The designated I/O unit of the I/O units 3 connected to the FPGA circuit of the I/O processing device 22 needs to share the target data K to the real-time computing device 21, where the target data K may be data generated by the designated I/O unit or data generated by the test piece connected to the designated I/O unit; the FPGA circuit of the I/O processing apparatus 22 obtains the target data K from the specified I/O unit, generates an operation instruction R K for writing the target data K into the shared memory 4, and sends the operation instruction R K to the shared operation unit 1, and after receiving the operation instruction R K, the shared operation unit 1 obtains the specified apparatus that needs to receive the operation instruction R K, and since the target memory is not configured in the I/O processing apparatus 22, the shared operation unit 1 sends only the operation instruction R K (or the target data K) to the real-time computing apparatus 21 (data transfer unit), and the data transfer unit in the real-time computing apparatus 21 can directly store the target data K to the target memory to which it is connected; when the target data K needs to be used, the processing unit of the subsequent real-time computing device 21 reads the target data K from the local target memory.
In this embodiment, the data that cannot be read from the local target memory or the device that does not have the local target memory need to be read from the shared memory by the shared operation unit, and the following description will be given, respectively, wherein the first device and the second device are not provided with the local target memory, and the first device and the second device are provided with the local target memory, respectively, and the following manner may be adopted to read the required data from the shared memory.
As shown in fig. 10 and 11, the real-time computing device 21 includes a data transfer unit and a processing unit, and the I/O processing device 22 includes: a data transfer unit and a processing unit, the processing unit being connected to one or more I/O units 3.
In fig. 10, the real-time computing device 21 shares the data A1 to a designated I/O unit to which the I/O processing device 22 is connected, for example, by: the processing unit of the real-time computing device 21 may generate the data A1 to be issued to the designated I/O unit during the test and generate the operation instruction R A1 (which may be one or more operation instructions) for writing the data A1 into the shared memory 4, and after the processing unit gives the operation instruction R A1 to the corresponding data transfer unit, the data transfer unit may give the operation instruction R A1 to the shared operation unit 1, and the shared operation unit 1 may write the data A1 into the shared memory 4 by executing the operation instruction R A1.
In the case where the data A1 is written into the shared memory 4 and then the data A1 needs to be transferred to a designated I/O unit so as to send the data A1 (or other data obtained by the designated I/O unit based on the data A1) to the tested object, the I/O processing device 22 corresponding to the designated I/O unit needs to read the data A1, at this time, the processing unit of the I/O processing device 22 may generate an operation instruction R dA1 (which may be one or more operation instructions) for reading the data A1, the processing unit may send the operation instruction R dA1 to the shared operation unit 1 after sending the operation instruction R dA1 to the corresponding data transfer unit, and then the shared operation unit 1 may read the data A1 from the shared memory 4 back to the data transfer unit of the I/O processing device 22 and return the data A1 to the corresponding processing unit via the data transfer unit, and the designated I/O unit may send the data A1 (or other data obtained by the designated I/O unit based on the data obtained by the designated I/O unit to the tested object).
In fig. 11, the I/O processing device 22 shares the data A2 to the real-time computing device 21, for example, by: the processing unit of the I/O processing device 22 acquires the data A2 generated by the test piece acquired by the specified I/O unit (or the data A2 generated by the specified I/O unit) and generates the operation instruction R A2 (which may be one or more operation instructions) for writing the data A2 into the shared memory 4, and after giving the operation instruction R A2 to the corresponding data transfer unit, the data transfer unit may give the operation instruction R A2 to the shared operation unit 1, and the shared operation unit 1 may write the data A2 into the shared memory 4 by executing the operation instruction R A2.
In the case that the data A2 needs to be transferred to the real-time computing device 21 after the data A2 is written into the shared memory 4, the real-time computing device 21 needs to read the data A2, at this time, the processing unit of the real-time computing device 21 may generate an operation instruction R dA2 (may be one or more operation instructions) for reading the data A2, and after the processing unit gives the operation instruction R dA2 to the corresponding data transfer unit, the data transfer unit may give the operation instruction R dA2 to the shared operation unit 1, and in turn, the shared operation unit 1 may read the data A2 from the shared memory 4 and return the data A2 to the data transfer unit of the real-time computing device 21 by executing the operation instruction R dA2, so that the processing unit of the real-time computing device 21 may acquire the data A2.
As shown in fig. 12 and 13, the real-time computing device 21 includes a data transfer unit and a processing unit, and the I/O processing device 22 includes: FPGA circuitry connected to one or more I/O cells 3.
In fig. 12, the real-time computing device 21 shares data to a designated I/O unit connected to the I/O processing device 22, and the FPGA circuit in the I/O processing device 22 may implement the functions of the data transfer unit and the processing unit in the I/O processing device 22 in fig. 8, and the specific process is similar to that in fig. 8, and will not be repeated here.
In fig. 13, the I/O processing device 22 shares data to the real-time computing device 21, and the FPGA circuit in the I/O processing device 22 can implement the functions of the data transmission unit and the processing unit in the I/O processing device 22 in fig. 8, and the specific process is similar to that in fig. 9, and will not be repeated here.
As shown in fig. 14, the third real-time computing device and the fourth real-time computing device each include a data transmission unit and a processing unit. When the third real-time computing device shares the data A3 with the fourth real-time computing device, the processing unit of the fourth real-time computing device generates an operation command R A3 (which may be one or more operation commands) for writing the data A3 into the shared memory 4, and sends the operation command R A3 to the shared operation unit 1 through the data transfer unit, the shared operation unit 1 executes the operation command R A3, writes the data A3 into the shared memory 4, and in the case that the data A3 needs to be transferred to the fourth real-time computing device after the data A3 is written into the shared memory 4, the fourth real-time computing device needs to read the data A2, at this time, the processing unit of the fourth real-time computing device may generate the operation command R dA3 (which may be one or more operation commands) for reading the data A3, and after the processing unit gives the operation command R dA3 to the corresponding data transfer unit, the data transfer unit may give the operation command R dA3 to the shared operation unit 1, and then, when the shared operation unit 1 may read the data A3 back from the shared memory 4 through executing the operation command R dA3, the data transfer unit may obtain the data A3 from the fourth real-time computing device, and the fourth real-time computing device may obtain the data.
Fig. 14 is an example of sharing data between two real-time computing devices, but is not limited thereto, and based on a similar manner, it is also possible to implement data sharing between two I/O units transferred between two I/O processing devices, which is not described herein.
It should be noted that, in the test system of the present application, whether the shared operation unit sends the target data to the designated device for local storage can be configured according to the requirement; such as: the sharing operation unit only sends target data shared between at least two real-time computing devices to the real-time computing devices needing to use the target data for local storage, and the target data can be data needing to be interacted between test models running in the real-time computing devices; and if the target data which is needed to be shared between the real-time computing device and the I/O processing device is needed, the target data is not sent to the I/O processing device for local storage.
In the first or second embodiment of the present application, a shared operation unit receives an operation instruction from any one of a plurality of devices (denoted as a target device), the operation instruction is used for writing target data into a shared memory or reading at least part of existing target data in the shared memory, the shared operation unit executes the operation instruction sent by the target device, if the operation instruction is used for writing target data into the shared memory, the operation instruction contains target data to be written, and the shared operation unit executes the operation instruction and writes the target data contained in the operation instruction into the shared memory; if the operation instruction is used for reading at least part of the existing target data in the shared memory, the operation instruction comprises identification information of the target data to be read, the identification information characterizes a device from which the target data is derived, the shared operation unit executes the operation instruction, reads the target data corresponding to the identification information in the operation instruction, and feeds the read target data back to a target device for sending the operation instruction; or the operation instruction contains the position information (for example, an address range) of the target data to be read in the shared memory, the shared operation unit executes the operation instruction, reads the target data indicated by the position information of the operation instruction in the shared memory, and feeds back the read target data to the target device sending the operation instruction.
In one example, each device in the test system is connected to the shared operation unit through a PCIe bus, that is, the shared operation unit is connected to each device through a PCIe connector, so that each device can map target data to be shared into a section of address in the shared memory, each device can read data from the shared memory by accessing local memory data, thereby realizing read-write access of each device to the same memory data, and realizing sharing of target data among a plurality of devices.
The shared operation unit is used as standard PCIe equipment, and can convert an operation instruction of a target device in a plurality of devices into a high-speed serial signal, and transmit the high-speed serial signal representing the operation instruction to the shared operation unit through a high-speed serial bus, and the shared operation unit executes the operation instruction to read and write target data from and into the shared memory.
In one embodiment, the shared operating unit may be implemented using an FPGA.
In one embodiment, the shared operation unit may also be implemented by using a memory expansion controller MXC, which is a memory controller supporting Compute Express Link (CXL) protocols, and the memory expansion controller MXC supports and conforms to the JEDEC standards of DDR4 and DDR5, conforms to the specifications of CXL2.0 and CXL3.0, and supports the transmission speed of PCIE 5.0. The memory expansion controller MXC can realize high-bandwidth, low-delay communication interconnection between each apparatus 1 and the CXL device, allowing each apparatus 1 to realize higher data sharing performance by sharing the memory. When the memory expansion controller MXC is used to implement the sharing operation unit, the customized function and parameter adjustment of the memory expansion controller MXC can be performed based on the data sharing manner of the star connection between the plurality of devices 1 in the embodiment, so as to better perform data sharing.
Specifically, the sharing operation unit comprises a CXL sub-module and a memory connection sub-module, and an MXC controller and a CXL controller which are mutually connected are arranged in the CXL sub-module; the memory connection submodule is provided with a memory DDR4/5 memory controller and a DDR4/5 slot; the CXL controller is connected to the real-time computing device and the I/O processing device through a PCIE interface; the CXL controller is also connected to the shared memory through a memory connection submodule; note that the shared operation unit further includes: peripheral circuits such as a GPIO interface, a JTAG interface, a clock/reset interface, an SPI interface, and the like are not described in detail herein.
In one example, the test system of the present application is an HIL system, please refer to fig. 15, wherein the HIL system comprises: the shared operating unit 1, the shared memory 4, the industrial personal computer pool 20, the I/O pool 30 and the at least one control module 50 are described above.
The industrial personal computer pool 20 can comprise at least one industrial personal computer 201, the I/O pool 30 can comprise at least one I/O unit 3, and each industrial personal computer 201 and each I/O unit 3 can be arranged in different cabinets or in the same cabinet. Specifically, the number of the industrial computers 201 in the industrial computer pool 20 may be fixed or may be expandable, the industrial computers 201 in the industrial computer pool 20 may be disposed in the same cabinet or may be disposed in different cabinets, the number of the I/O units 3 in the I/O pool 30 may be fixed or may be expandable, and the I/O units 3 in the I/O pool 30 may be disposed in the same cabinet or may be disposed in different cabinets.
The industrial personal computer is a real-time computing device, and can be a board card arranged on an industrial control cabinet or an independent device; the control module is one form of I/O processing device.
In one example, the industrial personal computer pool 20 includes a configurable number of at least one industrial personal computer 201 (in the figure, 4 industrial personal computers 201 are set in the industrial personal computer pool 20 as an example), that is, the number of the industrial personal computers 201 in the industrial personal computer pool 20 is expandable, and the number of the industrial personal computers can be configured according to requirements. The computers 201 in the industrial personal computer pool 20 are connected in communication with each other, for example, besides sharing data by using a shared memory unit, they may also be connected together through ethernet communication to transfer other data besides the target data.
In one example, the I/O pool 30 includes a configurable number of at least one I/O cell 3 (3I/O cells 3 are shown as being disposed in the I/O pool 30), i.e., the number of I/O cells 3 in the I/O pool 30 is scalable and the number can be configured as desired. Wherein the I/O units 3 in the I/O pool 30 are communicatively coupled to each other.
The control module 50 is in communication connection with the industrial personal computers 201 in the industrial personal computer pool 20, and the control module 50 is also in communication connection with each I/O unit 3 in the I/O pool 30. Wherein the control module 50 may be a computer including an I/O controller.
The control module 50 and each I/O unit 3 are connected to the same EtherCAT network, where the I/O units 3 and the control module 50 are connected in a cascade manner and communicate based on EtherCAT, and the EtherCAT is adopted to basically meet the low-latency requirement. Furthermore, the I/O unit may also be plugged into the control module, e.g., connected to the control module via a data bus (e.g., PCIe bus) of the control module, etc.
The industrial personal computer 201 can be understood as part or all of the real-time simulator RTPC in the HIL system. The industrial personal computer 201 and the control module 50 may be different computers, or may be different circuit boards, circuits, and the like.
The I/O unit 3 therein may be understood as an input/output unit.
The specific method can be understood as follows: the I/O unit 3 satisfies at least one of:
data can be input to the object 6;
the data can be output relative to the measured piece 6;
data can be input to the industrial personal computer 201;
the output of data can be realized relative to the industrial personal computer 201;
The data a input and/or output by the I/O unit 3 with respect to the tested object 6 may be related or unrelated to the data B input and/or output by the I/O unit 3 with respect to the industrial personal computer.
Specifically, the data a and the data B may be data in different forms with the same content, for example, a digital signal with a certain content is received from the industrial personal computer 201, an analog signal with the same content is sent to the tested piece 6, or vice versa, for example, a signal before the injection failure is received from the industrial personal computer 201, and a signal after the injection failure of the I/O unit 3 is sent to the tested piece 6;
The data A and the data B can also be data with the same content and the same form;
The data a and the data B may also be data with different contents, for example, the data a and the data B are respectively a trigger signal for triggering the I/O unit 3 to generate a signal Sign1 and the signal Sign1, and for example, the I/O unit 3 needs to obtain a certain condition signal from the industrial personal computer 201 to simulate a Sing signal to be sent to the tested piece 6, and at this time, the condition signal and the signal Sign2 are respectively the data a and the data B;
The I/O unit 3 may refer to a circuit, a circuit board, or a device including a circuit board and other components.
In one example, the I/O unit 3 may interact with an industrial personal computer via a control module, or may interact with a test object (e.g., a controller of a vehicle) directly or via an exchange matrix.
The I/O unit 3 may implement only input and/or output functions, and in some examples, may process the transmitted signals during input and/or output, for example, perform signal conversion, fault simulation, information simulation, signal generation, on-off control, and so on. It will be seen that this may be an implementation of the I/O unit 3, whether or not other functions are integrated as well.
The I/O unit 3 may be an I/O board, for example, a board that supports at least one of the following functions: digital signal input, analog signal input, digital signal output, analog signal output, PWM signal input, PWM signal output, high side power output and low side power output. The method can further realize the collection and output of high-speed signals, and can realize the flexible configuration of board card resources according to requirements, and the board card precision and sampling frequency index brought by the technology reach the industry leading level.
The I/O board card is shown by at least one of the following: AD PWM-IN board card, DAC board card, FIU board card, PWM-OUT board card, RELAY-IO board card, RC board card, PSI5& DSI3& SENT board card, multi-bus board card (Flexray/CANFD/LIN), eth (vehicle-mounted with large network) board card, etc.;
The I/O card may also be, for example, at least one of the following specialized cards: current output board card, thermocouple board card, battery simulator, temperature simulator, motor board card, IO_HUB board card.
In one example, the HIL system may further comprise a cluster server, or at least one device (e.g., one of the real-time computing devices) of the plurality of devices may be configured to act as a cluster server, where the cluster server may be configured to determine data transfer information (e.g., data transfer relationships) for each test task, such as data transfer relationship information for each target test task, where the data transfer relationship information may be configured to determine real-time computing devices and I/O units for performing the target test task, such as real-time computing devices and I/O units for directly or indirectly sharing target data with each other when performing the corresponding test task, and such as real-time computing devices for directly or indirectly sharing target data with each other when performing the corresponding test task, and such as I/O units for directly or indirectly sharing target data with each other when performing the corresponding test task.
When the HIL system executes the target test task, the target data is transmitted among the real-time computing device, the I/O processing device and the I/O unit based on the data transmission relation.
In the HIL system, for the current test task, a data transmission relationship between at least part of the I/O units 3 and at least part of the industrial personal computers 201 is determined by a cluster server in the HIL system. Wherein the cluster server may be connected to one computer of each of the industrial computers 201, or any of the industrial computers 201 is configured as a cluster server.
The data transmission relationship can be understood as: the industrial personal computer 201 and the I/O unit 3 for determining that data needs to be shared directly or indirectly with each other when performing the corresponding test task may further at least represent: one relationship between one or more computers 201 (i.e., at least a portion of computers 201) and one or more I/O units 3 (i.e., at least a portion of I/O units 3) that allows data to be transferred is to delineate the computers 201, 3 that allow data to be transferred.
In one example, the data transmission relationship can further determine to which industrial personal computer 201 the data transmitted by the industrial personal computer 201 should be synchronized, and to which I/O unit 3 the data transmitted by the industrial personal computer 201 should be synchronized, i.e. the mapping relationship between the industrial personal computer 201 and the I/O unit 3 is defined in detail, and further, the data transmission relationship can carefully define the mapping relationship between the ports of the industrial personal computer 201 and the ports and channels of the I/O unit 3; the ports may refer to hardware ports, or may refer to software ports, addresses, etc. (e.g., a certain output port, an input port of a certain model running in an industrial personal computer); further, when the mapping relationship is described, the I/O unit 3 and the industrial personal computer 201 which allows data transmission can be shown.
In another example, the data transmission relationship is mainly used to define the range of the I/O unit 3 and the I/O unit 201 that is allowed to transmit data, and as to which I/O unit 3, the tested object or port (I/O unit 3 or port of the tested object 6) the I/O unit 3 transmits data to which I/O unit 201 or which port of the I/O unit 201 is required to transmit data, the data transmission relationship may be determined by other means.
In addition, if there are a plurality of control modules 50, and different control modules 50 are connected to different I/O units 3, then in one example, the data transmission relationship can be understood as: at least, the I/O unit 3 connected to the industrial personal computer 201 and the control module 50 is used to define the range of the industrial personal computer 201 and the I/O unit 3 that allow data transmission.
Different data transmission relations can be determined according to different tasks, and the different tasks can be executed simultaneously or sequentially.
After determining the data transmission relationship between at least part of the I/O units 3 and at least part of the industrial personal computers 201, the cluster server completes data transmission between the I/O units 3 and the industrial personal computers 201 in a plurality of ways based on the data transmission relationship, and takes the example that the cluster server determines the data transmission relationship between K industrial personal computers 201 and L I/O units 3.
In one example, the cluster server sends the data transmission relationship to the K industrial personal computers 201, respectively, so that the industrial personal computer 201 can know which I/O channel going to which I/O unit 3 obtains the target data when the target data needs to be obtained based on the data transmission relationship; when the target data needs to be sent to the tested piece, the I/O channel of which I/O unit 3 is sent with the target data can be known; the connection relationship between the control module 50 and the I/O unit 3 is fixed, so that the industrial personal computer 201 can know from which control module 50 the required target data is acquired, and can also know to which control module 50 the target data is transmitted. Specific: when the industrial personal computers 201 need to send the issue information to the tested piece, the I/O units 3 for receiving the issue information are designated based on the data transmission relationship, and then the control module 50 sends the issue information to the tested piece through the designated I/O units 3. In addition, when the measured piece needs to send the report information to the industrial personal computer 201, the control module 50 receives the report information through L I/O units 3, and the I/O units 3 may mark the I/O units 3 that send each report information, so that each industrial personal computer 201 receives the report information from the specified I/O unit 3 based on the above data transmission relationship.
Assuming that data transmission is required between one of the computers 201 and the I/O unit 3 to which one of the control modules 50 is connected, the computer 201 is denoted as an a device and the control module 50 is denoted as a B device.
For example, the address space of each device (including the industrial personal computer 201 and the control module 50) is preset in the memory of each device, when the device a transmits the target data to be shared to the device B, the device a may write the target data to the corresponding address space in the memory of the device B, and the device B may periodically acquire data from the corresponding address space in the memory, where if the device B is to distribute the acquired data to the I/O unit 3, in one scheme, the device a may write the identifier of the I/O unit 3 (or the I/O channel thereof) in the shared target data, and the device B may distribute the data according to the identifier included in the acquired (or I/O channel thereof) data; alternatively, different I/O units 3 of the B device may be allocated with different address subspaces, and the a device may instruct to write the target data to the corresponding address subspace when sharing the target data, and the B device may only need to read from the address subspace to give the corresponding I/O unit 3.
When the device A acquires target data from the device B, the device A can also directly take the data from the corresponding address space or address subspace of the device B based on the data transmission relation and then send the data to the corresponding port of the corresponding model according to the data transmission relation; wherein the model may refer to a test simulation model running in device a. Or alternatively
When the device A acquires target data from the device B, the device B can write the target data into the corresponding address space of the device A, and the device A can regularly take the target data from the address space corresponding to the device A in the memory, and at the moment, if the target data is to be given to the corresponding model and the port thereof; under one scheme, the B device may write the identity of the I/O unit 3 (or its I/O channel) in the shared target data, and the a device knows which port of which model the data from the I/O unit 3 (or its I/O channel) should be given to based on this identity and the data transfer relationship.
In another example, the cluster server sends the data transmission relationship to one or more control modules 50 connected to the L I/O units 3, and when it is required to send the downlink information to the tested object, each industrial personal computer 201 directly sends the downlink information to the control module 50, and based on the data transmission relationship, the control module 50 sends each downlink information to the tested object through the designated industrial personal computer 201. Similarly, when the measured piece needs to send the report information to the industrial personal computer 201, the control module 50 receives the report information through the L I/O units 3, and the control module 50 sends the report information from each I/O unit 3 to the designated industrial personal computer 201 based on the above data transmission relationship.
For example, in the process of executing a certain test task, the K industrial personal computers 201 and the L I/O units 3 are used for testing the tested piece 6, and the L I/O units 3 are connected to the tested piece 6; the data transmission relation defines the flow direction of target data between the industrial personal computer 201 and the I/O unit 3, namely, after the report information which is from the tested piece 6 or the I/O unit 3 and needs to be sent to the industrial personal computer 201 is transmitted to the I/O unit 3, each I/O unit 3 sends the report information to the control module 50, and the data transmission relation determines the industrial personal computer 201 (or the port thereof) to which the control module needs to send the report information which is from each I/O unit; after the downlink information generated by the target industrial personal computer and to be sent to the tested piece 6 or the I/O unit 3 is transmitted to the control module, the data transmission relationship determines that the control module sends the downlink information from each industrial personal computer 201 to the tested piece 6 or the I/O unit 3, where the tested piece 6 can receive different information through different pins. When transmitting the issuing information to the control module 50, the industrial personal computer 201 may add its own identity or the identity of the I/O unit 3 receiving the data into the issuing information; when the I/O unit 3 transmits the report information to the control module 50, the identity of the I/O unit may be added to the report information or the identity of the industrial personal computer 201 that receives the report information; the control module 50 thus forwards data between the industrial personal computer 201 and the I/O unit 3 based on the identification carried in the information and the data transmission relationship.
It can be seen that the control module 50 can be used to realize the selection of the interaction path between the industrial personal computer 201 and the I/O unit 3.
The ports referred to herein may refer to hardware ports, as well as software ports, port addresses, etc. (e.g., a certain output port, input port of a certain model running in an industrial personal computer).
The control module 50 may obtain some or all of the data transfer relationships from the cluster server, or other information used to determine the data transfer relationships, which may be obtained via ethernet, for example. The cluster server is connected to each industrial personal computer 201, and is used for transmitting test related data to each industrial personal computer 201 and configuring the data transmission relation of the control module 50.
In addition, at the same time, the I/O units 3 connected to the single control module 50 may be used for the same test task, or may be partially used for one test task, or may be partially used for other test tasks, and the control module 50 may acquire the required data transmission relationships separately or together.
In addition, other switching circuits, interfaces, etc., such as DB9 interfaces, EDAC interfaces, BOB modules, etc., may also be provided between the test piece and the I/O unit.
It should be noted that, in fig. 15, the number of control modules 50 is taken as an example, but the number of control modules 50 is not limited thereto, and may be plural, each control module 50 corresponds to one or plural I/O units 3, each I/O unit 3 corresponds to only one control module 50, and each control module 50 is connected to a corresponding I/O unit 3; for the current test task, each control module 50 may determine a data transmission relationship corresponding to itself, for example, any one control module 50 is taken as an example, the data transmission relationship determined by the control module 50 defines a data transmission relationship between at least a portion of the industrial personal computers 201 and all the target I/O units, where the target I/O units are I/O units corresponding to the control module 50, that is, the control module 50 determines to which industrial personal computer 201 the data transmitted by each target I/O unit is synchronized, and to which target I/O unit the data transmitted by the industrial personal computer 201 is synchronized. Wherein, each control module 50 and the corresponding I/O unit 3 may be connected in a cascade manner, as shown in fig. 3, taking the number of control modules 50 as 2, and each control module 50 corresponds to 3I/O units 16 as an example; or each control module 50 is directly connected to a corresponding I/O unit 3, as shown in fig. 17, for example, the number of control modules 50 is 2, and each control module 50 corresponds to a plurality of I/O units 3.
In this embodiment, each I/O unit 3 is directly or indirectly connected to the tested piece 6, and the number of tested pieces 6 may be one or more. In fig. 15 to 17, taking the direct connection of the I/O unit 3 and the tested piece 6 as an example, that is, the tested piece 6 is directly connected to the port of each I/O unit 3 through a connector, so as to realize signal transmission; different I/O units 3 may be connected to different pins of the test piece 6 to transmit different information. In another example, a switching matrix may also be provided in the HIL system, which is connected between the I/O units 3 and the test pieces 6, i.e. each I/O unit 3 is indirectly connected to a corresponding test piece 6 via the switching matrix.
It can be seen that, in order to realize corresponding communication among the industrial personal computer, the I/O unit and the tested piece and realize transmission of the target data, the switching matrix is configured, and the data transmission relation of the control module is also configured under the condition that the switching matrix is arranged. And further realizing data transmission required by the test between the industrial personal computer and the tested piece, for example, data transmission between a port of a simulation model in the industrial personal computer and a port of the tested piece. In this way, the connection mode of the tested piece in access is more flexible and free, and only the switching matrix needs to be configured according to the actual access condition, for example, after the control module 50 is configured, if the switching matrix is not set, it is necessary to find out which I/O units the tested piece is accessed to according to the configuration result, how to connect, and under the condition of setting the switching matrix, the tested piece can be accessed to the switching matrix more freely, and then only the switching matrix needs to be configured to achieve the data transmission required by the test.
It should be noted that, the test system is taken as an HIL system as an example, but the test system is not limited to this, and may be a system used in other application scenarios, for example, the test system may be a simulation injection system, and may implement simulation injection of virtual video, where the real-time computing device may not only be an industrial personal computer, but also may be a computer (which may be understood as a simulation server) for generating a simulation video image, and may simulate injection of virtual video into a tested piece connected to the I/O processing device through the I/O unit. The object to be tested by the test system may be an ECU, a test stand, an ECU for a vehicle, a test stand, or the like, or a controller or a test stand for an unmanned aerial vehicle, an aircraft, a ship, or the like.
While the preferred embodiments of the present invention have been described in detail above, it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above detailed description. In general, in the claims, the terms used should not be construed to be limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled.
Claims (16)
1. A test system, the test system comprising: at least one I/O unit, a plurality of devices and a shared operating unit;
The plurality of devices comprise at least one real-time computing device and at least one I/O processing device, wherein the I/O processing device is connected to at least one I/O unit, and the I/O unit is directly or indirectly connected to a tested piece;
A first device of the plurality of devices is used for acquiring an operation instruction for performing target operation on a shared memory and sending the operation instruction to the shared operation unit; the target operation is used for writing target data into the shared memory; the target data is data which needs to be transferred between the first device and a second device in the plurality of devices in the process of testing the tested piece, and a target memory is configured in the second device;
The sharing operation unit is configured to cause the target data to be stored in a target memory of at least one designated device among the plurality of devices, the at least one designated device including the second device;
the second device is used for reading at least part of the target data required for testing from a target memory of the second device.
2. The test system of claim 1, wherein the second means comprises: designating a module and a target memory;
The designating module is used for receiving the operation instruction or the target data from the sharing operation unit, sending the target data to a target memory of the second device, and reading at least part of the target data required by the test from the target memory.
3. The test system of claim 2, wherein the assignment module comprises: a data transfer unit and a processing unit;
The data transfer unit is used for receiving the operation instruction or the target data from the sharing operation unit and sending the target data to a target memory of the second device;
The processing unit is used for reading at least part of the target data required for testing from a target memory of the second device.
4. The test system of claim 1, wherein the designated device is configured to prohibit a write operation to a target memory of the designated device or: is configured to prohibit execution of a write operation to a target address space of a target memory of the specified device, the target address space including a storage address for storing the target data.
5. The test system of claim 1, wherein the at least one designated device further comprises the first device;
The first device is further configured to: the target data is read from a target memory of the first device.
6. The test system according to claim 1, wherein the shared operating unit, when causing the target data to be stored in the target memory of at least one designated device of the plurality of devices, is specifically configured to: the target data is written into the target memory of the specified device.
7. The test system according to claim 1, wherein the shared operation unit is configured to cause the target data to be stored in a target memory of at least one designated device of the plurality of devices when the target data corresponding to the operation instruction satisfies a preset condition.
8. The test system of claim 7, wherein the preset conditions include any one or any combination of the following:
the target data is derived from a first designated device of the at least one real-time computing device or a first designated port of the real-time computing device;
the target data is to be sent to a second designated device of the at least one real-time computing device or a second designated port of the real-time computing device;
The target data is data that needs to be transferred between the real-time computing devices;
the target data is derived from a first designated I/O unit of the at least one I/O unit or a third designated port of the I/O unit;
The target data is required to be sent to a second designated I/O unit of the at least one I/O unit or a fourth designated port of the I/O unit;
the target data is for being written to a specified address;
the target data are data containing preset identifiers;
the target data are located in a first preset data list;
the target data are located outside a second preset data list;
The acquisition frequency of the target data is smaller than a preset frequency threshold;
The target data is to be transmitted to a plurality of second devices.
9. The test system of claim 1, wherein the shared operating unit is further configured to:
And refusing to transmit the target data or the operation instruction to a preset port so that the target data cannot be written into a target memory of a preset device in the plurality of devices through the preset port.
10. The test system of claim 1, wherein the test system comprises N devices, N being greater than 1;
the plurality of devices are ones of the N devices for performing a current test task.
11. The test system of claim 10, wherein the at least one designated device satisfies at least one of:
the at least one designated device is all of the plurality of devices;
the at least one designated device is the real-time computing device;
The first device is the real-time computing device, the at least one designated device includes all I/O processing devices of the plurality of devices;
the first device is the I/O processing device, the at least one designated device includes all real-time computing devices of the plurality of devices;
The at least one designated device includes the device of the plurality of devices corresponding to the target data.
12. The test system of claim 1, wherein the second means is for:
determining whether to read the specified data from a target memory of the second device when the specified data required for the test needs to be read;
if yes, reading the specified data from the target memory;
if not, the specified data is read from the shared memory through the shared operation unit.
13. The test system of claim 12, wherein the second means is for:
Determining to read the specified data from a target memory of the second device when the specified data is within a preset data range; and/or the number of the groups of groups,
When the current time is within the specified time range of the specified data, it is determined to read the specified data from the target memory of the second device.
14. The test system of claim 12, wherein the second means is for:
If the specified data is the target data, it is determined to read the specified data from a target memory of the second device.
15. The test system according to claim 1, wherein the shared operation unit is configured to execute the operation instruction to write the target data into the shared memory;
At least one third device of the plurality of devices is configured to: at least part of the target data required for the test is read from the shared memory by the shared operation unit.
16. The test system of claim 1, wherein the test system is a HIL system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311414737 | 2023-10-27 | ||
| CN2023114147373 | 2023-10-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117891236A true CN117891236A (en) | 2024-04-16 |
Family
ID=90648745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410081374.4A Pending CN117891236A (en) | 2023-10-27 | 2024-01-19 | Test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117891236A (en) |
-
2024
- 2024-01-19 CN CN202410081374.4A patent/CN117891236A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6813732B2 (en) | Trace circuit | |
| CN113076227A (en) | MCU verification method, system and terminal equipment | |
| CN111782154B (en) | Data moving method, device and system | |
| CN114564428B (en) | I/O port expansion system of airborne electronic equipment | |
| US11237832B2 (en) | Module with a serialization unit and improved compatibility with deserialization units of different series | |
| CN117148817A (en) | Test system | |
| CN114444422A (en) | Chip verification system, method and storage medium | |
| Kwon et al. | Gen-z memory pool system architecture | |
| CN113128144A (en) | Prototype verification system and simulation platform for verifying logic system design | |
| CN117891236A (en) | Test system | |
| CN215219509U (en) | Entertainment system test bench based on domain controller electrical architecture | |
| CN118012007A (en) | Test system | |
| CN112966335B (en) | Interface simulation device and automatic driving simulation test platform | |
| CN113157602B (en) | Method, equipment and computer readable storage medium for distributing memory | |
| CN115312094A (en) | SRAM control system and method, FPGA chip and electronic equipment | |
| CN103856363A (en) | System for testing subservers with many test phases and method thereof | |
| CN114442590A (en) | Vehicle diagnosis method, apparatus, diagnosis communication device, server, and storage medium | |
| CN102385547A (en) | Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller | |
| US9229737B2 (en) | Method and system of emulating devices across selected communication pathways through a terminal session | |
| CN216014148U (en) | Server and server backboard | |
| CN116820867B (en) | Chip debugging method and device and chip | |
| CN111459867B (en) | Method, device, converter and storage medium for converting USB (Universal Serial bus) into SMI (SMI) | |
| CN114444423A (en) | Data processing method and system based on verification platform and electronic equipment | |
| CN115905036A (en) | Data access system, method and related equipment | |
| CN117971578A (en) | Data processing system, method, device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |