CN117971578A

CN117971578A - Data processing system, method, device, electronic equipment and storage medium

Info

Publication number: CN117971578A
Application number: CN202410117511.5A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Bi Ren Technology Co ltd
Current assignee: Shanghai Bi Ren Technology Co ltd
Priority date: 2024-01-26
Filing date: 2024-01-26
Publication date: 2024-05-03

Abstract

The invention provides a data processing system, a method, a device, electronic equipment and a storage medium, and relates to the technical field of chip verification; the system comprises a circuit DUT to be tested, a first intellectual property VIP and a second VIP; the first VIP is used for receiving a first command from the DUT and writing target data carried by the first command into the memory; or receiving a first atomic operation request from the DUT, and writing target data carried by the first atomic operation request into a memory; a second VIP to receive a second command from the DUT; based on the second command, the target data or the history data is read from the memory. The system avoids the data narrow transmission behavior caused by the condition that one VIP does not support the inconsistency of the data bit widths of the DUTs, and solves the problem that the VIP can still be used for verifying the DUTs under the condition that the read-write data bit widths of the DUTs are inconsistent.

Description

Data processing system, method, device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of chip verification technologies, and in particular, to a data processing system, a method, an apparatus, an electronic device, and a storage medium.

Background

In chip design, to increase throughput, advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA) high-performance expansion bus interface (Advanced eXtensible Interface, AXI) is commonly used to interact with peripherals. Authentication intellectual property (Verification Intellectual Property, VIP), also known as authentication IP, is a tool commonly used to support authentication of AXI buses.

In practical application, when verifying the AXI bus, the data bit width of the AXI bus read-write data channel may be inconsistent, but VIP does not support the situation of inconsistent data bit width of the read-write data channel. Under the above circumstances, when the tested AXI bus sends data to the VIP, the VIP cannot receive correct data, and thus the VIP cannot verify the AXI bus.

Therefore, how to realize the verification of the AXI bus under the condition that the data bit widths of the AXI bus read-write data channels are inconsistent is a problem to be solved at present.

Disclosure of Invention

Aiming at the problems existing in the prior art, the embodiment of the invention provides a data processing system, a data processing method, a data processing device, electronic equipment and a storage medium.

The invention provides a data processing system, which comprises a circuit DUT to be tested, a first intellectual property verification VIP and a second VIP;

The DUT and the write address channel port, the write data channel port and the write response channel port corresponding to the first VIP are connected with each other;

The DUT and the write address channel port, the write data channel port, the read address channel port and the read data channel port corresponding to the second VIP are connected with each other;

The data bit widths of the first type channel and the second type channel corresponding to the DUT are different; the data bit widths of the first type channels corresponding to the first VIP and the second VIP are different, and the data bit widths of the second type channels corresponding to the first VIP and the second VIP are different; the first type channel comprises at least one of a write address channel, a write data channel and a write response channel, and the second type channel comprises at least one of a read address channel and a read data channel; wherein,

The first VIP is used for receiving a first command from the DUT and writing target data carried by the first command into a memory; or alternatively

Receiving a first atomic operation request from the DUT, and writing the target data carried by the first atomic operation request into the memory;

the second VIP is configured to receive a second command from the DUT; based on the second command, the target data or history data is read from the memory.

Optionally, the read address channel port and the read data channel port corresponding to the first VIP are suspended, and the write response channel port corresponding to the second VIP is suspended.

Optionally, the first command includes any one of the following:

A data writing request;

And a second atomic operation request, configured to instruct the first VIP to write the target data into the memory.

Optionally, the first VIP is specifically configured to:

receiving the write data request from the DUT; writing the target data carried in the data writing request into the memory;

Or alternatively

Receiving the second atomic operation request from the DUT; and writing the target data carried in the second atomic operation request into the memory.

Optionally, the second VIP is specifically configured to:

after the first VIP writes the target data carried in the write data request into the memory, receiving a second command from the DUT; the second command is a read data request;

reading the target data from the memory based on the read data request;

The target data is sent to the DUT.

Optionally, the second VIP is specifically configured to:

Receiving a second command from the DUT, the second command being the first atomic operation request;

Reading the history data from the memory based on the first atomic operation request;

the historical data is sent to the DUT.

Optionally, the first VIP is specifically configured to:

Receiving the first atomic operation request from the DUT;

And after the second VIP reads the historical data from the memory, writing the target data carried by the first atomic operation request into the memory.

Optionally, the read-write data bit width of the memory is the same as the data bit widths of the first type channel and the second type channel corresponding to the first VIP.

The invention also provides a data processing method applied to the first VIP, which comprises the following steps:

receiving a first command from a circuit DUT to be tested, and writing target data carried by the first command into a memory;

Or alternatively

Receiving a first atomic operation request from the DUT;

After a second VIP reads historical data from the memory and sends the historical data to the DUT, writing the target data carried by the first atomic operation request into the memory;

Wherein the data bit widths of the first type channel and the second type channel corresponding to the DUT are different; the data bit widths of the first type channels corresponding to the first VIP and the second VIP are different, and the data bit widths of the second type channels corresponding to the first VIP and the second VIP are different; the first type of channel includes at least one of a write address channel, a write data channel, and a write response channel, and the second type of channel includes at least one of a read address channel and a read data channel.

The invention also provides a data processing method which is applied to the two VIPs, and the method comprises the following steps:

receiving a second command from the circuit under test DUT;

In the case where the first VIP writes target data to a memory and the second command is a read data request, reading the target data from the memory based on the read data request;

Or alternatively

Reading historical data from the memory based on a first atomic operation request if the second command is the first atomic operation request;

The invention also provides a data processing device applied to the first VIP, the device comprises:

The first receiving module is used for receiving a first command from the circuit DUT to be tested and writing target data carried by the first command into the memory;

receiving a first atomic operation request from the DUT;

The present invention also provides a data processing apparatus for use with a second VIP, the apparatus comprising:

the second receiving module is used for receiving a second command from the circuit DUT to be tested;

a reading module, configured to, in a case where a first VIP writes target data into a memory and the second command is a read data request, read the target data from the memory based on the read data request;

Or alternatively

The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing a data processing method as described in any of the above when executing the program.

The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a data processing method as described in any of the above.

The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements a data processing method as described in any of the above.

According to the data processing system, the method, the device, the electronic equipment and the storage medium, through the interconnection of the write address channel port, the write data channel port and the write response channel port corresponding to the DUT and the first VIP, the first command or the target data carried by the first atomic operation request are written into the memory under the condition that the first VIP receives the first command or the first atomic operation request from the DUT; the DUT and a write address channel port, a write data channel port, a read address channel port and a read data channel port corresponding to the second VIP are connected with each other, so that target data or historical data is read from the memory under the condition that the second VIP receives a second command from the DUT; in the data processing system, the write request and the read request of the DUT are respectively realized by using the two VIPs with different data bit widths, namely, the first VIP can correctly receive target data sent by the DUT and correctly write the target data into the memory, and the second VIP can correctly read target data or history data required by the DUT from the memory, so that the data narrow transmission behavior caused by the condition that one VIP does not support inconsistent data bit widths of the DUT is avoided, and the problem that the DUT can still be verified by the VIP under the condition that the read-write data bit widths of the DUT are inconsistent is solved.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of one of the architectures of a data processing system provided by the present invention;

FIG. 2 is a second schematic diagram of a data processing system according to the present invention;

FIG. 3 is a schematic flow chart of a data processing method according to the present invention;

FIG. 4 is a second flow chart of the data processing method according to the present invention;

FIG. 5 is a schematic diagram of a signaling flow for data processing performed by the data processing system according to the present invention;

FIG. 6 is a second diagram illustrating a signaling flow of a data processing system according to the present invention;

FIG. 7 is a third diagram illustrating a signaling flow for data processing performed by the data processing system according to the present invention;

FIG. 8 is a schematic diagram of a data processing apparatus according to the present invention;

FIG. 9 is a second schematic diagram of a data processing apparatus according to the present invention;

fig. 10 is a schematic structural diagram of an electronic device provided by the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In order to facilitate a clearer understanding of various embodiments of the present application, some relevant knowledge will be presented first.

In chip design, to improve throughput, AMBA AXI bus is commonly used to interact with peripherals. VIP is the most commonly used tool to support validating AXI buses. For example, the VIP may implement data-to-communication protocol conversion: the data transmitting terminal inputs the wanted data to the VIP, and the VIP outputs the data conforming to the corresponding communication protocol, and the data can be directly used as an input signal of the corresponding module. For another example, the VIP may be used to verify whether the output data conforms to the timing of the corresponding communication protocol and whether the output data is correct.

Taking the AXI bus based on the AXI 5 protocol as an example, AXI 5VIP is the most commonly used tool to support validating the AXI 5 bus.

However, in practical application, when AXI bus is designed according to different bandwidth requirements, the data bit widths of the read-write data channels may not be consistent, and the scenario is in accordance with the protocol, but some VIPs do not provide support for such scenarios; that is, some VIPs do not support verification of AXI buses where the data bit widths of the read and write data channels are inconsistent.

For example, when the read bit width of the AXI bus is greater than the write bit width, if the read bit width of the AXI bus is the maximum bit width of the VIP, the actual bit width of the write request of the AXI bus will be smaller than the write bit width of the VIP interface at this time, and at this time, narrow transmission needs to be performed according to the protocol, so that the VIP cannot receive the correct data sent by the AXI bus, and verification on the AXI bus cannot be achieved.

In the related art, for a scenario that VIP does not support inconsistency of data bit widths of read-write data channels, there are generally the following solutions:

1. Waiting for vendor repair problems, but timeliness is not guaranteed.

2. Other manufacturers' AXI VIP kits are purchased, but such solutions are time consuming and expensive, and such VIPs are not typically sold separately, requiring a bundle of purchase of other kits.

3. AXI VIP was self-ground. The proposal has high requirements on time and manpower and the reliability is not well ensured although the proposal is once and forever

Based on the technical problems, the invention provides a data processing system, a method, a device, electronic equipment and a storage medium, which can verify a circuit to be tested (Device Under Test, DUT) by using VIP under the condition that the read-write data bit widths of an AXI bus are inconsistent. It is understood that DUT refers to the AXI bus under test.

The data processing system provided by the present invention is described in detail below with reference to fig. 1-2. FIG. 1 is a schematic diagram of a data processing system according to the present invention, wherein:

The data processing system includes a DUT, a first VIP (i.e., VIP 0 in fig. 1 as slave (slave) end), and a second VIP (i.e., VIP 1 in fig. 1 as slave end). In practical applications, the DUT may be an AXI bus to be verified, and the data processing system provided by the embodiment of the present invention will be further described below by taking an AXI bus based on the XAI 5 protocol as an example. For convenience of description, VIP 0 refers to the first VIP, and VIP 1 refers to the second VIP.

The write address channel (WRITE ADDRESS CHANNEL, AW) port, write data channel (WRITE DATA CHANNEL, W) port, and write response channel (write response channel, B) port corresponding to the DUT and VIP 0 are connected to each other. Through the connection mode, the VIP 0 only responds to the write request of the DUT and is used for completing the write request of the DUT.

The AW port, W port, read address channel (READ ADDRESS CHANNEL, AR) port, read data channel (READ DATA ADDRESS CHANNEL, R) port, corresponding to the DUT and VIP 1, are connected to each other. Through the connection mode, the VIP 1 can respond to the read request of the DUT and the special Atomic (Atomic) request.

In practical application, the AR port and the R port corresponding to VIP 0 may be suspended, that is, the AR port and the R port corresponding to VIP 0 are not connected. The B port corresponding to the VIP 1 is suspended, namely the B port is not connected. By the method, the VIP 0 can only respond to the write request of the DUT, and the VIP 1 can respond to the read request and the Atomic request of the DUT.

Note that the AXI protocol specifies 5 channels: AW, W, B, AR and R channels, wherein there is no dependency between AW, W and B channels and AR and R channels. In practice, some AXI protocols, such as AXI 5, have a special Atomic request, including multiple types of Atomic operations, such as Atomic store (AtomicStore) requests, atomic Load (Atomic Load) requests, atomic Compare (Atomic Compare) requests, and Atomic Swap (Atomic Swap) requests.

Wherein AtomicStore request refers to: the master (master) sends AtomicStore type write operation carrying source data, after receiving AtomicStore type write operation, the slave receives source data, returns response to the master, and then processes source data to a certain extent.

The Atomic Load request refers to: the master terminal sends an operation of an atmospheric Load type to a certain address of the slave terminal and carries source data; the data stored at the slave end is destination data (destination data); the slave end performs certain processing on source data and self-stored destination data, and the slave end also returns destination data to the master end.

An Atomic compound request refers to: the master sends an Atomic complex type write operation to a certain address of the slave, and two data are needed to be carried: one is comparison data (compare data), and one is source data; the data stored at the slave end is the destination data. The master-end-transmitted write operation of the atmospheric computer type carries the Compare data and the source data, and the slave can detect whether the Compare data is consistent with the self-stored destinationdata or not; if the data are consistent, replacing the destination data with source data; if the source data are inconsistent, discarding the source data, and reserving the original destination data. It should be noted that, no matter whether the compatibility data and the degradation data are consistent or not, the slave end needs to return the degradation data to the master end.

The Atomic Swap request refers to: the master sends an Atomic Swap type write operation to a certain address of the slave, and the master needs to carry a data source data, and the data stored in the slave is destination data. The slave end replaces the destination data with source data, and then returns the destination data to the master end.

When the AXI bus sends an Atomic Load/computer/Swap request, a write request is sent through the AW channel, and read data is received through the R channel. Based on the above, the invention simulates the slave end with two VIPs for the AW, W, B channel, AR, R channel respectively through the architecture of the data processing system, and is used for realizing the request of writing data and reading data indicated by the Atomic request.

In the data processing system, the DUT is connected to the slave part as a master in the data processing system, and the slave comprises two VIPs, namely VIP 0 and VIP 1.

VIP 0 is configured to receive a first command from a DUT (e.g., an AXI bus based on AXI 5 protocol), and write target data carried by the first command into a Memory (Memory).

Or alternatively

And receiving a first atomic operation request from the DUT, and writing target data carried by the first atomic operation request into the Memory.

In an embodiment of the invention, the first Atomic operation request is, for example, an Atomic Load/computer/Swap request sent by the DUT to VIP 0 over the AW channel.

Optionally, the first command includes any one of:

a) A write data request. I.e., a write request sent by the DUT to VIP 0 over the AW channel.

B) And a second atomic operation request, which is used for instructing the VIP 0 to write the target data into the Memory.

Specifically, the second atomic operation request is, for example, atomicStore request.

VIP 1 for receiving a second command from the DUT; based on the second command, the target data or the history data is read from the Memory.

Optionally, the second command includes any one of:

a) And reading the data request. I.e., a read request sent by the DUT to VIP 1 over the AR channel.

B) A first atomic operation request. Such as an Atomic Load/computer/Swap request.

In the above data processing system, VIP 0 and VIP 1 need to respond to the general read-write request and the special Atomic request sent from the DUT. It should be noted that, the data bit widths of the first type channel and the second type channel corresponding to the DUT are different; the data bit widths of the first type channels corresponding to the VIP 0 and the VIP 1 are different, and the data bit widths of the second type channels corresponding to the VIP 0 and the VIP 1 are different; the first type channel comprises at least one of a write address channel, a write data channel and a write response channel, and the second type channel comprises at least one of a read address channel and a read data channel. In the scene that the data bit widths of the DUT read-write channels are inconsistent, the two VIPs are respectively used for processing read requests and write requests sent by the DUT.

For example, the DUT has a read data bit width of 2 kilobits (kilobit, kb) and a write data bit width of 1Kb; then VIP 0 has a data bit width of 2Kb for processing a read request from the DUT; VIP 1 has a data bit width of 1Kb for processing write requests from DUTs.

FIG. 2 is a second schematic diagram of a data processing system according to the present invention, in FIG. 2, VIP 0 and VIP 1 share the same Memory for solving the problem of read/write address consistency.

Specifically, if one Memory is configured for each of the two VIPs, when the addresses of the two VIP read requests and the addresses of the write requests are identical, the write requests are sent to VIP 0, the read requests are sent to VIP 1, and the two VIPs read and write data in different memories, the two VIPs may use the same address, but obtain data different from the expected one.

Therefore, VIP 0 and VIP 1 share the same Memory as the Memory space of two VIPs to store an address and data corresponding to the address. Optionally, the read-write data bit width of the Memory is the same as the data bit widths of the first type channel and the second type channel corresponding to VIP 0.

Taking the DUT as an AXI bus based on an AXI 5 protocol, wherein the read data bit width is 2Kb, and the write data bit width is 1Kb; the write data bit width of VIP 0 is 1Kb; VIP 1 has a read data bit width of 2Kb and memory has a data bit width of 1 Kb.

Alternatively, VIP 0 is particularly useful for any one of the following:

a) Receiving a write data request from a DUT; and writing target data carried in the data writing request into the Memory.

When the AXI bus is used as a master end to initiate a data writing request, the VIP 0 responds to the request, and a VIP built-in writing function is called in a slave sequence (slave_sequence) to write target data carried in the data writing request into a Memory.

It should be noted that, in practical application, the AXI bus will send the write data request to VIP 0 and VIP 1 at the same time, but VIP 1 does not perform any processing after receiving the write data request, and does not send a write response status (Bresp) signal.

B) Receiving a second atomic operation request from the DUT; and writing target data carried in the second atomic operation request into the Memory.

A second atomic operation request, such as AtomicStore request, the AXI bus sends AtomicStore requests to VIP 0 and VIP 1 simultaneously, at which point VIP 0 responds to the request and writes the target data carried in the AtomicStore request to the Memory.

Optionally, VIP 1 is specifically configured to perform the following steps:

Step 1), after the VIP 0 writes the target data carried in the data writing request into the Memory, receiving a second command from the DUT; the second command is a read data request;

Step 2), reading target data from the Memory based on the read data request;

Step 3), the target data is sent to the DUT.

Specifically, when the DUT initiates a read data request as master, VIP 0 will not respond to the request because it is not connected to the DUT's AR port.

VIP 1 responds to the read data request and fetches data from the Memory corresponding address and returns to the R channel. Since the Memory is 1Kb in data bit width and VIP 1 is 2Kb in data bit width, VIP 1 needs to access data of two adjacent addresses continuously when accessing the Memory, spells up 2Kb of target data, and returns to the R channel.

Optionally, in another implementation of the present invention, VIP 1 is specifically configured to perform the following steps:

Step 1), receiving a second command from the DUT, wherein the second command is a first atomic operation request;

Step 2), based on the first atomic operation request, reading historical data from the Memory;

Step 3), the historical data is sent to the DUT.

In an embodiment of the invention, the DUT makes a first Atomic operation request, such as an Atomic Load/computer/Swap request, to both VIP 0 and VIP 1.

At this time, VIP 0 does not process first after receiving an Atomic Load/computer/Swap request.

After receiving the request from the mobile Load/computer/Swap, VIP 1 parses the request to generate a request for reading the history data. VIP 1 then reads the history data from the Memory and returns to the R-channel to effect transmission of the history data to the DUT.

Optionally, VIP 0 is further specifically configured to perform the following steps:

after VIP 1 reads the history data from the Memory, the target data carried by the first atomic operation request is written into the Memory.

For example, VIP 0 does not process first after receiving an Atomic Load/complete/Swap request sent by the DUT. After VIP 1 reads the history data from the Memory, the target data carried by the Atomic Load/computer/Swap request is written to the Memory.

According to the data processing system provided by the invention, through mutually connecting the write address channel port, the write data channel port and the write response channel port corresponding to the DUT and the first VIP, the read address channel port and the read data channel port corresponding to the first VIP are suspended, and the first command or the target data carried by the first atomic operation request are written into the memory under the condition that the first VIP receives the first command or the first atomic operation request from the DUT; the DUT and a write address channel port, a write data channel port, a read address channel port and a read data channel port corresponding to the second VIP are connected with each other, and a write response channel port corresponding to the second VIP is suspended, so that target data or historical data is read from a memory under the condition that the second VIP receives a second command from the DUT; in the data processing system, the write request and the read request of the DUT are respectively realized by using the two VIPs with different data bit widths, namely, the first VIP can correctly receive target data sent by the DUT and correctly write the target data into the memory, and the second VIP can correctly read target data or history data required by the DUT from the memory, so that the data narrow transmission behavior caused by the condition that one VIP does not support inconsistent data bit widths of the DUT is avoided, and the problem that the DUT can still be verified by the VIP under the condition that the read-write data bit widths of the DUT are inconsistent is solved.

Fig. 3 is a schematic flow chart of a data processing method provided by the present invention. Referring to fig. 3, the method is applied to VIP 0, and includes step 301, wherein:

Step 301, receiving a first command from a DUT, and writing target data carried by the first command into a Memory;

Or alternatively

Receiving a first atomic operation request from a DUT; after VIP 1 reads the history data from the Memory and sends the history data to the DUT, writing the target data carried by the first atomic operation request into the Memory; wherein, the data bit widths of the first type channel and the second type channel corresponding to the DUT are different; the data bit widths of the first type channels corresponding to the VIP 0 and the second VIP 1 are different, and the data bit widths of the second type channels corresponding to the VIP 0 and the VIP 1 are different; the first type of channel includes at least one of a write address channel, a write data channel, and a write response channel, and the second type of channel includes at least one of a read address channel and a read data channel.

In an embodiment of the present invention, the first Atomic operation request is, for example, an Atomic Load/computer/Swap request.

The first command includes any one of the following:

a) A data writing request;

According to the data processing method provided by the invention, the VIP 0 only processes the data writing request from the DUT, so that the data narrow transmission behavior caused by the condition that one VIP does not support the inconsistency of the data bit width of the DUT is avoided, and the problem that the DUT can still be verified by the VIP under the condition that the read-write data bit width of the DUT is inconsistent is solved.

FIG. 4 is a second flow chart of the data processing method according to the present invention. Referring to fig. 4, the method is applied to VIP 1, and includes steps 401-402, wherein:

step 401, receiving a second command from the DUT;

Step 402, in the case that VIP 0 writes the target data into the Memory and the second command is a read data request, reading the target data from the Memory based on the read data request;

Or alternatively

In the case where the second command is a first atomic operation request, reading history data from the Memory based on the first atomic operation request; wherein, the data bit widths of the first type channel and the second type channel corresponding to the DUT are different; the data bit widths of the first type channels corresponding to the VIP 0 and the second VIP 1 are different, and the data bit widths of the second type channels corresponding to the VIP 0 and the VIP 1 are different; the first type of channel includes at least one of a write address channel, a write data channel, and a write response channel, and the second type of channel includes at least one of a read address channel and a read data channel.

According to the data processing method provided by the invention, the VIP 1 only processes the read data request from the DUT, so that the data narrow transmission behavior caused by the condition that one VIP does not support the inconsistency of the data bit width of the DUT is avoided, and the problem that the DUT can still be verified by the VIP under the condition that the read data bit width of the DUT is inconsistent is solved.

FIG. 5 is a schematic diagram of a signaling flow for data processing performed by the data processing system according to the present invention. FIG. 5 shows a signaling interaction diagram when the DUT sends write data requests to VIP 0 and VIP 1; wherein:

Step 1, a DUT sends a data writing request to VIP 0 and VIP 1; the target data is carried in the write data request.

And 2, responding to the data writing request by the VIP 0, and writing the target data into the Memory.

And 3, the DUT sends read data requests to the VIP 0 and the VIP 1.

And 4, in response to the read data request, the VIP 1 reads the target data from the Memory.

Step 5, the VIP 1 sends the target data to the DUT.

FIG. 6 is a second diagram illustrating a data processing signaling flow of the data processing system according to the present invention. FIG. 6 shows a signaling interaction diagram when the DUT sends a second atomic operation request to VIP 0 and VIP 1; wherein,

Step 1, the DUT sends a second atomic operation request to the VIP 0 and the VIP 1; the target data is carried in the second atomic operation request.

And 2, responding to a second atomic operation request by the VIP 0, and writing the target data into the Memory.

FIG. 7 is a third diagram illustrating a data processing signaling flow of the data processing system according to the present invention. FIG. 7 shows a signaling interaction diagram when the DUT sends a first atomic operation request to VIP 0 and VIP 1; wherein,

Step 1, a DUT sends a first atomic operation request to VIP 0 and VIP 1; the target data is carried in the first atomic operation request.

Specifically, the first Atomic operation request is, for example, an Atomic Load/complete/Swap request.

And 2, analyzing the first atomic operation request by the VIP 1 to generate a historical data reading request.

Step 3, based on the history data reading request, the VIP 1 reads the history data from the Memory.

Step 4, the VIP 1 sends the historical data to the DUT.

And 5, the VIP 0 writes target data carried in the atmospheric Load/complete/Swap request into the Memory.

And 6, the DUT sends read data requests to the VIP 0 and the VIP 1.

And 7, in response to the read data request, the VIP 1 reads the target data from the Memory.

Step 8, the VIP 1 sends the target data to the DUT.

The data processing apparatus provided by the present invention will be described below, and the data processing apparatus described below and the data processing method described above may be referred to correspondingly to each other. Fig. 8 is a schematic structural diagram of a data processing apparatus according to the present invention, and as shown in fig. 8, the data processing apparatus 800 is applied to VIP 0, and includes: a first receiving module 801, wherein:

a first receiving module 801, configured to receive a first command from a circuit DUT to be tested, and write target data carried by the first command into a memory;

receiving a first atomic operation request from the DUT;

In the data processing device provided by the invention, the first receiving module only processes the data writing request from the DUT, so that the data narrow transmission behavior caused by the condition that one VIP does not support the inconsistency of the data bit width of the DUT is avoided, and the problem that the DUT can still be verified by the VIP under the condition that the read-write data bit width of the DUT is inconsistent is solved.

Fig. 9 is a second schematic structural diagram of a data processing apparatus according to the present invention, as shown in fig. 9, the data processing apparatus 900 is applied to VIP 1, and includes: the second receiving module 901 and the reading module, wherein:

A second receiving module 901, configured to receive a second command from a circuit under test DUT;

a reading module 902, configured to, in a case where the first VIP writes target data to a memory and the second command is a read data request, read the target data from the memory based on the read data request;

Or alternatively

The data processing device provided by the invention only processes the read data request from the DUT, avoids the data narrow transmission behavior caused by the condition that one VIP does not support the inconsistency of the data bit width of the DUT, and solves the problem that the DUT can still be verified by the VIP under the condition that the read data bit width of the DUT is inconsistent.

Fig. 10 illustrates a physical structure diagram of an electronic device, as shown in fig. 10, which may include: processor 1010, communication interface (Communications Interface) 1020, memory 1030, and communication bus 1040, wherein processor 1010, communication interface 1020, and Memory 1030 communicate with each other via communication bus 1040. Processor 1010 may invoke logic instructions in memory 1030 to perform the data processing methods described above and illustrated in fig. 3 or 4.

Further, the logic instructions in the memory 1030 described above may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In another aspect, the present invention also provides a computer program product comprising a computer program storable on a non-transitory computer readable storage medium, the computer program being executable by a processor to perform the data processing method as shown in fig. 3 or fig. 4 described above.

In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the data processing method shown in fig. 3 or fig. 4 described above.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing system comprising a circuit under test DUT, a first validated intellectual property VIP, and a second VIP;

2. The data processing system of claim 1, wherein the read address channel port and the read data channel port corresponding to the first VIP are suspended and the write response channel port corresponding to the second VIP is suspended.

3. The data processing system of claim 1 or 2, wherein the first command comprises any one of:

A data writing request;

4. A data processing system according to claim 3, wherein the first VIP is configured to:

Or alternatively

5. A data processing system as claimed in claim 4, wherein the second VIP is operable, in particular, to:

reading the target data from the memory based on the read data request;

The target data is sent to the DUT.

6. The data processing system of claim 1, wherein the second VIP is configured to:

the historical data is sent to the DUT.

7. The data processing system of any one of claims 1,2 or 6, wherein the first VIP is specifically configured to:

Receiving the first atomic operation request from the DUT;

8. A data processing system according to claim 1 or claim 2, wherein the read and write data bit widths of the memory are the same as the data bit widths of the first and second type of channels corresponding to the first VIP.

9. A data processing method for application to a first authenticated intellectual property VIP, the method comprising:

Or alternatively

Receiving a first atomic operation request from the DUT;

10. A data processing method for application to a second authenticated intellectual property VIP, the method comprising:

receiving a second command from the circuit under test DUT;

Or alternatively

11. A data processing apparatus for application to a first authenticated intellectual property VIP, the apparatus comprising:

receiving a first atomic operation request from the DUT;

12. A data processing apparatus for application to a second authenticated intellectual property VIP, the apparatus comprising:

Or alternatively

13. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the data processing method according to claim 9 or 10 when executing the program.

14. A non-transitory computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the data processing method according to claim 9 or 10.

15. A computer program product comprising a computer program which, when executed by a processor, implements the data processing method according to claim 9 or 10.